An on-chip current acquisition circuit

Abstract

The present application relates to the technical field of current acquisition, in particular to a kind of in-chip current acquisition circuit, including chip acquisition current positive port, chip acquisition current negative port, first resistance, second resistance, off-chip sampling resistance, third resistance, operational amplifier, first current source, second current source.The size of first resistance and first current source can be controlled to realize current acquisition with consideration to small current acquisition and large current acquisition accuracy, and meet the requirements of different application scenarios for current acquisition accuracy.

Description

Technical Field

[0001] This invention relates to the field of current acquisition technology, and more specifically to an on-chip current acquisition circuit. Background Technology

[0002] On-chip current acquisition is an essential part of battery management chips and control chips. With the development of technology, the requirements for the accuracy of on-chip current acquisition are also getting higher and higher.

[0003] In existing technology, after the sampled current flows through the external sampling resistor, a voltage difference is generated between the positive and negative ports of the chip's current acquisition. This voltage difference is amplified by the on-chip operational amplifier, and then the amplified signal is sent to the on-chip analog-to-digital converter for processing. This technology achieves high accuracy when acquiring large currents; however, when acquiring small currents, even with amplification, the voltage value remains small, causing the operational amplifier's output stage to saturate. This results in the output voltage failing to accurately reflect the voltage difference across the external sampling resistor, leading to poor acquisition accuracy. Increasing the amplification factor allows the operational amplifier to function normally for small current acquisitions, but this results in an excessively high output voltage after acquiring large currents, further affecting the accuracy of large current acquisitions.

[0004] Therefore, it is essential to provide an on-chip current acquisition circuit that balances the accuracy of both small and large current acquisition. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides an on-chip current acquisition circuit.

[0006] The specific technical solution used by this invention to solve the above-mentioned technical problems is as follows:

[0007] An on-chip current acquisition circuit includes a positive current acquisition port CSP, a negative current acquisition port CSN, a first resistor R0, and a second resistor R. 0’ External sampling resistor R sense The third resistor R1, operational amplifier OP, voltage source VDD, first current source I0, and second current source I 0’ ;

[0008] The positive input port CSP of the chip is connected to the positive input terminal of the operational amplifier OP through the first resistor R0;

[0009] The chip's negative current acquisition port CSN is connected to a second resistor R. 0’ Connected to the negative input terminal of the operational amplifier OP;

[0010] External sampling resistor R sense It is connected between the positive current acquisition port CSP and the negative current acquisition port CSN of the chip to acquire changes in external current.

[0011] The third resistor R1 is connected between the output terminal and the negative input terminal of the operational amplifier OP;

[0012] Voltage source VDD is used to supply current to the first current source I0 and the second current source I. 0’ powered by;

[0013] The first current source I0 is connected between the first resistor R0 and the positive input terminal of the operational amplifier OP, and the second current source I... 0’ Connected to the second resistor R 0’ Between the negative input terminal of the operational amplifier (OP) and the on-chip current acquisition circuit, current is supplied to the positive and negative input terminals of the operational amplifier, thereby simultaneously raising the input voltage at both terminals.

[0014] Furthermore, the first resistor R0, the second resistor R 0’ It is made of the same material as the third resistor R1.

[0015] Furthermore, the first resistor R0 and the second resistor R 0’ The resistance values ​​are equal; the resistance value of the third resistor R1 is greater than or equal to the resistance value of the first resistor R0, that is, R1 ≥ R0 = R 0’ .

[0016] Furthermore, the voltage generated by the first current source I0 through the first resistor R0 is greater than the minimum output voltage required for the operational amplifier OP to operate in the amplification region.

[0017] Furthermore, the first current source I0 and the second current source I 0’ They are mirror images of each other.

[0018] Furthermore, the first current source I0 and the second current source I 0’ The specific implementation of the mirrored current sources is as follows: a current mirror is formed by a first P-type MOSFET PM0, a second P-type MOSFET PM1, and a third P-type MOSFET PM2. The current of the first P-type MOSFET PM0 comes from the on-chip current source I. S ;

[0019] The source of the first P-type MOSFET PM0 is connected to the voltage source VDD, and the drain of the first P-type MOSFET PM0 is connected to the on-chip current source I. S The gate and drain of the first P-type MOSFET PM0 are shorted.

[0020] The source of the second P-type MOSFET PM1 is connected to the voltage source VDD, and the drain of the second P-type MOSFET PM1 is connected between the first resistor R0 and the positive input terminal of the operational amplifier OP.

[0021] The source of the third P-type MOSFET PM2 is connected to the voltage source VDD, and the drain of the third P-type MOSFET PM2 is connected between the second resistor R1 and the negative input terminal of the operational amplifier OP.

[0022] The gate of the second P-type MOSFET PM1 is connected to the gate of the third P-type MOSFET PM2, and is also connected to the gate of the first P-type MOSFET PM0.

[0023] Furthermore, the width-to-length ratio of the second P-type MOSFET PM1 is equal to that of the third P-type MOSFET PM2, and the width-to-length ratio of the first P-type MOSFET PM0 is proportional to the width-to-length ratios of the second P-type MOSFET PM1 and the third P-type MOSFET PM2.

[0024] Furthermore, the ratio of the width-to-length ratio of the first P-type MOSFET PM0 to the width-to-length ratio of the second P-type MOSFET PM1 and the third P-type MOSFET PM2 is as follows: the width-to-length ratio of the second P-type MOSFET PM1 and the width-to-length ratio of the third P-type MOSFET PM2 are β times the width-to-length ratio of the first P-type MOSFET, where β > 0.

[0025] The present invention also provides a current acquisition chip, including the on-chip current acquisition circuit described in any of the above claims.

[0026] Compared with the prior art, the technical solution provided by this invention can achieve the following beneficial effects:

[0027] The accuracy of the on-chip current acquisition can be improved by adjusting the current source size, the resistance values ​​of the first and second resistors, and the β value.

[0028] It balances the accuracy of small current acquisition with that of large current acquisition, making it suitable for various application scenarios. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the circuit structure of an on-chip current acquisition circuit provided in an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of another on-chip current acquisition circuit provided in an embodiment of the present invention. Implementation

[0031] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0032] In one embodiment, such as Figure 1 As shown, an on-chip current acquisition circuit includes a positive current acquisition port CSP, a negative current acquisition port CSN, a first resistor R0, and a second resistor R 0’ External sampling resistor R senseThe third resistor R1, operational amplifier OP, voltage source VDD, first current source I0, and second current source I 0’ ;

[0033] The chip's positive current acquisition port CSP is connected to the positive input terminal of the operational amplifier OP through resistor R0;

[0034] The chip acquires current through the negative port CSN via resistor R. 0’ Connected to the negative input terminal of the operational amplifier OP;

[0035] External sampling resistor R sense It is connected between the positive current acquisition port CSP and the negative current acquisition port CSN of the chip to acquire changes in external current.

[0036] Resistor R1 is connected between the output terminal and the negative input terminal of operational amplifier OP;

[0037] Voltage source VDD is used to supply current to the first current source I0 and the second current source I. 0’ powered by;

[0038] The first current source I0 is connected between resistor R0 and the positive input terminal of operational amplifier OP, and the second current source I... 0’ Connected to resistor R 0’ Between the negative input terminal of the operational amplifier (OP), current is supplied to the on-chip current acquisition circuit to simultaneously raise the input voltages at both the positive and negative input terminals of the OP. The first current source I0 and the second current source I... 0’ It is a mirror current source.

[0039] First resistor R0, second resistor R 0’ Both the first resistor R0 and the third resistor R1 are made of the same material to offset the effects of temperature and process variations on the amplification factor. The first resistor R0 and the second resistor R... 0’ With equal resistance values, the resistance of the third resistor R1 is greater than or equal to that of the first resistor R0 and the second resistor R1. 0’ The resistance value, i.e., R1≥R0=R 0’ .

[0040] The voltage generated by the first current source I0 through the first resistor R0 is greater than the minimum voltage at which the operational amplifier OP operates in the amplification region.

[0041] When voltage source VDD supplies current source I0 to the on-chip current acquisition circuit, the voltage difference between the positive input terminal of the operational amplifier and the positive current acquisition port CSP of the chip is I0*R0, and the output voltage at this time is: V OUT = (I0*R0) + (1+R1 / R) 0’ )*V （CSP-CSN） Where 1+R1 / R 0’V is the magnification factor. （CSP-CSN） =Collected current * R sense Combining R1≥R0=R 0’ Therefore, the magnification is at least 2 times.

[0042] By adjusting the values ​​of I0 or R0, a suitable output voltage V can be obtained. OUT .

[0043] In this embodiment, the first resistor R0 and the second resistor R 0’ The first resistor R0 and the second resistor R1 are both made of the same material. 0’ The resistances of the first two resistors are equal, both being 20kΩ. The resistance of the third resistor, R1, is 380kΩ. Therefore, the amplification factor is (1 + R1 / R...). 0’ The value is 20 times; the external sampling resistor R sense The resistance is 10mΩ.

[0044] When the current being sampled is 0mA, I0 = I 0’ When the current is 10μA, the output voltage V of the on-chip current acquisition circuit is... OUT1 = (I0*R0) + (1+R1 / R) 0’ )*V (CSP-CSN) = (10μA*20kΩ)+20*(0mA*10mΩ)=200mV+0mV=200mV.

[0045] When the current being sampled is 50mA, I0 = I 0’ When the current is 10μA, the output voltage V of the on-chip current acquisition circuit is... OUT2 = (I0*R0) + (1+R1 / R) 0’ )*V (CSP-CSN) = (10μA*20kΩ)+20*(50mA*10mΩ)=200mV+10mV=210mV.

[0046] When the current being sampled is 100mA, I0 = I 0’ When the current is 10μA, the output voltage V of the on-chip current acquisition circuit is... OUT3 = (I0*R0) + (1+R1 / R) 0’ )*V (CSP-CSN) =(10μA*20kΩ)+20*(100mA*10mΩ)=200mV+20mV=220mV

[0047] Therefore, regardless of whether the current being sampled is 0mA, 50mA, or 100mA, the output voltage V of the current acquisition circuit within this chip remains constant. OUTAll are greater than 200mV, which is greater than the minimum output voltage that makes the operational amplifier (OP) operate in the amplification region. Generally, the minimum output voltage of the operational amplifier when it operates in the amplification region is 100mV.

[0048] In practical applications, the values ​​of I0 and R0 can be adjusted according to the application scenario of the on-chip current acquisition circuit, so that the output voltage of the on-chip current acquisition circuit is raised by a fixed value (I0*R0). As long as the value of (I0*R0) is greater than or equal to the minimum output voltage value when the operational amplifier OP is working in the amplification region, it can be guaranteed that the operational amplifier is working in the amplification region. In this way, the acquisition accuracy will not be affected regardless of whether the acquired current is large or small.

[0049] Furthermore, according to the above formula, when the resistance values ​​of each resistor in the on-chip current sampling circuit and the magnitude of the current source are known, but the magnitude of the sampled current is unknown, the magnitude can be determined by the change in output voltage, the amplification factor, and the external sampling resistor R. sense To calculate the sampling current.

[0050] Acquisition current = (V OUT2 -V OUT1 The amplification factor and the sampling resistance are calculated as (210mV-200mV) / 20 / 10mΩ, which gives the sampling current as 50mA.

[0051] In another embodiment, such as Figure 2 The on-chip current acquisition circuit shown includes a positive current acquisition port CSP, a negative current acquisition port CSN, a first resistor R0, and a second resistor R 0’ External sampling resistor R sense The third resistor R1, the operational amplifier OP, and the on-chip current source I S The first P-type MOSFET is PM0, the second P-type MOSFET is PM1, the third P-type MOSFET is PM2, and the voltage source is VDD;

[0052] The first resistor R0 and the second resistor R 0’ With equal resistance values, the resistance of the third resistor R1 is greater than or equal to that of the first resistor R0 and the second resistor R1. 0’ The resistance value;

[0053] The positive input port CSP of the chip is connected to the positive input terminal of the operational amplifier OP through the first resistor R0;

[0054] The chip's negative current acquisition port CSN is connected to a second resistor R. 0’ Connected to the negative input terminal of the operational amplifier OP;

[0055] External sampling resistor R senseIt is connected between the positive current acquisition port CSP and the negative current acquisition port CSN of the chip to acquire changes in external current.

[0056] The second resistor R1 is connected between the output terminal and the negative input terminal of the operational amplifier OP;

[0057] A current mirror is formed by a first P-type MOSFET PM0, a second P-type MOSFET PM1, and a third P-type MOSFET PM2. The current of the first P-type MOSFET PM0 comes from the on-chip current source I. S ;

[0058] The source of the first P-type MOSFET PM0 is connected to the voltage source VDD, and the drain of the first P-type MOSFET PM0 is connected to the on-chip current source I. S The gate and drain of the first P-type MOSFET PM0 are shorted.

[0059] The source of the second P-type MOSFET PM1 is connected to the voltage source VDD, and the drain of the second P-type MOSFET PM1 is connected between the first resistor R0 and the positive input terminal of the operational amplifier OP.

[0060] The source of the third P-type MOSFET PM2 is connected to the voltage source VDD, and the drain of the third P-type MOSFET PM2 is connected between the second resistor R1 and the negative input terminal of the operational amplifier OP.

[0061] The gate of the second P-type MOSFET PM1 is connected to the gate of the third P-type MOSFET PM2, and is also connected to the gate of the first P-type MOSFET PM0.

[0062] The width-to-length ratio of the first P-type MOSFET PM0 is proportional to the width-to-length ratio of the second P-type MOSFET PM1 and the third P-type MOSFET PM2.

[0063] The width-to-length ratio of the second P-type MOSFET PM1 is equal to that of the third P-type MOSFET PM2. The width-to-length ratio of the second P-type MOSFET PM1 and the third P-type MOSFET PM2 are β times the width-to-length ratio of the first P-type MOSFET PM0, where β > 0.

[0064] Current I S It is an on-chip current source, generated by VBG / R. s , where VBG is the on-chip bandgap voltage. R s To be related to the first resistor R0 and the second resistor R 0’ The third resistor R1 is a resistor of the same material.

[0065] Therefore, we can conclude that I0 = I 0’ =β*I S According to the formula: V OUT = (I0*R0) + (1+R1 / R)0’ )*V （CSP-CSN） By selecting an appropriate β value, the output voltage V can be controlled by controlling the magnitude of the first current source I0. OUT This ensures that the operational amplifier is in amplification mode.

[0066] In this embodiment, the first resistor R0 and the second resistor R 0’ The first resistor R0 and the second resistor R1 are both made of the same material. 0’ The resistance values ​​of all resistors are equal, both being 20kΩ, while the resistance of the third resistor R1 is 180kΩ; the external sampling resistor R... sense The resistance is 5mΩ; the width-to-length ratio of the second P-type MOSFET PM1 and the third P-type MOSFET PM2 is 3 times that of the first P-type MOSFET PM0, i.e., β=3; the current of the on-chip current source Is is 2.5μA.

[0067] It can be concluded that the first current source I0 and the second current source I 0’ The magnitude of the current is: I0 = I 0’ =β*I S =3*2.5μA=7.5μA.

[0068] When the current being sampled is 0mA, the output voltage V OUT4 = (I0*R0) + (1+R1 / R) 0’ )*V （CSP-CSN） =(7.5μA*20kΩ)+(1+180kΩ / 20kΩ)*(0mA*5mΩ)=150mV

[0069] When the current being sampled is 10mA, the output voltage V OUT5 = (I0*R0) + (1+R1 / R) 0’ )*V （CSP-CSN） =(7.5μA*20kΩ)+(1+180kΩ / 20kΩ)*(10mA*5mΩ)=150.5mV

[0070] When the current being sampled is 50mA, the output voltage V OUT6 = (I0*R0) + (1+R1 / R) 0’ )*V （CSP-CSN） =(7.5μA*20kΩ)+(1+180kΩ / 20kΩ)*(50mA*5mΩ)=152.5mV

[0071] Therefore, given that the resistance values ​​of each resistor in the on-chip current acquisition circuit are known, the first current source I0 and the second current source I can be adjusted by adjusting the β value. 0’Then, the output voltage is adjusted to raise the output voltage of the on-chip current acquisition circuit by a fixed value (I0*R0). As long as the value of (I0*R0) is greater than or equal to the minimum output voltage value when the operational amplifier OP is working in the amplification region, it can be guaranteed that the operational amplifier is working in the amplification region. In this way, the acquisition accuracy will not be affected regardless of whether the acquired current is large or small.

[0072] In another embodiment, the on-chip current acquisition circuit is located in the current acquisition chip and works with the processor and other peripheral circuits to realize current acquisition and corresponding signal processing.

[0073] The above embodiments are merely explanations and illustrations of the technical solutions of the present invention, and should not be construed as limiting the specific implementation methods of the present invention to these descriptions. For those skilled in the art, simple deductions or substitutions made without departing from the concept of the present invention still fall within the protection scope of the technical solutions of this application.

Claims

1. An on-chip current acquisition circuit, characterized in that, Includes a positive port for chip current acquisition, a negative port for chip current acquisition, a first resistor, a second resistor, an external sampling resistor, a third resistor, an operational amplifier, a voltage source, a first current source, and a second current source; The positive current acquisition port of the chip is connected to the positive input terminal of the operational amplifier through the first resistor; The negative input port of the chip for acquiring current is connected to the negative input terminal of the operational amplifier through the second resistor; The external sampling resistor is connected between the positive port of the chip's current acquisition and the negative port of the chip's current acquisition; The third resistor is connected between the output terminal and the negative input terminal of the operational amplifier; The voltage source is used to supply power to the first current source and the second current source; The first current source is connected between the first resistor and the positive input terminal of the operational amplifier, and the second current source is connected between the second resistor and the negative input terminal of the operational amplifier. It is used to provide current to the on-chip current acquisition circuit so that the input voltage of the positive input terminal and the negative input terminal of the operational amplifier rises simultaneously. The resistance values ​​of the first resistor and the second resistor are equal, and the resistance value of the third resistor is greater than or equal to the resistance value of the first resistor; The first current source and the second current source are mirror images of each other.

2. The on-chip current acquisition circuit according to claim 1, characterized in that, The first resistor, the second resistor, and the third resistor are made of the same material.

3. The on-chip current acquisition circuit according to claim 2, characterized in that, The voltage generated by the first current source through the first resistor is greater than the minimum output voltage required for the operational amplifier to operate in the amplification region.

4. The on-chip current acquisition circuit according to claim 3, characterized in that, The specific implementation of the first current source and the second current source being mirror images of each other is as follows: a current mirror is composed of a first P-type MOS transistor, a second P-type MOS transistor, and a third P-type MOS transistor, and the current of the first P-type MOS transistor comes from the on-chip current source. The source of the first P-type MOS transistor is connected to the voltage source, the drain of the first P-type MOS transistor is connected to the on-chip current source, and the gate and drain of the first P-type MOS transistor are shorted. The source of the second P-type MOS transistor is connected to the voltage source, and the drain of the second P-type MOS transistor is connected between the first resistor and the positive input terminal of the operational amplifier. The source of the third P-type MOS transistor is connected to the voltage source, and the drain of the third P-type MOS transistor is connected between the second resistor and the negative input terminal of the operational amplifier. The gate of the second P-type MOS transistor is connected to the gate of the third P-type MOS transistor, and is also connected to the gate of the first P-type MOS transistor.

5. The on-chip current acquisition circuit according to claim 4, characterized in that, The width-to-length ratio of the second P-type MOS transistor is equal to that of the third P-type MOS transistor; the width-to-length ratio of the first P-type MOS transistor is proportional to the width-to-length ratios of the second P-type MOS transistor and the third P-type MOS transistor.

6. The on-chip current acquisition circuit according to claim 5, characterized in that, The aspect ratio of the first P-type MOS transistor to the aspect ratio of the second P-type MOS transistor and the third P-type MOS transistor is as follows: the aspect ratio of the second P-type MOS transistor and the aspect ratio of the third P-type MOS transistor are β times the aspect ratio of the first P-type MOS transistor, where β > 0.

7. A current acquisition chip, characterized in that, Includes the on-chip current acquisition circuit as described in any one of claims 1 to 6.

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