Chip testing methods, systems, and SOC chips

Abstract

This application discloses a chip testing method, system, and SOC chip. The chip testing method includes the following steps performed by the chip under test: sending first test data to a testing device; obtaining second test data fed back by the testing device in response to the first test data; and testing the chip based on the second test data. This application enables the testing device to be applicable to the testing of different types of SOC chips, improving the compatibility and flexibility of the corresponding testing scheme.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a chip testing method, system, and SOC chip. Background Technology

[0002] USB (Universal Serial Bus) 2.0 is a high-speed serial interface technology widely used in SOC (system on chip). After SOC products are packaged, they need to undergo rigorous FT (Final Test) to ensure that the SOC products are fully functional and that their performance indicators meet the requirements.

[0003] Currently, the common testing methods for SOC chips supporting USB 2.0 DRP (Dual Role Port) are based on the product under test (DUT) acting as the booted device. This type of SOC chip testing solution often suffers from low compatibility and poor flexibility. Summary of the Invention

[0004] In view of this, this application provides a chip testing method, system and SOC chip to solve the problems of low compatibility and poor flexibility of existing SOC chip testing solutions.

[0005] This application provides a chip testing method, including the following steps performed by the chip under test:

[0006] S110, send the first test data to the test equipment;

[0007] S120, Obtain the second test data fed back by the test device in response to the first test data;

[0008] S130, Test this chip according to the second test data.

[0009] Optionally, step S130 includes:

[0010] If the second test data matches the first test data, then the current test is considered passed;

[0011] And / or, if the second test data exceeds the range of the first test data, adjust the physical characteristics of the first test data to update the first test data, return to step S110, until the number of times the second test data exceeds the range of the corresponding first test data reaches the first threshold, then determine that the current test has failed.

[0012] Optionally, after the current test passes, the chip testing method further includes the following steps performed by the chip under test:

[0013] S150, Receive the test data packet sent by the test device;

[0014] S160, Calculate the bit error rate based on the test data packet;

[0015] S170, if the bit error rate exceeds the preset bit error rate range, the current test is determined to have failed;

[0016] S180, if the bit error rate is within the bit error rate range, control the test device to adjust the physical characteristics of the test data packet to update the test data packet, return to step S150, until the number of times the bit error rate is within the bit error rate range reaches the second threshold, then determine that the current test has passed.

[0017] Optionally, prior to step S150, the chip testing method further includes the following steps performed by the chip under test:

[0018] S140, a test bit error rate notification message is sent to the test device, so that the test device sends the specified test data packet to the chip under test.

[0019] Optionally, the notification message carries the physical characteristics of the test data packet; step S180 includes:

[0020] If the bit error rate is within the bit error rate range, update the notification message and return to step S140 until the number of times the bit error rate is within the bit error rate range reaches the second threshold, then determine that the current test has passed.

[0021] Optionally, after the current test passes, the chip testing method further includes the following steps performed by the chip under test:

[0022] Update the first test data according to the test requirements, and return to the execution step S110.

[0023] Optionally, prior to step S110, the chip testing method further includes the following steps performed by the chip under test:

[0024] The chip shakes hands with the test device to obtain the first data transmission speed of the test device and determines the corresponding second data transmission speed, which is used to limit the speed at which the chip sends data to the test device during the test.

[0025] Optionally, prior to step S110, the chip testing method further includes the following steps performed by the chip under test:

[0026] Enumerate the test devices to obtain their communication description information, and send data to the test devices within the range corresponding to the communication description information.

[0027] This application also provides a chip testing system.

[0028] This includes a transmitting module, an acquiring module, and a testing module located on the chip under test:

[0029] The sending module is used to send the first test data to the test equipment;

[0030] The acquisition module is used to acquire the second test data fed back by the test device in response to the first test data;

[0031] The test module is used to test the chip based on the second test data.

[0032] This application also provides a SOC chip, including an arithmetic circuit; the arithmetic circuit is used to perform any of the chip testing methods described above.

[0033] In the chip testing method, system, and SOC chip provided in this application, the chip under test (DUT) acts as the leading device. When it needs to be tested, it sends first test data to the testing device for testing itself. The testing device only needs to feed back second test data based on the first test data, enabling the DUT to obtain the second test data and perform its own testing. During the above testing process, the DUT can determine the test data (such as the first test data) and corresponding test rules according to its own testing needs, so that the corresponding test process matches its own configuration and / or functional characteristics, which can improve the adaptability of the corresponding test scheme. Moreover, the testing device performs relatively simple responses such as data feedback under the leadership of the DUT, without needing to adjust the driver and / or test process configuration information for different types of DUTs, effectively simplifying the testing work on the testing device side. This makes the testing device applicable to the testing of various SOC chips, improving the compatibility and utilization of the testing device and enhancing the flexibility of the corresponding test scheme.

[0034] Furthermore, this application employs a chip testing method where the chip under test (DUT) acts as the primary device, connecting to external testing equipment (such as a standard USB 2.0 device) to enable testing of the DUT itself. For different types of SOC chips, the testing equipment setup does not need to be changed as the SOC chip to be tested changes. The DUT can adjust the first test data and other test content according to its own needs at different times, so as to balance the accuracy and efficiency of testing processes such as FT testing. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic flowchart of a chip testing method according to an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the connection relationship between the chip under test and the test equipment in one embodiment of this application;

[0038] Figure 3 This is a schematic flowchart of a chip testing method according to another embodiment of this application;

[0039] Figure 4 This is a schematic diagram of a chip testing system according to an embodiment of this application. Detailed Implementation

[0040] During their research, the inventors discovered that in traditional SOC chip testing schemes, the test equipment acts as the master device, while the SOC chip under test (DUT) is often a passive device (guided by the test equipment). In such a testing system, to meet the different requirements of the DUT, not only is it necessary to debug the DUT's software, but also to update the test equipment's drivers according to the DUT's testing requirements and hardware changes. Furthermore, if the DUT's testing requirements change, the test equipment's drivers must also be updated accordingly. Based on these considerations, testing systems where the DUT acts as the guided device have poor compatibility and operability, resulting in low flexibility in the chip testing process.

[0041] To address this issue, the chip testing method, system, and SOC chip provided in this application utilize a chip under test (DUT) as the primary device. When DUT needs to perform testing, it sends first test data to the testing equipment. The testing equipment then only needs to provide second test data based on the first test data, enabling DUT to acquire the second test data and perform its own testing. During this testing process, DUT can determine the test data (such as the first test data) and corresponding test rules based on its own testing requirements, ensuring that the testing process matches its own configuration and / or functional characteristics. This improves the adaptability of the testing scheme. Furthermore, the testing equipment, under the guidance of DUT, provides relatively simple responses such as data feedback, eliminating the need to adjust driver and / or test process configurations for different types of DUTs. This effectively simplifies the testing work on the testing equipment side, making the testing equipment applicable to testing various SOC chips, improving the compatibility and utilization of the testing equipment, and enhancing the flexibility of the testing scheme.

[0042] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0043] The first aspect of this application provides a chip testing method, which can be applied to SOC chips that require SLT (System Level Test); see reference Figure 1 As shown, the above chip testing method includes the following steps performed by the chip under test:

[0044] S110, send the first test data to the test equipment.

[0045] like Figure 2 As shown, the chip under test (DUT) and the test equipment can communicate with each other, enabling the DUT to send data to the test equipment and receive feedback data from the test equipment for testing. Specifically, the DUT and the test equipment typically each have corresponding USB interfaces, and they can be synchronized through a controllable USB communication protocol to ensure the reliability of the communication process.

[0046] Specifically, after the test equipment is powered on, it can run firmware and other initialization programs, waiting for the chip under test (DUT) to connect. After the DUT is powered on, it can connect to the test equipment at the corresponding test time. After handshaking and / or enumeration and other pre-test interactions with the test equipment, it sends first test data to the test equipment, so that the test equipment can generate second test data for testing the DUT based on the first test data.

[0047] S120, Obtain the second test data fed back by the test device in response to the first test data.

[0048] S130, Test this chip according to the second test data.

[0049] After acquiring the second test data, the chip under test can determine the test result according to the test rules corresponding to the chip. For example, for some SOC chips, if the second test data is consistent with the first test data, it means that the current test has passed; if it is inconsistent with the first test data, it means that the test has failed. For other chips, if the second test data is within a certain range, it means that the current test has passed; if it is outside that range, it means that the test has failed, and so on.

[0050] In the above chip testing method, the chip under test (DUT) acts as the master device. When the DUT needs to be tested, it sends first test data to the testing device. The testing device only needs to feed back second test data based on the first test data, which enables the DUT to obtain the second test data and test itself. In this way, the testing device can be applied to the testing of different types of SOC chips, and has high compatibility and flexibility.

[0051] In one embodiment, step S130 includes:

[0052] If the second test data matches the first test data, then the current test is considered passed;

[0053] And / or, if the second test data exceeds the range of the first test data, adjust the physical characteristics of the first test data to update the first test data, return to step S110, until the number of times the second test data exceeds the range of the corresponding first test data reaches the first threshold, then determine that the current test has failed.

[0054] Here, "matching the second test data with the first test data" can mean that the second test data and the first test data are completely identical, or it can mean that the difference between the second test data and the first test data is within a preset difference range. This embodiment compares the second test data with the first test data to detect whether the current test has passed. It eliminates the need for other test parameters, simplifying the testing process and improving test stability.

[0055] The threshold value for the first test can be set according to the test precision, for example, it can be set to 3. Specifically, the physical characteristics of the first test data include parameters characterizing the waveform corresponding to the first test data; changing the physical characteristics of the first test data can change the waveform corresponding to the first test data, so as to avoid the problem of incompatibility between the first test data and the test equipment causing interference in the test process of the chip under test, thereby updating the first test data, reducing the probability of incompatibility between the first test data and the test equipment, and improving the stability of the entire test process.

[0056] SLT testing typically includes at least one level of testing, each with its own objective. For example, the first level of testing might involve data transmission between the chip under test (DUT) and the testing equipment, comparing the data before and after transmission to obtain the test result. The second level of testing might involve data transmission between the DUT and the testing equipment, calculating the bit error rate (BER) to obtain the corresponding test result, and so on. This allows for a more comprehensive test of the DUT. In one example, after the current test passes, the chip testing method further includes the following steps performed by the DUT:

[0057] S150, Receive the test data packet sent by the test device;

[0058] S160, Calculate the bit error rate based on the test data packet;

[0059] S170, if the bit error rate exceeds the preset bit error rate range, the current test is determined to have failed;

[0060] S180, if the bit error rate is within the bit error rate range, control the test device to adjust the physical characteristics of the test data packet to update the test data packet, return to step S150, until the number of times the bit error rate is within the bit error rate range reaches the second threshold, then determine that the current test has passed.

[0061] The aforementioned bit error rate range can be set based on characteristics such as the data length of the test data packet and / or the required test accuracy of the chip under test. In many tests, a lower bit error rate indicates better chip performance. This example performs bit error rate testing on the chip under test after the previous test is passed, allowing for a more comprehensive test and improving the reliability of the test results.

[0062] The aforementioned second threshold can be set according to the corresponding test precision, such as a value of 3. The physical characteristics of the test data packet include parameters that limit the content of the test data packet. The chip under test (DUT) controls the test equipment to adjust the physical characteristics of the test data packet, which can update the content of the test data packet, allowing the DUT to calculate the bit error rate (BER) based on multiple different test data packets, thus improving the reliability of the obtained BER. When the number of consecutive BER values ​​within the BER range reaches the second threshold, the current test is considered passed, further improving the reliability of the corresponding test process. Optionally, the test data packet is a data packet used to calculate the chip's BER. When the DUT needs to obtain the corresponding BER, it can send a relevant notification message to the test equipment, allowing the test equipment to promptly provide a test data packet. The DUT can then calculate the BER based on the received test data packet. Optionally, the notification message used to notify the test equipment to send the test data packet can carry additional messages that limit the physical characteristics of the test data packet, allowing the test equipment to send the test data packet limited by the DUT according to these additional messages. This enables the DUT to quickly calculate the BER based on the test data packet and its limited physical characteristics.

[0063] In one example, prior to step S150, the chip testing method further includes the following steps performed by the chip under test:

[0064] S140, a test bit error rate notification message is sent to the test device, so that the test device sends the specified test data packet to the chip under test.

[0065] This example sends a test bit error rate notification message to the test equipment, so that the test equipment sends a specified test data packet to the chip under test. The chip under test can then compare the specified test data packet with the reference data packet that matches the notification message. By statistically analyzing the data that does not match, the bit error rate in the current test process can be calculated to ensure the accuracy of the obtained bit error rate.

[0066] Furthermore, the notification message carries the physical characteristics of the test data packet; step S180 includes:

[0067] If the bit error rate is within the bit error rate range, update the notification message and return to step S140 until the number of times the bit error rate is within the bit error rate range reaches the second threshold, then determine that the current test has passed.

[0068] Here, the chip under test updates the notification message, returns to step S140, and sends a new notification message to the test device, so that the test device can send back a test data packet matching the new notification message to the chip under test, enabling the chip under test to take control of the entire test process.

[0069] In one example, after the current test passes, the chip testing method further includes the following steps performed by the chip under test:

[0070] Update the first test data according to the test requirements, return to the execution step S110, and send the first test data to the test device.

[0071] Optionally, the chip under test (DUT) can reset the content, length, and / or format of the first test data according to its current testing requirements to update the first test data. The updated first test data has a higher degree of matching with the subsequent tests to be carried out, so when the DUT returns to step S110 and sends the first test data to the test equipment, it can continue to perform effective testing.

[0072] In one embodiment, before entering the formal testing process, the chip under test can first perform pre-test communication tasks such as handshake and / or enumeration with the test equipment to determine the reliability of the communication link between the two and ensure the stability of subsequent testing. It can also obtain information required for the testing process, such as the configuration information of the test equipment, so as to determine the characteristics of various data that need to be sent to the test equipment in subsequent testing, so that the various data sent to the test equipment are matched with the test equipment, which can further improve the reliability of the testing process.

[0073] In one example, prior to step S110, the chip testing method further includes the following steps performed by the chip under test: handshaking with the test device to obtain a first data transmission speed of the test device, and determining a corresponding second data transmission speed, wherein the second data transmission speed is used to limit the speed at which the chip sends data to the test device during the test, such as the speed at which the first test data is sent, so that the speed at which the chip under test sends data to the test device matches the first data transmission speed of the test device, thereby ensuring the stability of the chip under test when sending data to the test device.

[0074] In another example, prior to step S110, the chip testing method further includes the following steps performed by the chip under test: enumerating with the test device to obtain communication description information of the test device, and sending data to the test device within the range corresponding to the communication description information. The aforementioned communication description information may include information related to the testing process, such as the communication protocol, configuration features, and / or functional features of the test device. After obtaining the communication description information of the test device, the chip under test can adjust the size and other characteristics of various types of data (such as first test data) that need to be sent to the test device during the testing process, so that after receiving the data sent by the chip under test, the test device can reliably process these data to obtain corresponding feedback data (such as second test data corresponding to the first test data), and smoothly feed this feedback data back to the chip under test, enabling the chip under test to accurately obtain the corresponding test results.

[0075] Optionally, the chip testing method further includes the following steps performed by the chip under test: if the chip under test fails to handshake with the testing device, the current test is determined to have failed; and / or, if the chip under test fails to enumerate with the testing device, the current test is determined to have failed. After determining that the current test has failed, the testing process can be exited to avoid occupying the resources related to the testing device, allowing the testing device to be used for testing other SOC chips, thereby further improving the utilization rate of the testing device.

[0076] In one example, both the first and second threshold numbers are 3. The chip testing method's procedure in the specific SLT testing process can also be referenced. Figure 3 As shown, it includes:

[0077] S511, the test equipment is powered on and running firmware, waiting for the chip under test to connect;

[0078] S512, the chip under test is powered on and connected to the test equipment to perform handshake and enumeration;

[0079] S513, the chip under test determines whether the handshake and enumeration are completed normally; if yes, proceed to step S514; if no, proceed to step S524.

[0080] S514, the chip under test (DUT) and the test equipment perform test data transmission; this step specifically includes: the DUT sends first test data to the test equipment, the test equipment receives the first test data, sends second test data to the DUT, and the DUT receives and compares the second test data with the first test data;

[0081] S515, the chip under test determines whether the data is normal; if yes, proceed to step S516; otherwise, proceed to step S531; specifically, if the second test data is consistent with the first test data, it indicates that the data is correct; if the second test data is inconsistent with the first test data, it indicates that the data is incorrect.

[0082] S531, the chip under test determines that the data comparison error has occurred 3 times consecutively; if yes, proceed to step S524; otherwise, proceed to step S532.

[0083] S532, the chip under test adjusts the physical characteristics of the test data to update the test data transmitted between the chip and the test equipment, and returns to step S514.

[0084] S516, the chip under test sends a notification message to the test equipment;

[0085] S517, the test data packet corresponding to the notification message sent by the test equipment to the chip under test;

[0086] S518, the chip under test calculates the bit error rate based on the test data packet; this step specifically includes: the chip under test calculates the bit error rate based on the pre-stored reference data packet and test data packet;

[0087] S519, the chip under test determines whether the bit error rate meets the requirements; if yes, proceed to step S521, otherwise proceed to step S524; this step specifically includes: determining whether the bit error rate exceeds the corresponding bit error rate range (such as being less than a certain threshold range); if the bit error rate does not exceed the corresponding bit error rate range, the bit error rate is determined to meet the requirements; if the bit error rate exceeds the corresponding bit error rate range, the bit error rate is determined to not meet the requirements.

[0088] S521, the chip under test determines whether the number of times the bit error rate has reached the requirement has exceeded 3 times; if yes, proceed to step S522; if no, proceed to step S523.

[0089] S522, the chip under test has passed the SLT test;

[0090] S523, the chip under test is updated with a notification message to control the test equipment to update the test data packet, and the process returns to step S516.

[0091] S524, the chip under test has determined that the SLT test of this chip has failed.

[0092] In the chip under test (DUT), as SLT test results accumulate over time, when FT test requirements change, the DUT takes the lead in controlling data transmission. Only the configuration and / or related software on the DUT side need to be modified according to the requirements, adjusting the amount and / or format of transmitted data, while the test equipment remains unchanged. This ensures both test accuracy and test efficiency. Optionally, such as... Figure 3 As shown, after step S522, the above chip testing method may further include:

[0093] S525, the chip under test adjusts the length and format of the transmitted data according to the test requirements, and returns to step S514 to enter the next round of SLT test according to the test requirements of the chip under test.

[0094] In the multi-round SLT test provided in this example, the test equipment only needs to respond to the data and / or notification messages sent by the chip under test, without needing to adjust the driver and / or other configuration information. This effectively simplifies the testing work at the test equipment, improves the utilization rate of the test equipment, and enhances the compatibility and flexibility of the test equipment in multi-round testing and / or multi-type SOC chip testing.

[0095] In the above chip testing method, the chip under test (DUT) acts as the leading device. When it needs to be tested, it sends first test data to the testing equipment. The testing equipment only needs to feed back second test data based on the first test data, enabling the DUT to obtain the second test data and perform its own testing. During the testing process, the DUT can determine the test data (such as the first test data) and corresponding test rules according to its own testing needs, so that the corresponding test process matches its own configuration and / or functional characteristics. This can improve the adaptability of the corresponding test scheme. Moreover, the testing equipment performs relatively simple responses such as data feedback under the leadership of the DUT, without needing to adjust the driver and / or test process configuration information for different types of DUTs. This effectively simplifies the testing work on the testing equipment side, making the testing equipment applicable to the testing of various SOC chips, improving the compatibility and utilization of the testing equipment, and enhancing the flexibility of the corresponding test scheme. Furthermore, using this chip testing method, the chip under test (DUT) acts as the primary device, connecting to external testing equipment (such as a standard USB 2.0 device) to perform testing on the DUT itself. For different types of SOC chips, the testing equipment setup does not need to be changed as the SOC chip to be tested changes. The DUT can adjust the test content, such as the initial test data, according to its own needs at different times, to ensure the accuracy and efficiency of testing processes such as FT testing.

[0096] This application provides a chip testing system in a second aspect. This chip testing system can be installed on a System-on-a-Chip (SoC), for example, as a USB 2.0 DRP module of the SoC, allowing the SoC to lead the testing process with the corresponding testing equipment. (Reference) Figure 4 As shown, the chip testing system described above includes:

[0097] The sending module 110 is used to send the first test data to the test equipment;

[0098] The acquisition module 120 is used to acquire the second test data fed back by the test device in response to the first test data;

[0099] Test module 130 is used to test the chip based on the second test data.

[0100] For specific limitations regarding the chip testing system, please refer to the limitations on chip testing methods mentioned above, which will not be repeated here. Each module in the aforementioned chip testing system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the computing module in the computer device, or stored in software in the computer device's memory, so that the computing module of the computer device can call and execute the operations corresponding to each module.

[0101] This application provides a third aspect of a SOC chip, including a computing circuit; the computing circuit is used to execute the chip testing method described in any of the above embodiments.

[0102] The aforementioned SOC chip and testing equipment can communicate with each other, enabling the SOC chip to send data to the testing equipment and receive feedback data from the testing equipment, thus controlling each stage of the testing process and realizing the testing of the chip under test at various levels. Specifically, the chip under test and the testing equipment typically each have corresponding USB interfaces, and they can be synchronized through a controllable USB communication protocol to ensure the reliability of the communication process.

[0103] The aforementioned SOC chip uses the chip testing method provided in any of the above embodiments to perform its own testing. During the testing process, the SOC chip acts as the main device and connects to external testing equipment (such as a standard USB 2.0 device) to achieve its own testing. For different types of SOC chips, the testing equipment does not need to be changed as the SOC chip to be tested changes. The SOC chip can adjust the test content, such as the first test data, according to its own needs at different times, so as to balance the accuracy and efficiency of testing processes such as FT testing and improve the flexibility of related testing work.

[0104] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0105] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0106] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0107] The above description has been provided to enable any person skilled in the art to implement and use this application. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A method of testing a chip, characterized by, A chip test system is arranged on the to-be-tested chip, and the chip test system is used as a USB2.0 DRP module of the to-be-tested chip to enable the to-be-tested chip to lead the test work between the to-be-tested chip and a corresponding test device. The chip test method includes the following steps performed by the to-be-tested chip. S110, sending first test data to the test device; S120, obtaining second test data fed back by the test device for the first test data; S130, testing the chip according to the second test data.

2. The chip testing method according to claim 1, wherein Step S130 includes: If the second test data matches the first test data, it is determined that the current test is passed. And / or, if the second test data exceeds the range of the first test data, the physical characteristics of the first test data are adjusted to update the first test data, and step S110 is returned to be executed until the number of times that the second test data continuously exceeds the range of the corresponding first test data reaches a first number threshold, and it is determined that the current test is failed.

3. The chip testing method according to claim 2, wherein After the current test is passed, the chip test method further includes the following steps performed by the to-be-tested chip: S150, receiving a test data packet sent by the test device; S160, calculating a bit error rate according to the test data packet; S170, if the bit error rate exceeds a preset bit error rate range, it is determined that the current test is failed; S180, if the bit error rate is within the bit error rate range, the test device is controlled to adjust the physical characteristics of the test data packet to update the test data packet, and step S150 is returned to be executed until the number of times that the bit error rate continuously falls within the bit error rate range reaches a second number threshold, and it is determined that the current test is passed.

4. The chip testing method according to claim 3, wherein Before step S150, the chip test method further includes the following steps performed by the to-be-tested chip: S140, sending a notification message of a test bit error rate to the test device to enable the test device to send a specified test data packet to the to-be-tested chip.

5. The chip testing method according to claim 4, wherein The notification message carries the physical characteristics of the test data packet; and step S180 includes: If the bit error rate is within the bit error rate range, the notification message is updated, and step S140 is returned to be executed until the number of times that the bit error rate continuously falls within the bit error rate range reaches a second number threshold, and it is determined that the current test is passed.

6. The method of claim 3, wherein After the current test is passed, the chip test method further includes the following steps performed by the to-be-tested chip: The first test data is updated according to a test requirement, and step S110 is returned to be executed.

7. The method of claim 1, wherein Before step S110, the chip test method further includes the following steps performed by the to-be-tested chip: Handshaking with the test device to obtain a first data transmission speed of the test device and determine a corresponding second data transmission speed, the second data transmission speed being used to limit the speed of sending data by the to-be-tested chip to the test device in the test process.

8. The method of claim 1, wherein Before step S110; the chip testing method further includes the following steps executed by the chip to be tested: Enumerating with the testing device to obtain communication description information of the testing device, and sending data to the testing device within a range corresponding to the communication description information.

9. A chip testing system, characterized by comprising: The chip testing system is used for executing the chip testing method as claimed in any one of claims 1 to 8, comprising a sending module, an obtaining module and a testing module arranged on the chip to be tested, and the chip to be tested performs communication work with the testing device before entering formal testing work to determine the reliability of the communication link therebetween; The sending module is used for sending first testing data to the testing device; The obtaining module is used for obtaining second testing data fed back by the testing device in response to the first testing data; The testing module is used for testing the chip according to the second testing data.

10. A SOC chip, characterized by, The chip testing system comprises an operation circuit, and the operation circuit is used for executing the chip testing method as claimed in any one of claims 1 to 8.

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