Test circuit and working method thereof

Abstract

A test circuit and operating method thereof, wherein the test circuit includes: an address decoder, the address decoder including: several address input terminals and several address output terminals; a first inverter, the first inverter including: a first input terminal connected to the address output terminal and a first output terminal; an enable selection module, the enable selection module including: a second input terminal connected to the address output terminal, a third input terminal connected to the first output terminal, an enable input terminal, a second output terminal, and a third output terminal; a resistance test module, the resistance test module including: a fourth input terminal connected to the address output terminal, a fifth input terminal connected to the first output terminal, a sixth input terminal connected to the second output terminal, a seventh input terminal connected to the third output terminal, a fourth output terminal, and a device under test module; and a capacitance test module, the capacitance test module including: an eighth input terminal connected to the fourth output terminal. This ensures that resistance and capacitance can be tested on the same test circuit structure and that more devices can be tested.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a test circuit and a working method thereof. Background Art

[0002] In the resistance and capacitance testing of integrated circuits, the resistance and capacitance are usually distributed in different test structures, that is, the resistance test circuit and the capacitance test circuit are separate.

[0003] However, this method results in the actual resistance and capacitance values being obtained at different locations and in different test structures, failing to reflect the correlation between resistance and capacitance. Furthermore, due to the limited number of test probes available for each test, this method can only test a small number of devices under test at a time. Summary of the Invention

[0004] The technical problem solved by the present invention is a test circuit and its working method, which can simultaneously realize the resistance and capacitance testing of the same structure to achieve the purpose of truly reflecting the relationship between the processes, and at the same time provide address selection for the device to be tested, thereby increasing the number of testable devices under the same area.

[0005] To solve the above technical problems, the technical solution of the present invention provides a test circuit, comprising: an address decoder, the address decoder comprising: a plurality of address input terminals and a plurality of address output terminals; a first inverter, the first inverter comprising: a first input terminal connected to the address output terminal, and a first output terminal; an enable selection module, the enable selection module comprising: a second input terminal connected to the address output terminal, a third input terminal connected to the first output terminal, an enable input terminal, a second output terminal, and a third output terminal; a resistance testing module, the resistance testing module comprising: a fourth input terminal connected to the address output terminal, a fifth input terminal connected to the first output terminal, a sixth input terminal connected to the second output terminal, a seventh input terminal connected to the third output terminal, a fourth output terminal, and a device under test module; and a capacitance testing module, the capacitance testing module comprising an eighth input terminal connected to the fourth output terminal.

[0006] Optionally, the enable selection module further includes: a second inverter, wherein the input end of the second inverter is connected to the enable input end; a third inverter, wherein the input end of the third inverter is connected to the output end of the second inverter; a first transmission gate, wherein the first switch end of the first transmission gate is connected to the output end of the second inverter, the signal input end of the first transmission gate is connected to the second input end of the enable selection module, and the signal output end of the first transmission gate is connected to the second output end of the enable selection module; a second transmission gate, wherein the first switch end of the second transmission gate is connected to the second switch end of the first transmission gate and to the output end of the third inverter, the second switch end of the second transmission gate is connected to the output end of the second inverter, the signal input end of the second transmission gate is connected to the third input end of the enable selection module, and the signal output end of the second transmission gate is connected to the signal output end of the first transmission gate; and a fourth inverter, wherein the input end of the fourth inverter is connected to the signal output end of the second transmission gate, and the output end of the fourth inverter is connected to the third output end of the enable selection module.

[0007] Optionally, the resistance testing module further includes: a third transmission gate, wherein the first switch end of the third transmission gate is connected to the fourth input end, the second switch end of the third transmission gate is connected to the fifth input end, and the signal output end of the third transmission gate is connected to the first end of the device under test module; a fourth transmission gate, wherein the first switch end of the fourth transmission gate is connected to the sixth input end, the second switch end of the fourth transmission gate is connected to the seventh input end, and the signal output end of the fourth transmission gate is connected to the first end of the device under test module; a fifth transmission gate, wherein the first switch end of the fifth transmission gate is connected to the sixth input end, the second switch end of the fifth transmission gate is connected to the seventh input end, and the signal output end of the fifth transmission gate is connected to the second end of the device under test module; a sixth transmission gate, wherein the first switch end of the sixth transmission gate is connected to the sixth input end, and the second switch end of the sixth transmission gate is connected to the seventh input end; and the third end of the device under test module is connected to the fourth output end.

[0008] Optionally, the address input end includes: several chip select address input ends and several region address input ends; the address output end includes: several chip select valid output ends corresponding to the chip select address input ends and several region valid output ends corresponding to the region address input ends.

[0009] Optionally, the device under test module includes several chip select modules corresponding to the chip select valid output terminal, each chip select module includes several regional modules corresponding to the regional valid output terminal, and each regional module is used to couple to the device under test.

[0010] Optionally, the capacitance testing module is a QVCM capacitance testing circuit, and the capacitance testing module further includes a plurality of testing terminals.

[0011] Accordingly, the technical solution of the present invention provides a working method of a test circuit, comprising: providing a test circuit, wherein the test circuit comprises: an address decoder comprising: an address decoder comprising: a plurality of address input terminals and a plurality of address output terminals; a first inverter comprising: a first input terminal connected to the address output terminal, and a first output terminal; an enable selection module comprising: a second input terminal connected to the address output terminal, a third input terminal connected to the first output terminal, an enable input terminal, a second output terminal, and a third output terminal; a resistance test module, wherein the resistance The test module includes: a fourth input terminal connected to the address output terminal, a fifth input terminal connected to the first output terminal, a sixth input terminal connected to the second output terminal, a seventh input terminal connected to the third output terminal, a fourth output terminal, and a device under test module; a capacitance test module, wherein the capacitance test module includes an eighth input terminal connected to the fourth output terminal; a first signal group is input from the several address input terminals of the address decoder to perform a device selection step; an enable signal is input from the enable input terminal of the enable selection module to perform a function selection step; and a test step is performed after the device selection step and the function selection step.

[0012] Optionally, the address input end includes: several chip select address input ends and several region address input ends; the address output end includes: several chip select valid output ends corresponding to the chip select address input ends and several region valid output ends corresponding to the region address input ends.

[0013] Optionally, the device under test module includes several chip select modules corresponding to the chip select valid output terminal, each chip select module includes several regional modules corresponding to the regional valid output terminal, and each regional module is used to couple to the device under test.

[0014] Optionally, the first signal group includes a chip select address signal input from the chip select address input end and a region address signal input from the region address input end, and the device selection step includes: after the address input end obtains the first signal group, the address output end outputs a second signal group, the second signal group includes a chip select valid signal corresponding to the chip select address signal output from the chip select valid output end, and a region valid signal corresponding to the region address signal output from the region valid output end; according to the second signal group input from the first end of the device under test module, the device under test in the region module corresponding to the chip select module corresponding to the chip select valid signal and the region valid signal corresponding to the region valid signal are selected.

[0015] Optionally, the enable selection module further includes: a second inverter, wherein the input end of the second inverter is connected to the enable input end; a third inverter, wherein the input end of the third inverter is connected to the output end of the second inverter; a first transmission gate, wherein the first switch end of the first transmission gate is connected to the output end of the second inverter, the signal input end of the first transmission gate is connected to the second input end of the enable selection module, and the signal output end of the first transmission gate is connected to the second output end of the enable selection module; a second transmission gate, wherein the first switch end of the second transmission gate is connected to the second switch end of the first transmission gate and to the output end of the third inverter, the second switch end of the second transmission gate is connected to the output end of the second inverter, the signal input end of the second transmission gate is connected to the third input end of the enable selection module, and the signal output end of the second transmission gate is connected to the signal output end of the first transmission gate; and a fourth inverter, wherein the input end of the fourth inverter is connected to the signal output end of the second transmission gate, and the output end of the fourth inverter is connected to the third output end of the enable selection module.

[0016] Optionally, the resistance testing module further includes: a third transmission gate, wherein the first switch end of the third transmission gate is connected to the fourth input end, the second switch end of the third transmission gate is connected to the fifth input end, and the signal output end of the third transmission gate is connected to the first end of the device under test module; a fourth transmission gate, wherein the first switch end of the fourth transmission gate is connected to the sixth input end, the second switch end of the fourth transmission gate is connected to the seventh input end, and the signal output end of the fourth transmission gate is connected to the first end of the device under test module; a fifth transmission gate, wherein the first switch end of the fifth transmission gate is connected to the sixth input end, the second switch end of the fifth transmission gate is connected to the seventh input end, and the signal output end of the fifth transmission gate is connected to the second end of the device under test module; a sixth transmission gate, wherein the first switch end of the sixth transmission gate is connected to the sixth input end, and the second switch end of the sixth transmission gate is connected to the seventh input end; and the third end of the device under test module is connected to the fourth output end.

[0017] Optionally, the capacitance testing module is a QVCM capacitance testing circuit, and the capacitance testing module further includes a plurality of testing terminals.

[0018] Optionally, the function selection step includes: when the enable signal is at a high level, the function selection step is a capacitance test, the second transmission gate is turned on, the first transmission gate is turned off, the third transmission gate is turned on, the fourth transmission gate is turned off, the fifth transmission gate is turned off, and the sixth transmission gate is turned on; when the enable signal is at a low level, the function selection step is a resistance test, the second transmission gate is turned off, the first transmission gate is turned on, the third transmission gate is turned on, the fourth transmission gate is turned on, the fifth transmission gate is turned on, and the sixth transmission gate is turned on.

[0019] Optionally, the test step includes: when the function selection step is capacitance testing, inputting a clock signal at the signal input end of the third transmission gate, and performing capacitance testing through the several test ends of the capacitance testing module; when the function selection step is resistance testing, performing resistance testing through the signal input end of the third transmission gate, the signal input end of the fourth transmission gate, the signal input end of the fifth transmission gate, and the signal input end of the sixth transmission gate.

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] The technical solution of the present invention provides a test circuit, comprising an address decoder, an enable selection module, a resistance test module, and a capacitance test module. The resistance test module comprises a device under test module. The address decoder comprises a plurality of address input terminals and an address output terminal. The address decoder can compile a signal inputted from the address input terminal into a valid address signal outputted from the address output terminal. Based on the valid address signal, the device under test corresponding to the valid address signal can be selected within the device under test module. This increases the number of devices under test that can be tested per test when test probes are limited, thereby improving test efficiency. Furthermore, the enable selection module can control the test mode. When the enable input terminal of the enable selection module is at a high level, a capacitance test is performed; when the enable input terminal of the enable selection module is at a low level, a resistance test is performed. This ensures that the resistance and capacitance tests are performed on the same structure and in the same location, and can truly reflect the relationship between resistance and capacitance.

[0022] Furthermore, the address input terminals of the address decoder include: a plurality of chip select address input terminals and a plurality of region address input terminals; the device under test module includes a plurality of chip select modules corresponding to the chip select address input terminals, each of the chip select modules includes a plurality of region modules corresponding to the region address input terminals, and each of the region modules is coupled to the device under test. Based on the signals input to the chip select address input terminals and the signals input to the region address input terminals, the device under test corresponding to the region module within the corresponding chip select module can be selected. This increases the number of devices under test that can be tested per test when test probes are limited, thereby improving test efficiency.

[0023] Accordingly, in a method for operating a test circuit provided by the technical solution of the present invention, a first signal group is input from the address input terminals of the address decoder to perform a device selection step, and an enable signal is input from the enable input terminal of the enable selection module to perform a function selection step. The device selection step allows the selection of the device to be tested, thereby increasing the number of devices that can be tested per test when the number of test probes is limited, thereby improving test efficiency. The function selection step allows the control of whether the test mode is a resistance test or a capacitance test, ensuring that the resistance and capacitance tests are performed on the same structure and at the same location, and can truly reflect the relationship between the resistance and capacitance.

[0024] Furthermore, the first signal group includes a chip select address signal input from the chip select address input terminal and a region address signal input from the region address input terminal. The device selection step includes: after the address input terminal obtains the first signal group, the address output terminal outputs a second signal group, the second signal group including a chip select valid signal corresponding to the chip select address signal output from the chip select valid output terminal and a region valid signal corresponding to the region address signal output from the region valid output terminal; based on the second signal group input from the first terminal of the device under test module, selecting a device under test in a region module corresponding to the chip select valid signal and the region valid signal in the chip select module. The address decoder can compile the chip select address signal of the first signal group into the chip select valid signal and the region valid signal. Based on the chip select valid signal and the region valid signal, a corresponding device under test can be selected in the device under test module. This increases the number of devices under test that can be tested in each test when test probes are limited, thereby improving test efficiency.

[0025] Furthermore, the function selection step includes: when the enable signal is at a high level, the function selection step is a capacitance test; when the enable signal is at a low level, the function selection step is a resistance test, ensuring that the resistance and capacitance tests are performed on the same structure and at the same location, and can truly reflect the relationship between the resistance and capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 and Figure 2 Schematic diagram of the test circuit structure of an embodiment of the present invention;

[0027] Figure 3 Schematic diagram of a specific circuit structure of the enabling selection module in an embodiment of the present invention;

[0028] Figure 4 Schematic diagram of the specific circuit structure of the resistance testing module in an embodiment of the present invention;

[0029] Figure 5 1 is a flow chart of a working method of a test circuit according to an embodiment of the present invention;

[0030] Figure 6 and Figure 7 Schematic diagram of the working method of the test circuit when the enable signal is at a high level in an embodiment of the present invention;

[0031] Figure 8 and Figure 9 Schematic diagram of the working method of the test circuit when the enable signal is at a low level in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background, in integrated circuit resistance and capacitance testing, the resistance and capacitance test circuits are separate. This results in the actual resistance and capacitance values being obtained at different locations and in different test structures, failing to reflect the correlation between resistance and capacitance. Furthermore, due to the limited number of test probes available for each test, the above method can only test a small number of devices under test at a time.

[0033] To address the aforementioned technical issues, embodiments of the present invention provide a test circuit and operating method thereof. The test circuit comprises an address decoder, an enable selection module, a resistance test module, and a capacitance test module. The resistance test module comprises a device under test (DUT) module. The address decoder comprises a plurality of address input terminals and an address output terminal. The address decoder can interpret signals inputted from the address input terminals into valid address signals outputted from the address output terminals. Based on the valid address signals, the DUT corresponding to the valid address signals can be selected within the DUT module. This increases the number of DUTs that can be tested per test when test probes are limited, thereby improving test efficiency. Furthermore, the enable selection module can control the test mode. When the enable input terminal of the enable selection module is at a high level, a capacitance test is performed; when the enable input terminal of the enable selection module is at a low level, a resistance test is performed. This ensures that the resistance and capacitance tests are performed on the same structure and in the same location, effectively reflecting the relationship between resistance and capacitance.

[0034] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 and Figure 2 Schematic diagram of the test circuit structure of an embodiment of the present invention.

[0036] Please refer to Figure 1 and Figure 2 The test circuit includes: an address decoder 100, which includes: a plurality of address input terminals A and a plurality of address output terminals a; a first inverter 110, which includes: a first input terminal B connected to the address output terminal a, and a first output terminal b; an enable selection module 120, which includes: a second input terminal C connected to the address output terminal a, a third input terminal D connected to the first output terminal b, an enable input terminal E, a second output terminal c, and a third output terminal d; a resistance testing module 130, which includes: a fourth input terminal F connected to the address output terminal a, a fifth input terminal G connected to the first output terminal b, a sixth input terminal H connected to the second output terminal c, a seventh input terminal I connected to the third output terminal d, a fourth output terminal e, and a device under test module 131; and a capacitance testing module 140, which includes an eighth input terminal J connected to the fourth output terminal e.

[0037] Please continue to refer to Figure 1 and Figure 2The address input terminal A includes: several chip select address input terminals and several area address input terminals; the address output terminal a includes: several chip select valid output terminals corresponding to the chip select address input terminals and several area valid output terminals corresponding to the area address input terminals.

[0038] Figure 3 Schematic diagram of a specific circuit structure of the enabling selection module described in an embodiment of the present invention.

[0039] Please refer to Figure 3 The enable selection module 120 further includes: a second inverter 121, wherein the input terminal of the second inverter 121 is connected to the enable input terminal E; a third inverter 122, wherein the input terminal of the third inverter 122 is connected to the output terminal of the second inverter 121; a first transmission gate 123, wherein the first switch terminal k1 of the first transmission gate 123 is connected to the output terminal of the second inverter 121, the signal input terminal m1 of the first transmission gate 123 is connected to the second input terminal C of the enable selection module 120, and the signal output terminal m2 of the first transmission gate 123 is connected to the second output terminal c of the enable selection module 120; a second transmission gate 124, wherein the first switch terminal k1 of the second transmission gate 124 is connected to the output terminal of the second inverter 121, The switch end k3 is connected to the second switch end k2 of the first transmission gate 123 and the output end of the third inverter 122, the second switch end k4 of the second transmission gate 124 is connected to the output end of the second inverter 121, the signal input end m3 of the second transmission gate 124 is connected to the third input end D of the enable selection module 120, and the signal output end m4 of the second transmission gate 124 is connected to the signal output end m2 of the first transmission gate 123; the fourth inverter 125, the input end of the fourth inverter 125 is connected to the signal output end m4 of the second transmission gate 124, and the output end of the fourth inverter 125 is connected to the third output end d of the enable selection module 120.

[0040] In this embodiment, the enable selection module 120 controls whether the test circuit is to be tested for resistance or capacitance. When the enable input E of the enable selection module 120 is at a high level, a capacitance test is performed; when the enable input E of the enable selection module 120 is at a low level, a resistance test is performed. This ensures that the resistance and capacitance tests are performed on the same structure and location, and can truly reflect the relationship between resistance and capacitance.

[0041] Figure 4 Schematic diagram of the specific circuit structure of the resistance testing module in an embodiment of the present invention.

[0042] Please refer to Figure 4The resistance testing module 130 further includes: a third transmission gate 132, wherein the first switch terminal k5 of the third transmission gate 132 is connected to the fourth input terminal F, the second switch terminal k6 of the third transmission gate 132 is connected to the fifth input terminal G, and the signal output terminal m6 of the third transmission gate 132 is connected to the first terminal M of the device under test module 131; a fourth transmission gate 133, wherein the first switch terminal k7 of the fourth transmission gate 133 is connected to the sixth input terminal H, the second switch terminal k8 of the fourth transmission gate 133 is connected to the seventh input terminal I, and the signal output terminal m8 of the fourth transmission gate 133 is connected to the device under test module a fifth transmission gate 134, wherein a first switch terminal k9 of the fifth transmission gate 134 is connected to the sixth input terminal H, a second switch terminal k10 of the fifth transmission gate 134 is connected to the seventh input terminal I, and a signal output terminal m10 of the fifth transmission gate 134 is connected to the second terminal N of the device under test module 131; a sixth transmission gate 135, wherein a first switch terminal k11 of the sixth transmission gate 135 is connected to the sixth input terminal H, and a second switch terminal k12 of the sixth transmission gate 135 is connected to the seventh input terminal I; and a third terminal f of the device under test module 131 is connected to the fourth output terminal e.

[0043] In this embodiment, the enable selection module 120 can control the test mode.

[0044] In this embodiment, when the enable input E of the enable selection module 120 is at a low level, the resistance testing module 130 forms a test circuit for the Kelvin resistance test method. A resistance test can be performed by applying a test probe to each of the signal input m5 of the third transmission gate 132, the signal input m7 of the fourth transmission gate 133, the signal input m9 of the fifth transmission gate 134, and the signal input m11 of the sixth transmission gate 135. During the resistance test, the circuit of the capacitance testing module 140 is not operational.

[0045] In this embodiment, the capacitance test module 140 is a QVCM capacitance test circuit, and the capacitance test module 140 also includes a plurality of test terminals. When the enable input terminal E of the enable selection module 120 is at a high level, a clock signal is applied to the signal input terminal m5 of the third transmission gate 132. In conjunction with the capacitance test unit 140, a probe is applied to the test terminal of the capacitance test unit 140 to perform a capacitance test using the QVCM method.

[0046] By controlling the level of the enable input terminal E of the enable selection module 120, it is possible to select whether to perform a resistance test or a capacitance test, thereby ensuring that the resistance and capacitance tests are performed on the same structure and at the same location, and can truly reflect the relationship between resistance and capacitance.

[0047] In this embodiment, the device under test module 131 includes several chip select modules corresponding to the chip select valid output terminals, each of the chip select modules includes several regional modules corresponding to the regional valid output terminals, and each of the regional modules is used to couple to the device under test.

[0048] The address decoder 100 can compile the signal input from the address input terminal A into a valid address signal output from the address output terminal a. According to the valid address signal, the device under test corresponding to the valid address signal can be selected in the device under test module 131. In this way, when the test probes are limited, the number of devices under test that can be tested in each test is increased, thereby improving the test efficiency.

[0049] In this embodiment, there are three chip select address input terminals, corresponding to eight chip select modules in the DUT module 131. There are four region address input terminals, and each of the eight chip select modules in the DUT module 131 has 16 region modules. Within each chip select module, 16 DUTs are coupled to each region module. Therefore, in this embodiment, at least 128 DUTs can be tested per test. When test probes are limited, increasing the number of DUTs that can be tested per test improves test efficiency.

[0050] Accordingly, the embodiment of the present invention also provides a Figures 1 to 4 How the test circuit shown works, please refer to Figure 5 ,include:

[0051] Step S200, providing a test circuit;

[0052] Step S210, inputting a first signal group from the plurality of address input terminals of the address decoder to perform a device selection step;

[0053] Step S220, inputting an enable signal from the enable input terminal of the enable selection module to perform a function selection step;

[0054] Step S230, performing a test step.

[0055] The following is a detailed description with reference to the accompanying drawings.

[0056] Please continue to refer to Figures 1 to 4 , provide test circuit.

[0057] The test circuit includes: an address decoder 100, which includes: a plurality of address input terminals A and a plurality of address output terminals a; a first inverter 110, which includes: a first input terminal B connected to the address output terminal a, and a first output terminal b; an enable selection module 120, which includes: a second input terminal C connected to the address output terminal a, a third input terminal D connected to the first output terminal b, an enable input terminal E, a second output terminal c, and a third output terminal d; a resistance testing module 130, which includes: a fourth input terminal F connected to the address output terminal a, a fifth input terminal G connected to the first output terminal b, a sixth input terminal H connected to the second output terminal c, a seventh input terminal I connected to the third output terminal d, a fourth output terminal e, and a device under test module 131; and a capacitance testing module 140, which includes an eighth input terminal J connected to the fourth output terminal e.

[0058] Please continue to refer to Figure 3 The enable selection module 120 further includes: a second inverter 121, wherein the input terminal of the second inverter 121 is connected to the enable input terminal E; a third inverter 122, wherein the input terminal of the third inverter 122 is connected to the output terminal of the second inverter 121; a first transmission gate 123, wherein the first switch terminal k1 of the first transmission gate 123 is connected to the output terminal of the second inverter 121, the signal input terminal m1 of the first transmission gate 123 is connected to the second input terminal C of the enable selection module 120, and the signal output terminal m2 of the first transmission gate 123 is connected to the second output terminal c of the enable selection module 120; a second transmission gate 124, wherein the first switch terminal k1 of the second transmission gate 124 is connected to the output terminal of the second inverter 121, The switch end k3 is connected to the second switch end k4 of the first transmission gate 123 and the output end of the third inverter 122, the second switch end k4 of the second transmission gate 124 is connected to the output end of the second inverter 121, the signal input end m3 of the second transmission gate 124 is connected to the third input end D of the enable selection module 120, and the signal output end m4 of the second transmission gate 124 is connected to the signal output end m2 of the first transmission gate 123; the fourth inverter 125, the input end of the fourth inverter 125 is connected to the signal output end m4 of the second transmission gate 124, and the output end of the fourth inverter 125 is connected to the third output end d of the enable selection module 120.

[0059] Please refer to Figure 4The resistance testing module 130 further includes: a third transmission gate 132, wherein the first switch terminal k5 of the third transmission gate 132 is connected to the fourth input terminal F, the second switch terminal k6 of the third transmission gate 132 is connected to the fifth input terminal G, and the signal output terminal m6 of the third transmission gate 132 is connected to the first terminal M of the device under test module 131; a fourth transmission gate 133, wherein the first switch terminal k7 of the fourth transmission gate 133 is connected to the sixth input terminal H, the second switch terminal k8 of the fourth transmission gate 133 is connected to the seventh input terminal I, and the signal output terminal m8 of the fourth transmission gate 133 is connected to the device under test module a fifth transmission gate 134, wherein a first switch terminal k9 of the fifth transmission gate 134 is connected to the sixth input terminal H, a second switch terminal k10 of the fifth transmission gate 134 is connected to the seventh input terminal I, and a signal output terminal m10 of the fifth transmission gate 134 is connected to the second terminal N of the device under test module 131; a sixth transmission gate 135, wherein a first switch terminal k11 of the sixth transmission gate 135 is connected to the sixth input terminal H, and a second switch terminal k12 of the sixth transmission gate 135 is connected to the seventh input terminal I; and a third terminal f of the device under test module 131 is connected to the fourth output terminal e.

[0060] In this embodiment, the device under test module 131 includes several chip select modules corresponding to the chip select valid output terminals, each of the chip select modules includes several regional modules corresponding to the regional valid output terminals, and each of the regional modules is used to couple to the device under test.

[0061] Please continue to refer to Figure 1 and Figure 2 The address input terminal A includes: several chip select address input terminals and several area address input terminals; the address output terminal a includes: several chip select valid output terminals corresponding to the chip select address input terminals and several area valid output terminals corresponding to the area address input terminals.

[0062] Step S210 is executed to input a first signal group from the plurality of address input terminals A of the address decoder 100 to perform a device selection step. The first signal group includes a chip select address signal input from the chip select address input terminal and a region address signal input from the region address input terminal. The device selection step includes: after the address input terminal A receives the first signal group, the address output terminal a outputs a second signal group, the second signal group including a chip select valid signal output from the chip select valid output terminal corresponding to the chip select address signal and a region valid signal output from the region valid output terminal corresponding to the region address signal; and based on the second signal group input from the first terminal of the device under test module 131, selecting a device under test in a region module corresponding to the chip select valid signal and the region valid signal in the chip select module corresponding to the chip select valid signal.

[0063] The first signal group is used to control the chip select address and the region address. The address decoder 100 can compile the chip select address signal of the first signal group into the chip select valid signal and the region valid signal. Based on the chip select valid signal and the region valid signal, a corresponding device under test (DUT) can be selected in the DUT module 131. This increases the number of DUTs that can be tested in each test when test probes are limited, thereby improving test efficiency.

[0064] In this embodiment, there are three chip select address input terminals, the chip select address signal is a 3-bit binary number, and there are eight corresponding chip select modules in the device under test module 131. There are four region address input terminals, the region address signal is a 4-bit binary number, and each of the eight chip select modules in the device under test module 131 has 16 region modules. Within each chip select module, there are 16 devices under test coupled to each region module. Therefore, in this embodiment, at least 128 devices under test can be tested per test. When test probes are limited, increasing the number of devices under test that can be tested per test improves test efficiency.

[0065] Please continue to refer to Figure 1 and Figure 2 The capacitance testing module 140 is a QVCM capacitance testing circuit, and the capacitance testing module 140 also includes a plurality of testing terminals.

[0066] Figure 6 and Figure 7 Schematic diagram of the working method of the test circuit when the enable signal is at a high level in an embodiment of the present invention.

[0067] Execute step S220, input the enable signal EN from the enable input terminal E of the enable selection module 120 to perform a function selection step. The function selection step includes:

[0068] Please refer to Figure 6 and Figure 7 When the enable signal EN is at a high level, the function selection step is a capacitance test. After the enable input terminal E inputs the high-level enable signal EN, the output terminal of the second inverter is at a low level, the second transmission gate 124 is turned on, the third output terminal d is at a high level, the first transmission gate 123 is turned off, the second output terminal c is at a low level, the third transmission gate 132 is turned on, the fourth transmission gate 133 is turned off, the fifth transmission gate 134 is turned off, and the sixth transmission gate 135 is turned off. As long as a clock signal is input to the signal input terminal m5 of the third transmission gate 132, and the capacitance test unit 140 is used, and a probe is applied to the test terminal of the capacitance test unit 140, the capacitance test using the QVCM method can be performed.

[0069] Figure 8 and Figure 9 Schematic diagram of the working method of the test circuit when the enable signal is at a low level in an embodiment of the present invention.

[0070] Please refer to Figure 8 and Figure 9 When the enable signal EN is at a low level, the function selection step is a resistance test. After the enable input terminal E inputs the low-level enable signal EN, the second transmission gate 124 is disconnected, the third output terminal d is at a low level, the first transmission gate 123 is turned on, the second output terminal c is at a high level, the third transmission gate 132 is turned on, the fourth transmission gate 133 is turned on, the fifth transmission gate 134 is turned on, and the sixth transmission gate 135 is turned on. The resistance testing module 130 forms a test circuit for the Kelvin resistance test method. A resistance test can be performed by applying a test probe to each of the signal input terminal m5 of the third transmission gate 132, the signal input terminal m7 of the fourth transmission gate 133, the signal input terminal m9 of the fifth transmission gate 134, and the signal input terminal m11 of the sixth transmission gate 135. During the resistance test, the circuit of the capacitance testing module 140 is not operational.

[0071] It should be noted that there is no specific execution order for step S210 and step S220.

[0072] Execute step S230 to perform a test step. The test step includes: when the function selection step S220 is a capacitance test, inputting a clock signal to the signal input terminal m5 of the third transmission gate 132, and performing a capacitance test through the plurality of test terminals of the capacitance test module 140; when the function selection step S220 is a resistance test, performing a resistance test through the signal input terminal m5 of the third transmission gate 132, the signal input terminal m7 of the fourth transmission gate 133, the signal input terminal m9 of the fifth transmission gate 134, and the signal input terminal m11 of the sixth transmission gate 135.

[0073] In this embodiment, since the capacitance testing module 140 is a QVCM capacitance testing circuit, when the function selection step S220 is capacitance testing, the capacitance testing method is the QVCM capacitance testing method. When the function selection step S220 is resistance testing, the resistance testing module 130 forms a test circuit for the Kelvin resistance testing method, and thus the resistance testing method is the Kelvin resistance testing method.

[0074] In this embodiment, by controlling the level of the enable signal EN, it is possible to select whether to perform a resistance test or a capacitance test, thereby ensuring that the resistance and capacitance tests are performed on the same structure and at the same location, and can truly reflect the relationship between the resistance and capacitance.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test circuit, characterized in that: include: An address decoder, the address decoder comprising: a plurality of address input terminals and a plurality of address output terminals; A first inverter, comprising: a first input terminal connected to the address output terminal, and a first output terminal; An enable selection module, the enable selection module comprising: a second input terminal connected to the address output terminal, a third input terminal connected to the first output terminal, an enable input terminal, a second output terminal, and a third output terminal; a resistance testing module, the resistance testing module comprising: a fourth input terminal connected to the address output terminal, a fifth input terminal connected to the first output terminal, a sixth input terminal connected to the second output terminal, a seventh input terminal connected to the third output terminal, a fourth output terminal, and a device under test module; a capacitance testing module, the capacitance testing module comprising an eighth input terminal connected to the fourth output terminal; The resistance testing module further includes: a third transmission gate, wherein a first switch terminal of the third transmission gate is connected to the fourth input terminal, a second switch terminal of the third transmission gate is connected to the fifth input terminal, and a signal output terminal of the third transmission gate is connected to the first terminal of the device under test module; a fourth transmission gate, wherein a first switch terminal of the fourth transmission gate is connected to the sixth input terminal, a second switch terminal of the fourth transmission gate is connected to the seventh input terminal, and a signal output terminal of the fourth transmission gate is connected to the first terminal of the device under test module; a fifth transmission gate, wherein a first switch terminal of the fifth transmission gate is connected to the sixth input terminal, a second switch terminal of the fifth transmission gate is connected to the seventh input terminal, and a signal output terminal of the fifth transmission gate is connected to the second terminal of the device under test module; and a sixth transmission gate, wherein a first switch terminal of the sixth transmission gate is connected to the sixth input terminal, and a second switch terminal of the sixth transmission gate is connected to the seventh input terminal; and the third terminal of the device under test module is connected to the fourth output terminal.

2. The test circuit according to claim 1, wherein: The enable selection module further includes: a second inverter, wherein an input terminal of the second inverter is connected to the enable input terminal; a third inverter, wherein an input terminal of the third inverter is connected to an output terminal of the second inverter; a first transmission gate, wherein a first switch terminal of the first transmission gate is connected to an output terminal of the second inverter, a signal input terminal of the first transmission gate is connected to the second input terminal of the enable selection module, and a signal output terminal of the first transmission gate is connected to the second output terminal of the enable selection module; a second transmission gate, wherein a first switch terminal of the second transmission gate is connected to a second switch terminal of the first transmission gate and to an output terminal of the third inverter, a second switch terminal of the second transmission gate is connected to an output terminal of the second inverter, a signal input terminal of the second transmission gate is connected to the third input terminal of the enable selection module, and a signal output terminal of the second transmission gate is connected to the signal output terminal of the first transmission gate; and a fourth inverter, wherein an input terminal of the fourth inverter is connected to the signal output terminal of the second transmission gate, and an output terminal of the fourth inverter is connected to the third output terminal of the enable selection module.

3. The test circuit according to claim 1, wherein: The address input end includes: a plurality of chip select address input ends and a plurality of region address input ends; the address output end includes: a plurality of chip select valid output ends corresponding to the chip select address input ends and a plurality of region valid output ends corresponding to the region address input ends.

4. The test circuit according to claim 3, wherein: The device under test module includes a plurality of chip select modules corresponding to the chip select valid output terminal, each of the chip select modules includes a plurality of regional modules corresponding to the regional valid output terminal, and each of the regional modules is used for coupling to the device under test.

5. The test circuit according to claim 1, wherein: The capacitance test module is a QVCM capacitance test circuit, and the capacitance test module further includes a plurality of test terminals.

6. A method for testing a circuit, characterized in that: include: A test circuit is provided, the test circuit comprising an address decoder, the address decoder comprising: an address decoder including: a plurality of address input terminals and a plurality of address output terminals; a first inverter including: a first input terminal connected to the address output terminal and a first output terminal; an enable selection module including: a second input terminal connected to the address output terminal, a third input terminal connected to the first output terminal, an enable input terminal, a second output terminal, and a third output terminal; a resistance testing module including: a fourth input terminal connected to the address output terminal, a fifth input terminal connected to the first output terminal, a sixth input terminal connected to the second output terminal, a seventh input terminal connected to the third output terminal, a fourth output terminal, and a device under test module; and a capacitance testing module including: an eighth input terminal connected to the fourth output terminal. Inputting a first signal group from the plurality of address input terminals of the address decoder to perform a device selection step; Inputting an enable signal from the enable input terminal of the enable selection module to perform a function selection step; performing a testing step after the device selection step and the function selection step; The resistance testing module further includes: a third transmission gate, wherein a first switch terminal of the third transmission gate is connected to the fourth input terminal, a second switch terminal of the third transmission gate is connected to the fifth input terminal, and a signal output terminal of the third transmission gate is connected to the first terminal of the device under test module; a fourth transmission gate, wherein a first switch terminal of the fourth transmission gate is connected to the sixth input terminal, a second switch terminal of the fourth transmission gate is connected to the seventh input terminal, and a signal output terminal of the fourth transmission gate is connected to the first terminal of the device under test module; a fifth transmission gate, wherein a first switch terminal of the fifth transmission gate is connected to the sixth input terminal, a second switch terminal of the fifth transmission gate is connected to the seventh input terminal, and a signal output terminal of the fifth transmission gate is connected to the second terminal of the device under test module; and a sixth transmission gate, wherein a first switch terminal of the sixth transmission gate is connected to the sixth input terminal, and a second switch terminal of the sixth transmission gate is connected to the seventh input terminal; and the third terminal of the device under test module is connected to the fourth output terminal.

7. The operating method of the test circuit according to claim 6, wherein: The address input end includes: a plurality of chip select address input ends and a plurality of region address input ends; the address output end includes: a plurality of chip select valid output ends corresponding to the chip select address input ends and a plurality of region valid output ends corresponding to the region address input ends.

8. The operating method of the test circuit according to claim 7, wherein: The device under test module includes a plurality of chip select modules corresponding to the chip select valid output terminal, each of the chip select modules includes a plurality of regional modules corresponding to the regional valid output terminal, and each of the regional modules is used for coupling to the device under test.

9. The operating method of the test circuit according to claim 8, characterized in that: The first signal group includes a chip select address signal input from the chip select address input end and a region address signal input from the region address input end. The device selection step includes: after the address input end obtains the first signal group, the address output end outputs a second signal group, the second signal group includes a chip select valid signal corresponding to the chip select address signal output from the chip select valid output end, and a region valid signal corresponding to the region address signal output from the region valid output end; according to the second signal group input from the first end of the device under test module, selecting the device under test in the region module corresponding to the chip select module corresponding to the chip select valid signal and the region valid signal corresponding to the region valid signal.

10. The operating method of the test circuit according to claim 6, wherein: The enable selection module further includes: a second inverter, wherein an input terminal of the second inverter is connected to the enable input terminal; a third inverter, wherein an input terminal of the third inverter is connected to an output terminal of the second inverter; a first transmission gate, wherein a first switch terminal of the first transmission gate is connected to an output terminal of the second inverter, a signal input terminal of the first transmission gate is connected to the second input terminal of the enable selection module, and a signal output terminal of the first transmission gate is connected to the second output terminal of the enable selection module; a second transmission gate, wherein a first switch terminal of the second transmission gate is connected to a second switch terminal of the first transmission gate and to an output terminal of the third inverter, a second switch terminal of the second transmission gate is connected to an output terminal of the second inverter, a signal input terminal of the second transmission gate is connected to the third input terminal of the enable selection module, and a signal output terminal of the second transmission gate is connected to the signal output terminal of the first transmission gate; and a fourth inverter, wherein an input terminal of the fourth inverter is connected to the signal output terminal of the second transmission gate, and an output terminal of the fourth inverter is connected to the third output terminal of the enable selection module.

11. The operating method of the test circuit according to claim 10, wherein: The capacitance test module is a QVCM capacitance test circuit, and the capacitance test module further includes a plurality of test terminals.

12. The operating method of the test circuit according to claim 11, wherein: The function selection step includes: when the enable signal is at a high level, the function selection step is a capacitance test, the second transmission gate is turned on, the first transmission gate is turned off, the third transmission gate is turned on, the fourth transmission gate is turned off, the fifth transmission gate is turned off, and the sixth transmission gate is turned off; when the enable signal is at a low level, the function selection step is a resistance test, the second transmission gate is turned off, the first transmission gate is turned on, the third transmission gate is turned on, the fourth transmission gate is turned on, the fifth transmission gate is turned on, and the sixth transmission gate is turned on.

13. The operating method of the test circuit according to claim 12, wherein: The testing steps include: when the function selection step is capacitance testing, inputting a clock signal at the signal input end of the third transmission gate, and performing capacitance testing through the several test ends of the capacitance testing module; when the function selection step is resistance testing, performing resistance testing through the signal input end of the third transmission gate, the signal input end of the fourth transmission gate, the signal input end of the fifth transmission gate, and the signal input end of the sixth transmission gate.

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