Task migration method and apparatus, electronic device, and storage medium

Abstract

This disclosure discloses a task migration method, apparatus, electronic device, and storage medium, relating to the field of computer technology, and particularly to the field of asymmetric multiprocessor systems. The specific implementation is as follows: In response to detecting an operational anomaly in an asymmetric multiprocessor system, load information of the asymmetric multiprocessor system and error information of the abnormal processor core are obtained. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. Based on the error information, at least one candidate processor core from the multiple processor cores and the target task to be migrated from the abnormal processor core are determined. Based on the load information, the target processor core is determined from the at least one candidate processor core. The target task to be migrated is then migrated to the target processor core.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of asymmetric multiprocessor systems, specifically to a task migration method, apparatus, electronic device, and storage medium. Background Technology

[0002] Asymmetric multiprocessor systems are a type of multi-processor architecture. In this architecture, multiple processor cores exist, each assigned to execute a specific task at a given time. Because the memory address spaces of different processor cores are independent and do not interfere with each other, the system is highly complex.

[0003] Currently, asymmetric multiprocessor systems are widely used in the field of autonomous driving technology. Summary of the Invention

[0004] This disclosure provides a method, apparatus, electronic device, and storage medium for task migration.

[0005] According to one aspect of this disclosure, a task migration method is provided, comprising:

[0006] In response to the detection of an operational anomaly in an asymmetric multiprocessor system, the system acquires load information and error information of the abnormal processor core. The asymmetric multiprocessor system comprises multiple processor cores with independent memory address spaces. Based on the error information, at least one candidate processor core and a target task to be migrated from the abnormal processor core are identified. Based on the load information, a target processor core is determined from the at least one candidate processor core. The target task to be migrated is then migrated to the target processor core.

[0007] According to another aspect of this disclosure, a task migration apparatus is provided, comprising: an acquisition module, a first determination module, a second determination module, and a migration module. The acquisition module is configured to, in response to detecting an operational anomaly in an asymmetric multiprocessor system, acquire load information of the asymmetric multiprocessor system and error information of the abnormal processor core, wherein the asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. The first determination module is configured to, based on the error information, determine at least one candidate processor core from the multiple processor cores and a target task to be migrated from the abnormal processor core. The second determination module is configured to, based on the load information, determine a target processor core from the at least one candidate processor core. The migration module is configured to migrate the target task to the target processor core.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method as described above.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform the method described above.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method described above.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0013] Figure 1 This illustration schematically shows an exemplary system architecture to which task migration methods and apparatus can be applied according to embodiments of the present disclosure;

[0014] Figure 2 A flowchart illustrating a task migration method according to an embodiment of the present disclosure is shown schematically;

[0015] Figure 3 A schematic diagram illustrating the determination of a target processor core according to an embodiment of the present disclosure is shown.

[0016] Figure 4 A schematic diagram illustrating a task control information migration operation according to an embodiment of the present disclosure is shown.

[0017] Figure 5 The illustration shows a schematic diagram of a permission migration operation according to an embodiment of the present disclosure;

[0018] Figure 6 A schematic diagram illustrating a stack migration operation according to an embodiment of the present disclosure is provided.

[0019] Figure 7 The illustration shows a schematic diagram of a code segment migration operation according to an embodiment of the present disclosure;

[0020] Figure 8A block diagram of a task migration apparatus according to an embodiment of the present disclosure is schematically shown; and

[0021] Figure 9 A block diagram of an electronic device suitable for implementing a task migration method according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0022] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0023] In asymmetric multiprocessor systems, the memory address spaces of processor cores are independent and do not affect each other. Different processor cores need to handle different tasks, resulting in different load rates on the processor cores. When all processor cores are operating normally, load balancing can be achieved through task migration to ensure stable system operation.

[0024] However, when an asymmetric multiprocessor system experiences a malfunction, tasks in the malfunctioning processor core need to be migrated to restore system functionality as quickly as possible. Unlike symmetric multiprocessor systems, task control information between different processor cores is not stored in shared memory, which poses a challenge to task migration.

[0025] In view of this, embodiments of this disclosure provide a task migration method, comprising: in response to detecting an operational anomaly in an asymmetric multiprocessor system, acquiring load information of the asymmetric multiprocessor system and error information of the abnormal processor core, wherein the asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces; determining at least one candidate processor core from the multiple processor cores and a target task to be migrated from the abnormal processor core based on the error information; determining a target processor core from the at least one candidate processor core based on the load information; and migrating the target task to be migrated to the target processor core.

[0026] Figure 1 An exemplary system architecture for applying task migration methods and apparatus according to embodiments of the present disclosure is illustrated.

[0027] like Figure 1As shown, when an operational anomaly is detected in the asymmetric multiprocessor system, the error information of the abnormal processor core is obtained using the safety management unit (SMU). Then, the load management unit (102) obtains the load information of the asymmetric multiprocessor system, and can select the processor core with the lowest load rate from among the multiple processor cores in the current asymmetric multiprocessor system as the target processor core.

[0028] The task migration module 103 migrates the target task to be migrated in the exception handler core 104 to the target processor core 105. During the migration process, the running state of the target task to be migrated can be changed to the blocked state, and the task control information of the target task can be migrated to the blocked task queue of the target processor core 105.

[0029] Task control information is an information structure containing multi-dimensional information such as I / O permission information, stack information, and code segment information. After completing the migration operation of task control information, permission migration, stack migration, and code segment migration need to be performed sequentially, and the corresponding information in the task control information corresponding to the target task in the target processor core 105 needs to be changed accordingly to complete the migration operation of the target task.

[0030] It should be understood that Figure 1 The number of security management modules, load management modules, and task migration modules shown is merely illustrative. Depending on implementation needs, any number of these modules can be included.

[0031] Figure 2 A flowchart illustrating a task migration method according to an embodiment of the present disclosure is shown schematically;

[0032] like Figure 2 As shown, the method includes operations S210 to S240.

[0033] In operation S210, in response to the detection of an operational anomaly in the asymmetric multiprocessor system, the load information of the asymmetric multiprocessor system and the error information of the abnormal processor core are obtained. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces.

[0034] In operation S220, based on the error information, at least one candidate processor core and the target task to be migrated from the multiple processor cores are identified.

[0035] In operation S230, the target processor core is determined from at least one candidate processor core based on the load information.

[0036] In operation S240, the target task to be migrated is migrated to the target processor core.

[0037] According to embodiments of this disclosure, the error information of the exception processor core can include the following two types of error information: The first type is module-type error information, such as a CAN module exception. This type of error generally only affects the task currently running in the exception processor core. The second type is instruction-type error information, such as a division-by-zero instruction error. A division-by-zero instruction error indicates that an incorrect instruction with zero as the divisor has occurred in the running instructions. This type of error will affect the normal operation of all tasks in the entire exception processor core, and may even cause the exception processor core to crash.

[0038] According to embodiments of this disclosure, the load information of an asymmetric multiprocessor system can characterize the load rate of each processor core in the asymmetric multiprocessor system within a predetermined period. The load rate characterizes the ratio of the number of running tasks occupying processor core working time within each processor core to the total number of tasks per unit time. In an asymmetric multiprocessor system, each processor core corresponds to a real-time operating system (RTOS) used to periodically calculate the load rate of each processor core and the processor core utilization of each task. The processor core utilization characterizes the proportion of processor core working time to the total time, where the total time represents the sum of a continuous period of processor core working time and processor core idle time. The predetermined period can be 10ms.

[0039] For example, the error message could be "CAN module malfunction in processor core A." Since this type of error message only affects the currently running task in processor core A, the target task to be migrated can be determined as the currently running task T in processor core A. a .

[0040] According to embodiments of this disclosure, an asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces, and the types of tasks running on different processor cores can be different. This can be based on task T. a The task type is determined by identifying at least one candidate processor core from multiple processor cores in an asymmetric multiprocessor system to process task T. a .

[0041] According to embodiments of this disclosure, candidate processor cores may include processor core B and processor core C. Based on the load information of the candidate processor cores, the processor core with the relatively lower load rate can be selected as the target processor core. For example, if processor core B has a load rate of 50% and processor core C has a load rate of 60%, processor core B can be selected as the target processor core. Task Ta can then be migrated from processor core A to processor core B.

[0042] According to the embodiments of this disclosure, when an operational anomaly is detected in the asymmetric processor system, the target task to be migrated is determined based on the error information of the abnormal processor core, and the target processor core is determined in combination with the load information of the asymmetric processor system. This allows for accurate location of the migration object and the direction of task migration, enabling timely migration of the target task to the target processor core and ensuring the functional safety of the asymmetric processor system.

[0043] According to embodiments of this disclosure, the above operation S220 may include the following operations:

[0044] Parse the error message to determine its impact on the abnormal processor core. Based on the impact level, filter the task queue of the abnormal processor core to obtain target tasks for migration. Based on the target tasks to be migrated, determine at least one candidate processor core from multiple processor cores.

[0045] According to embodiments of this disclosure, by parsing error information, the degree of impact of the error information on the exception handler core can be obtained. For example, module-type error information only affects the currently running task in the exception handler core, and the currently running task can be identified as the target task to be migrated. Instruction-type error information affects all tasks in the exception handler core, and both the currently running tasks and the tasks to be run in the exception handler core can be identified as target tasks to be migrated.

[0046] According to embodiments of this disclosure, before performing task migration, the running state of a currently running task can be changed to a blocked state before the blocked task is migrated. The blocked state represents a state waiting to be woken up by the processor core; that is, a task changed to the blocked state temporarily no longer occupies the processor core's working time.

[0047] According to embodiments of this disclosure, at least one candidate processor core from a plurality of processor cores can be selected based on the task type or other attribute information that can characterize the task of the target task to be migrated. For example, if the target task is a time-sensitive task with high utilization of processor cores, the processor core with the highest processing speed among the plurality of processor cores can be identified as a candidate processor core.

[0048] According to embodiments of this disclosure, accurately locating the target task to be migrated in the abnormal processor core based on error information can effectively reduce the impact of redundant task migration on system functions and improve the accuracy of task migration.

[0049] According to embodiments of this disclosure, the above operation S230 may include the following operations:

[0050] Based on the load information, at least one candidate processor core is sorted to obtain a sorting result. Based on the selection strategy, the target processor core is determined from the at least one candidate processor core according to the sorting result.

[0051] For example, candidate processor cores that meet the processing power requirements of the target task may include: processor core A, processor core B, and processor core C. Processor core A has a load rate of 30%, processor core B has a load rate of 40%, and processor core C has a load rate of 50%.

[0052] According to embodiments of this disclosure, the selection strategy may be to select the processor core with the lowest load rate as the target processor core. For example, processor cores A, B, and C are sorted from highest to lowest load rate, resulting in a sorted list of processor cores C, B, and A. Processor core A, which is ranked last, has the lowest load rate and can be selected as the target processor core.

[0053] The following is for reference. Figures 3-7 In conjunction with specific embodiments, Figure 2 The method shown will be further explained.

[0054] Figure 3 A schematic diagram illustrating the determination of a target processor core according to an embodiment of the present disclosure is shown.

[0055] like Figure 3 As shown in Figure 300, the exception processor core 321 determines the target task to be migrated based on the error information, and determines candidate processor cores A322 and B323 from the asymmetric multiprocessor system based on the target task. Then, based on the load information of the candidate processor cores, the target processor core 324 is obtained from the candidate processor cores.

[0056] According to embodiments of this disclosure, a target processor core is selected from candidate processor cores using load information, thereby reducing the impact of task migration on load balancing while completing task migration, and maintaining load balancing of the entire asymmetric multiprocessor system as much as possible.

[0057] According to embodiments of this disclosure, the above operation S240 may include the following operations:

[0058] Retrieve the target task control information corresponding to the target task. Migrate the target task control information to the task queue of the target processor core. Perform permission migration, stack migration, and code segment migration operations sequentially on the target task control information.

[0059] According to embodiments of this disclosure, the target task control information may include multi-dimensional information related to the target task, such as: stack area information, task identification information, entry address information of the function to execute the task, virtual device used by the task and its corresponding address information, code area information, etc.

[0060] According to embodiments of this disclosure, the stack area can be used to store task function information required for task execution. The stack information may include stack content information representing the task function information and stack top pointer information, stack bottom pointer information, and stack length information representing the stack space.

[0061] According to embodiments of this disclosure, the code segment can be used to store instruction information required to execute a task. The code segment information may include code segment content information representing the instruction information, instruction address information representing the code segment space, and pointer address information used for task switching.

[0062] According to embodiments of this disclosure, the virtual devices used by a task and their corresponding address information are generally represented by a virtual array corresponding to the task. In the virtual array, each address corresponds one-to-one with a virtual device. When the address corresponding to the task in the virtual data array is not "empty," it indicates that the task has input / output permissions for the virtual device corresponding to that address.

[0063] According to embodiments of this disclosure, the entry address information of the execution task function can represent the stack address information corresponding to the task function stored in the stack area.

[0064] According to embodiments of this disclosure, before migrating the target task control information, the running state of the target task can be changed to a blocked state, and then the target task control information can be migrated from the blocked task queue of the exception processor core to the blocked task queue of the target processor core. Then, permission migration operations, stack migration operations, and code segment migration operations are executed sequentially to change the permission information, stack information, code segment information, etc., in the target task control information.

[0065] Figure 4 A schematic diagram illustrating a task control information migration operation according to an embodiment of the present disclosure is shown.

[0066] like Figure 4As shown in Figure 400, the task queue of exception processor core 431 may include: task control information Command_1 (431_1) corresponding to task Task_1, task control information Command_m (431_m) corresponding to the target task Task_m, ..., and task control information Command_M (431M) corresponding to task M. Before the task control information migration operation is performed, the task queue of target processor core 432 may include task control information Command_a (4321) corresponding to task Task_a, ..., and task control information Command_N (432_N) corresponding to task Task_N. The task control information migration operation is performed on the task control information Command_m corresponding to the target task Task_m, migrating the task control information Command_m (431m) corresponding to the target task Task_m to the task queue of target processor core 432. At this time, the task queue of the target processor core 432 includes: task control information Command_a(432_1) corresponding to task Task_a, ..., task control information Command_N(432N) corresponding to task Task_N, and task control information Command_m(431_m) corresponding to the target task Task_m.

[0067] According to embodiments of this disclosure, the above-described permission migration operation may include the following operations:

[0068] From the contiguous address space of the exception processor core, obtain the address information of the target task and the association information of the target virtual device. By modifying the association information, the first association is severed; the first association represents the association between the target task and the target virtual device within the exception processor core. Based on the identification information of the target virtual device, determine the target address information from the contiguous address space of the target processor core. By changing the target address information to the address information of the target task, establish a second association; the second association represents the association between the target task and the target virtual device within the target processor core. Based on the second association, modify the permission information in the target task's control information.

[0069] Figure 5 A schematic diagram illustrating a permission migration operation according to an embodiment of the present disclosure is provided.

[0070] like Figure 5As shown in Figure 500, the contiguous address space 531 of the exception handler core may include the address information and virtual device association information of task 1 (531_1) and the address information and virtual device association information of the target task m (531_m). The address information and virtual device association information of the target task m may include: the address Address_m corresponding to the target task Task_m, and the address Address_m corresponding to the virtual device Equipment_m. This association indicates that the target task Task_m has input / output permissions for the virtual device Equipment_m within the exception handler core.

[0071] According to embodiments of this disclosure, the first association relationship is terminated by changing the association information. For example, the address information of the target task Task_m in the contiguous address space of the exception processor core and the association information (531_m) with the virtual device are changed to (531_m'). In the changed association information, the address corresponding to the target task Task_m is "empty", and since the address corresponds one-to-one with the virtual device, the corresponding virtual device is also "empty". This indicates that the target task Task_m no longer has input / output permissions for the virtual device Equipment_m in the exception processor core.

[0072] According to embodiments of this disclosure, a target virtual device, namely virtual device Equipment_m, can be determined from the contiguous address space 532 of the target processor core based on the virtual device identifier. At this time, the address in the association information 532m of virtual device Equipment_m in the contiguous address space 532 of the target processor core is "empty," indicating that no task in the target processor core has input / output permissions for virtual device Equipment_m.

[0073] According to embodiments of this disclosure, by changing the target address information from "empty" to the address of the target task, Address_m, an association between the target task Task_m and the virtual device Equipment_m is established in the contiguous address space 532 of the target processor core, resulting in the modified association information 532m': the address corresponding to the virtual device Equipment_m is Address_mm, and the task corresponding to Address_mm is the target task Task_m. This completes the input / output permission migration operation for the target task Task_m.

[0074] According to embodiments of this disclosure, the above-described stack migration operation may include the following operations:

[0075] Obtain stack content and stack space information from the target task control information. Based on the stack space information, create a target stack on the target processor core to obtain the target stack information. Copy the stack content information to the target stack. Modify the stack information in the target task control information based on the target stack information.

[0076] According to embodiments of this disclosure, the stack space information may include first stack top pointer information, first stack bottom pointer information, and stack length information. The above-described method of obtaining target stack information by creating a target stack area on the target processor core based on the stack space information may include the following operations:

[0077] Based on the stack length information, a target stack area is created within the target processor core's stack area, and the second stack bottom pointer information of the target stack area is recorded. Based on the first stack top pointer information and the first stack bottom pointer information, the stack pointer offset information is obtained. Based on the second stack bottom pointer information and the stack pointer offset information, the second stack top pointer information is obtained. Based on the second stack bottom pointer information and the second stack top pointer information, the information of the target stack area is obtained.

[0078] Figure 6 A schematic diagram illustrating a stack migration operation according to an embodiment of the present disclosure is provided.

[0079] According to an embodiment of this disclosure, in step 600, in the exception processor core 631, the stack area Stack_m (631m) corresponding to the target task Task_m is migrated to the target processor core 632 by performing a stack migration operation, and the stack content information of the stack area Stack_m (631m) is copied to the target stack area (632m) to complete the stack migration operation of the target task.

[0080] According to embodiments of this disclosure, the information of the stack area Stack_m may include the content information of the stack area Stack_m, such as the content information of the task function used to execute the target task; it may also include the space information of the stack area Stack_m, such as the stack top pointer information, the stack bottom pointer information, and the stack length information of the stack area Stack_m.

[0081] According to embodiments of this disclosure, a target stack region (632_m) can be created in the target processor core 632 based on the stack length information of the stack region Stack_m (631_m), wherein the stack length of the target stack region (632_m) is the same as the stack length of the stack region Stack_m (631_m). The second stack bottom pointer information of the target stack region (632_m) in the target processor core 632 is recorded at this time. Then, based on the stack pointer offset information of the stack region Stack_m (631_m) in the exception processor core and the second stack bottom pointer information, the second stack top pointer information of the target stack region (632_m) is obtained.

[0082] According to embodiments of this disclosure, the stack pointer offset information can be as shown in equation (1):

[0083] Stack pointer offset information = First stack top pointer information - First stack bottom pointer information (1)

[0084] According to embodiments of this disclosure, in the exception handler core, the first stack top pointer information represents the address of the last element entering the stack area Stack_m, and the first stack bottom pointer information represents the starting address of the stack area of ​​the exception handler core. The stack pointer offset information represents the distance between the actual address of the stack top and its starting address. For example, in the exception handler core, if the value of the starting address of the stack area is 49 and the value of the address of the last element entering the stack area Stack_m is 30, then the stack pointer offset information is -19. According to embodiments of this disclosure, the second stack top pointer information can be as shown in equation (2):

[0085] Second stack top pointer information = Second stack bottom pointer information + Stack pointer offset information (2)

[0086] According to embodiments of this disclosure, the second stack bottom pointer information represents the starting address of the stack area in the target processor core. For example, if the starting address of the stack area in the target processor core is 20, then the value of the address at which the last element entered the target stack area is 1.

[0087] According to embodiments of this disclosure, the stack information in the target task control information can be changed accordingly based on the second stack top pointer information and the second stack bottom pointer information of the target stack area, thereby completing the stack information change operation.

[0088] According to embodiments of this disclosure, the code segment migration operation may include the following operations:

[0089] The instruction content information, instruction space information, and first pointer address information for task switching of the code segment corresponding to the target task are obtained from the exception handler core. Based on the instruction space information and the first pointer address information, the target code segment is created in the target processor core, and its information is obtained. The instruction content information is copied to the target code segment. Based on the information in the target code segment, the code segment information in the target task control information is modified.

[0090] According to embodiments of this disclosure, the instruction space information includes first instruction address information and instruction length information. Based on the instruction space information and the first pointer address information, the information of the target code region is obtained by creating a target code region in the target processor core. This can include the following operations:

[0091] Based on the instruction length information, a target code segment is created within the code segment of the target processor core, and the second instruction address information of the target code segment is recorded. Based on the first instruction address information and the first pointer address information, pointer address offset information is obtained. Based on the pointer address offset information and the second instruction address information, the second pointer address information is obtained. Based on the second instruction address information and the second pointer address information, the information of the target code segment is obtained.

[0092] Figure 7 A schematic diagram illustrating a code segment migration operation according to an embodiment of the present disclosure is shown.

[0093] like Figure 7 As shown in 700, in the exception handler core 731, the code segment Code_m (731_m) corresponding to the target task Task_m is created in the target processor core 732 by performing a code segment migration operation, and the code segment content information of the code segment Code_m (731_m) is copied into the target code segment (732_m), thus completing the code segment migration operation of the target task.

[0094] According to embodiments of this disclosure, since code regions cannot be allocated during system runtime, candidate code regions with different instruction spaces can be pre-allocated in the processor core. These candidate code regions do not contain task instruction information, in order to facilitate code region migration operations.

[0095] According to embodiments of this disclosure, a target code segment with the same instruction length as code segment m can be created in the target processor core 732 based on the instruction length information, and the second instruction address information of the target code segment can be recorded. The second instruction address information may be the address information of the first instruction of the target code segment.

[0096] According to embodiments of this disclosure, the code segment stores instruction information corresponding to the target task. Besides different instruction information, different tasks also require pointer information for task switching. Generally, the pointer information for task switching is stored in the stack area. When the target task migrates its code segment from the exception handler core to the target processor core, the pointer information for task switching also needs to be changed accordingly.

[0097] According to embodiments of this disclosure, pointer address offset information can be obtained according to equation (3):

[0098] Pointer address offset information = First pointer address information - First instruction address information (3)

[0099] According to embodiments of this disclosure, the first instruction address information can be the starting address of the code segment in the exception handler core defined in the linker script, and the first pointer address information can be the content address in the exception handler core defined in the linker script used to point to the execution of the next task. For example, the value of the starting address can be 30, the value of the pointer address can be 50, and the pointer address offset can be 20.

[0100] According to an embodiment of this disclosure, the second pointer address information can be obtained according to formula (4).

[0101] Second pointer address information = pointer address offset information + second instruction address information (4)

[0102] According to embodiments of this disclosure, the second instruction address information can be the starting address of the code segment in the target processor core as defined in the linker script. For example, if the value of the second instruction address is 10, then in the target processor core, the value of the content address used to point to the execution of the next task is 30.

[0103] According to embodiments of this disclosure, the code section information in the target task control information can be modified accordingly based on the second pointer address information and the second instruction address information of the target code section, thereby completing the code section information modification operation.

[0104] According to the embodiments of this disclosure, after the migration of task control information, permission, stack area and code area are completed in sequence, the migration operation of the target task from the exception handler core to the target processor core is completed.

[0105] It should be noted that under normal operating conditions in an asymmetric multiprocessor system, the different tasks running on different processor cores can easily lead to uneven processor core load. To address this, tasks with lower core utilization on processor cores with higher load rates can be selected as target tasks. These target tasks are then migrated to processor cores with lower load rates. The migration process involves sequentially migrating task control information, permissions, stack area, and code area.

[0106] Figure 8 A block diagram of a task migration apparatus according to an embodiment of the present disclosure is shown schematically.

[0107] like Figure 8 As shown, the task migration device in this embodiment includes an acquisition module 910, a first determination module 820, a second determination module 830, and a migration module 840.

[0108] The acquisition module 910 is used to acquire load information and error information of the abnormal processor core of the asymmetric multiprocessor system in response to detecting an operational anomaly in the asymmetric multiprocessor system. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. In one embodiment, the acquisition module 910 is used to implement the operation S210 described above, which will not be repeated here.

[0109] The first determining module 820 is used to determine, based on error information, at least one candidate processor core and the target task to be migrated from among a plurality of processor cores. In one embodiment, the first determining module 820 is used to implement the operation S220 described above, which will not be repeated here.

[0110] The second determining module 830 is used to determine a target processor core from at least one candidate processor core based on load information. In one embodiment, the second determining module 830 is used to perform the operation S230 described above, which will not be repeated here.

[0111] The migration module 840 is used to migrate the target task to the target processor core. In one embodiment, the migration module 840 is used to perform the operation S240 described above, which will not be repeated here.

[0112] According to embodiments of this disclosure, the first determining module 820 may include a first obtaining submodule, a second obtaining submodule, and a first determining submodule. The first obtaining submodule is used to parse error information to obtain the degree of impact of the error information on the abnormal processor core. The second obtaining submodule is used to filter target tasks to be migrated from the task queue of the abnormal processor core based on the degree of impact. The first determining submodule is used to determine at least one candidate processor core from a plurality of processor cores based on the target task to be migrated.

[0113] According to embodiments of this disclosure, the second determining module 830 may include a third obtaining submodule and a second determining submodule. The third obtaining submodule is used to sort at least one candidate processor core based on load information to obtain a sorting result. The second determining submodule is used to determine a target processor core from the at least one candidate processor core based on a selection strategy and the sorting result.

[0114] According to embodiments of this disclosure, the migration module 840 may include: an acquisition submodule, a first migration submodule, and a second migration submodule. The acquisition submodule is used to acquire target task control information corresponding to the target task. The first migration submodule is used to migrate the target task control information to the task queue of the target processor core. The second migration submodule is used to sequentially perform permission migration operations, stack migration operations, and code segment migration operations on the target task control information.

[0115] According to embodiments of this disclosure, the second migration submodule may include: a first acquisition unit, a release unit, a determination unit, a first modification unit, and a second modification unit. The first acquisition unit is used to acquire the address information of the target task and the association information of the target virtual device from the contiguous address space of the abnormal processor core. The release unit is used to release the first association relationship by modifying the association information; the first association relationship represents the association relationship between the target task and the target virtual device in the abnormal processor core. The determination unit is used to determine the target address information from the contiguous address space of the target processor core based on the identification information of the target virtual device. The first modification unit is used to establish a second association relationship by changing the target address information to the address information of the target task; the second association relationship represents the association relationship between the target task and the target virtual device in the target processor core. The second modification unit is used to modify the permission information in the target task control information according to the second association relationship.

[0116] According to embodiments of this disclosure, the second migration submodule may include a second acquisition unit, a first acquisition unit, a first copying unit, and a third modification unit. The second acquisition unit is used to acquire stack content information and stack space information from the target task control information. The first acquisition unit is used to obtain the target stack information by creating a target stack in the target processor core based on the stack space information. The first copying unit is used to copy the stack content information to the target stack. The third modification unit is used to modify the stack information in the target task control information based on the information of the target stack.

[0117] According to embodiments of this disclosure, the stack space information includes: first stack top pointer information, first stack bottom pointer information, and stack length information. The first obtaining unit may include a first creation subunit, a first obtaining subunit, a second obtaining subunit, and a third obtaining subunit. The first creation subunit is used to create a target stack area within the stack area of ​​the target processor core based on the stack length information, and to record the second stack bottom pointer information of the target stack area. The first obtaining subunit is used to obtain stack pointer offset information based on the first stack top pointer information and the first stack bottom pointer information. The second obtaining subunit is used to obtain second stack top pointer information based on the second stack bottom pointer information and the stack pointer offset information. The third obtaining subunit is used to obtain the information of the target stack area based on the second stack bottom pointer information and the second stack top pointer information.

[0118] According to embodiments of this disclosure, the second migration module may include a second acquisition unit, a second obtaining unit, a second copying unit, and a fourth modification unit. The second acquisition unit is used to acquire instruction content information, instruction space information, and first pointer address information for task switching from the exception processor core for the code segment corresponding to the target task. The second obtaining unit is used to obtain information about the target code segment by creating a target code segment in the target processor core based on the instruction space information and the first pointer address information. The second copying unit is used to copy the instruction content information to the target code segment. The fourth modification unit is used to modify the code segment information in the target task control information based on the information of the target code segment.

[0119] According to embodiments of this disclosure, the instruction space information includes first instruction address information and instruction length information. The second obtaining unit may include a second creation subunit, a fourth obtaining subunit, a fifth obtaining subunit, and a sixth obtaining subunit. The second creation subunit is used to create a target code segment within the code segment of the target processor core based on the instruction length information, and to record the second instruction address information of the target code segment. The fourth obtaining subunit is used to obtain pointer address offset information based on the first instruction address information and the first pointer address information. The fifth obtaining subunit is used to obtain second pointer address information based on the pointer address offset information and the second instruction address information. The sixth obtaining subunit is used to obtain information about the target code segment based on the second instruction address information and the second pointer address information.

[0120] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0121] According to an embodiment of the present disclosure, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described above.

[0122] According to embodiments of the present disclosure, a non-transitory computer-readable storage medium stores computer instructions, wherein the computer instructions are used to cause a computer to perform the method described above.

[0123] According to an embodiment of this disclosure, a computer program product includes a computer program that, when executed by a processor, implements the method described above.

[0124] Figure 9 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0125] like Figure 9 As shown, device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 902 or a computer program loaded from storage unit 908 into random access memory (RAM) 903. RAM 903 may also store various programs and data required for the operation of device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0126] Multiple components in device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of monitors, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0127] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as task migration methods. For example, in some embodiments, the task migration method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the task migration method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform task migration methods by any other suitable means (e.g., by means of firmware).

[0128] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0129] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0130] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0131] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0132] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0133] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, distributed system servers, or servers incorporating blockchain technology.

[0134] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0135] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A task migration method, comprising: In response to the detection of an operational anomaly in the asymmetric multiprocessor system, the load information of the asymmetric multiprocessor system and the error information of the abnormal processor core are obtained. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. Based on the error information, at least one candidate processor core among the plurality of processor cores and the target task to be migrated in the abnormal processor core are determined; Based on the load information, a target processor core is determined from the at least one candidate processor core; Obtain the target task control information corresponding to the target task; The target task control information is migrated to the task queue of the target processor core; as well as The permission migration operation, stack migration operation, and code segment migration operation are performed sequentially on the target task control information.

2. The method of claim 1, wherein, The step of determining at least one candidate processor core from the plurality of processor cores and the target task to be migrated from the abnormal processor core based on the error information includes: Analyze the error message to determine the extent of its impact on the abnormal processor core; Based on the degree of impact, the target tasks to be migrated are selected from the task queue of the exception processor core; and Based on the target task to be migrated, at least one candidate processor core is determined from the plurality of processor cores.

3. The method of claim 1, wherein, The step of determining the target processor core from the at least one candidate processor core based on the load information includes: Based on the load information, the at least one candidate processor core is sorted to obtain a sorting result; and Based on the selection strategy, the target processor core is determined from the at least one candidate processor core according to the sorting results.

4. The method of claim 1, wherein, The permission migration operation includes: Obtain the address information of the target task and the association information of the target virtual device from the contiguous address space of the exception processor core; By changing the association information, the first association relationship is terminated. The first association relationship represents the association relationship between the target task and the target virtual device in the abnormal processor core. Based on the identification information of the target virtual device, the target address information is determined from the contiguous address space of the target processor core; By changing the target address information to the address information of the target task, a second association is established. This second association represents the association between the target task and the target virtual device within the target processor core. Based on the second association relationship, the permission information in the target task control information is changed.

5. The method of claim 1, wherein, The stack migration operation includes: Obtain stack area content information and stack area space information from the target task control information; Based on the stack space information, the target stack area information is obtained by creating a target stack area on the target processor core; Copy the contents of the stack area to the target stack area; and Based on the information in the target stack area, modify the stack area information in the target task control information.

6. The method of claim 5, wherein, The stack space information includes: first stack top pointer information, first stack bottom pointer information, and stack length information; the step of obtaining the target stack area information by creating a target stack area on the target processor core based on the stack space information includes: Based on the stack length information, a target stack area is created within the stack area of ​​the target processor core, and the second stack bottom pointer information of the target stack area is recorded; Based on the first stack top pointer information and the first stack bottom pointer information, the stack pointer offset information is obtained; Based on the second stack bottom pointer information and the stack pointer offset information, the second stack top pointer information is obtained; and The information of the target stack area is obtained based on the second stack bottom pointer information and the second stack top pointer information.

7. The method of claim 1, wherein, The code segment migration operation includes: The error handler core obtains the instruction content information, instruction space information, and first pointer address information for task switching of the code segment corresponding to the target task; Based on the instruction space information and the first pointer address information, the target code region information is obtained by creating a target code region in the target processor core; Copy the instruction content information to the target code area; and Based on the information in the target code area, modify the code area information in the target task control information.

8. The method according to claim 7, wherein, The instruction space information includes first instruction address information and instruction length information. The step of obtaining information about the target code region by creating a target code region in the target processor core based on the instruction space information and the first pointer address information includes: Based on the instruction length information, the target code segment is created within the code segment of the target processor core, and the second instruction address information of the target code segment is recorded; Based on the first instruction address information and the first pointer address information, the pointer address offset information is obtained; Based on the pointer address offset information and the second instruction address information, the second pointer address information is obtained; and The information of the target code area is obtained based on the second instruction address information and the second pointer address information.

9. A task migration device, comprising: The acquisition module is used to acquire the load information of the asymmetric multiprocessor system and the error information of the abnormal processor core in response to the detection of an operational abnormality in the asymmetric multiprocessor system. The asymmetric multiprocessor system includes multiple processor cores with independent memory address spaces. The first determining module is used to determine, based on the error information, at least one candidate processor core among the plurality of processor cores and the target task to be migrated among the abnormal processor cores; The second determining module is used to determine the target processor core from the at least one candidate processor core based on the load information; The migration module includes: The acquisition submodule is used to acquire target task control information corresponding to the target task. A first migration submodule is used to migrate the target task control information to the task queue of the target processor core; and The second migration submodule is used to sequentially perform permission migration operation, stack area migration operation, and code area migration operation on the target task control information.

10. The apparatus according to claim 9, wherein, The first determining module includes: The first acquisition submodule is used to parse the error information and obtain the degree of impact of the error information on the abnormal processor core; The second acquisition submodule is used to filter the target task to be migrated from the task queue of the exception processor core according to the degree of impact; and The first determining submodule is used to determine at least one candidate processor core among the plurality of processor cores based on the target task to be migrated.

11. The apparatus according to claim 10, wherein, The second determining module includes: The third obtaining submodule is used to sort the at least one candidate processor core according to the load information to obtain a sorting result; and The second determining submodule is used to determine the target processor core from the at least one candidate processor core based on the selection strategy and the sorting result.

12. The apparatus according to claim 9, wherein, The second migration submodule includes: The first acquisition unit is used to acquire the address information of the target task and the association information of the target virtual device from the continuous address space of the abnormal processor core; The termination unit is used to terminate the first association relationship by changing the association information, wherein the first association relationship represents the association relationship between the target task and the target virtual device in the abnormal processor core; The determining unit is configured to determine target address information from the contiguous address space of the target processor core based on the identification information of the target virtual device; The first modification unit is configured to establish a second association by modifying the target address information to the address information of the target task, wherein the second association represents the association between the target task and the target virtual device in the target processor core; and The second modification unit is used to modify the permission information in the target task control information according to the second association relationship.

13. The apparatus according to claim 9, wherein, The second migration submodule includes: The second acquisition unit is used to acquire stack area content information and stack area space information from the target task control information; The first obtaining unit is configured to obtain information about the target stack area by creating a target stack area in the target processor core based on the stack area space information. The first copying unit is used to copy the stack area content information to the target stack area; and The third modification unit is used to modify the stack area information in the target task control information according to the information of the target stack area.

14. The apparatus according to claim 13, wherein, The stack space information includes: first stack top pointer information, first stack bottom pointer information, and stack length information; the first obtaining unit includes: The first creation subunit is used to create a target stack area within the stack area of ​​the target processor core according to the stack length information, and to record the second stack bottom pointer information of the target stack area; The first obtaining sub-unit is used to obtain stack pointer offset information based on the first stack top pointer information and the first stack bottom pointer information; The second obtaining subunit is used to obtain the second stack top pointer information based on the second stack bottom pointer information and the stack pointer offset information; and The third obtaining subunit is used to obtain the information of the target stack area based on the second stack bottom pointer information and the second stack top pointer information.

15. The apparatus according to claim 9, wherein, The second migration submodule includes: The second acquisition unit is used to acquire from the exception processor core the instruction content information, instruction space information and first pointer address information for task switching of the code area corresponding to the target task; The second obtaining unit is used to obtain information about the target code region by creating a target code region in the target processor core based on the instruction space information and the first pointer address information; A second copying unit is used to copy the instruction content information to the target code area; and The fourth modification unit is used to modify the code area information in the target task control information according to the information in the target code area.

16. The apparatus according to claim 15, wherein, The instruction space information includes first instruction address information and instruction length information, and the second obtaining unit includes: The second creation subunit is used to create the target code region within the code region of the target processor core according to the instruction length information, and to record the second instruction address information of the target code region; The fourth obtaining subunit is used to obtain pointer address offset information based on the first instruction address information and the first pointer address information; The fifth obtaining subunit is used to obtain the second pointer address information based on the pointer address offset information and the second instruction address information; and The sixth obtaining subunit is used to obtain the information of the target code area based on the second instruction address information and the second pointer address information.

17. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

18. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8.

19. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-8.

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