Method for communication between processor cores, multi-processor platform and readable storage medium

Abstract

Embodiments of the present invention provide a method for inter-processor core communication, a multi-processor platform, and a storage medium. The method is applied to a multi-processor platform comprising a master core and at least one slave core, the at least one slave core being on a different CPU from the master core. The method comprises: during a basic input / output system startup phase, the master core obtains the initialization status of a random access memory (RAM) and the connection status of a bus; upon determining that RAM initialization is complete and that the bus connection status meets preset conditions, the master core writes a preset flag into a predetermined register of the slave core via the bus, the preset flag being used to indicate that RAM initialization is complete; and the slave core obtains the RAM initialization status by cyclically monitoring its own predetermined register for the presence of the preset flag. Embodiments of the present invention can improve the stability and performance of the multi-processor platform.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for communication between processor cores, a multi-processor platform, and a readable storage medium. Background Art

[0002] When multiple central processing units (CPUs) are interconnected, the master core of the main CPU performs most of the initialization work during the Basic Input / Output System (BIOS) startup phase. To ensure normal execution from read-only memory (ROM) to random access memory (RAM) during the BIOS startup process, the slave cores of the slave CPUs must repeatedly obtain RAM initialization information from the master core via the HT bus. Hyper Transport (HT) is an end-to-end bus technology designed for interconnecting integrated circuits on motherboards.

[0003] However, while the slave core is receiving RAM initialization information from the master core via the HT bus, the master core may not have completed HT bus initialization. During HT bus initialization, the original low-speed hardware connection must be configured, followed by a software reconnection to complete HT bus initialization. Therefore, at some point during HT bus initialization, the HT bus may be disconnected. If a slave core accesses the HT bus at the same time as the HT bus is disconnected, the access address of the slave core will become an unreachable, invalid address, causing the core to lock up and become unresponsive, impacting the stability and performance of the multiprocessor platform. Summary of the Invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a method for communication between processor cores that overcomes the above problems or at least partially solves the above problems. It can avoid the overlap between the access time of the slave core to the bus and the time when the bus is disconnected, and can avoid the occurrence of the slave core being locked or losing response, thereby improving the stability and performance of the multi-processor platform.

[0005] Correspondingly, an embodiment of the present invention further provides a multi-processor platform and a readable storage medium to ensure the implementation and application of the above method.

[0006] To solve the above problem, an embodiment of the present invention discloses a method for communication between processor cores, which is applied to a multi-processor platform. The multi-processor platform includes a master core and at least one slave core, where the at least one slave core is on a CPU different from the CPU where the master core is located. The method includes:

[0007] During the basic input and output system startup phase, the main core obtains the initialization status of the random access memory RAM and the connection status of the bus;

[0008] When the master core determines that the RAM initialization is completed and the bus connection status satisfies a preset condition, the master core writes a preset flag into a predetermined register of the slave core via the bus, where the preset flag is used to indicate that the RAM initialization status is completed;

[0009] The slave core monitors in a loop whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM.

[0010] An embodiment of the present invention further discloses a multi-processor platform, comprising a master core and at least one slave core, wherein the at least one slave core is on a CPU different from the CPU where the master core is located, wherein:

[0011] The main core includes a state acquisition unit for acquiring the initialization state of the random access memory RAM and the connection state of the bus during the basic input and output system startup phase;

[0012] The master core further includes a flag writing unit, configured to write a preset flag into a predetermined register of the slave core via the bus when it is determined that the RAM initialization is completed and the bus connection status satisfies a preset condition, wherein the preset flag is used to indicate that the RAM initialization status is completed;

[0013] The slave core includes a flag monitoring unit, which is used to cyclically monitor whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM.

[0014] An embodiment of the present invention further discloses a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, one or more of the methods for inter-processor core communication described in the embodiment of the present invention can be implemented.

[0015] The embodiments of the present invention include the following advantages:

[0016] The embodiment of the present invention improves the method of communication between processor cores without changing the hardware of the multi-processor platform. When the master core determines that the RAM initialization is complete and that the bus connection status meets the preset conditions, the master core writes a preset flag into the predetermined register of the slave core through the bus, so that the slave core can obtain the initialization status of the RAM by cyclically monitoring whether the preset flag exists in its own predetermined register. While ensuring that the running address of the slave core can jump normally, it can avoid the slave core accessing the bus in an unknown state, thereby avoiding the slave core's access time to the bus and the bus disconnection time from coinciding, avoiding the slave core from being locked or losing response, and thus improving the stability and performance of the multi-processor platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flowchart of an embodiment of a method for communication between processor cores of the present invention;

[0018] Figure 2 1 is a schematic diagram comparing the processes of an example of a method for communication between processor cores of the present invention and an example of a conventional method for communication between processor cores;

[0019] Figure 3 It is a structural block diagram of an embodiment of a multi-processor platform 300 of the present invention. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Method Example

[0022] Reference Figure 1 , shows a flowchart of an embodiment of a method for communication between processor cores of the present invention. The method can be applied to a multi-processor platform, wherein the multi-processor platform includes a master core and at least one slave core, wherein the at least one slave core is on a CPU different from the CPU where the master core is located. The method may specifically include the following steps:

[0023] Step 101: During the basic input / output system startup phase, the main core obtains the initialization status of the random access memory (RAM) and the connection status of the bus.

[0024] Step 102: When the master core determines that RAM initialization is complete and the bus connection status satisfies a preset condition, the master core writes a preset flag into a predetermined register of the slave core via the bus, where the preset flag is used to indicate that the RAM initialization status is complete.

[0025] Step 103: The slave core cyclically monitors whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM.

[0026] The method provided in the embodiments of the present invention can be applied to a multi-processor platform. In the embodiments of the present invention, a multi-processor platform refers to a platform with multiple processing cores. The platform may include multiple CPUs, each of which may include at least one core. All CPUs in the platform include a master CPU and at least one slave CPU. The master core is located on the master CPU, and the cores in the slave CPUs are referred to as slave cores.

[0027] In an example, the multi-processor platform may be a Loongson multi-processor platform. Furthermore, the basic input and output system BIOS may be, for example, a PMON.

[0028] In practical applications, the main CPU's master core performs most of the initialization work during the startup phase of a basic input / output system (BIOS) (such as PMON or uboot), including RAM initialization. After RAM initialization is complete, the master core typically stores a preset flag, such as the SYSTEM_INIT_OK flag, in its own predefined registers. This flag indicates that RAM initialization is complete. The slave core accesses the master core's predefined registers to obtain the RAM initialization status. If the slave core determines that RAM initialization is complete, it jumps the execution address from ROM to RAM.

[0029] If the time when the slave core accesses the bus coincides with the disconnection time during the bus initialization process, the access address of the slave core will become an unreachable invalid address, causing the slave core to lock and lose response, thereby affecting the stability and performance of the multi-processor platform.

[0030] To solve this problem, an embodiment of the present invention improves the method of communication between processor cores in a multi-processor platform, so that the process of obtaining the RAM initialization status from the core does not depend on the bus, so as to avoid the time of accessing the bus from the core coinciding with the disconnection time during the bus initialization process, thereby improving the stability and performance of the multi-processor platform.

[0031] Specifically, in an embodiment of the present invention, during the startup phase of a basic input / output system (such as PMON or uboot), the master core obtains the initialization status of the random access memory (RAM) and the bus connection status. Upon determining that RAM initialization is complete and that the bus connection status satisfies a preset condition, the master core writes a preset flag into a predetermined register of the slave core via the bus. The preset flag is used to indicate that the RAM initialization status is complete, for example, the preset flag is 5a5a. In this way, the slave core can obtain the RAM initialization status by cyclically monitoring whether the preset flag is present in its own predetermined register.

[0032] In an optional embodiment of the present invention, the bus may include an HT bus and / or a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) bus. For ease of description, the present invention mainly uses the HT bus as an example for explanation. In a multi-processor platform, different CPUs can be connected via an HT bus, which may be an HT0 / HT1 bus, and the HT bus may be an 8-bit bus.

[0033] In an optional embodiment of the present invention, the predetermined register may be a mail box register.

[0034] The MAILBOX register is a dedicated register for inter-core communication. When it is determined that RAM initialization is complete and the bus connection status meets preset conditions, the embodiment of the present invention writes a preset flag into the MAILBOX register of the slave core via the bus.

[0035] In an optional embodiment of the present invention, writing the preset flag into a predetermined register of the slave core via the bus includes:

[0036] Obtaining an address of a predetermined register of a slave core in the multiprocessor platform;

[0037] Preset flags are written into addresses of predetermined registers of the slave cores respectively.

[0038] In one example, a multiprocessor platform includes two CPUs: CPU1 and CPU2. CPU1 is the master CPU, containing a master core, and CPU2 is the slave CPU, containing two slave cores. After the master core determines that RAM initialization is complete and the bus connection status meets preset conditions, it obtains the addresses of predetermined registers of CPU2's two slave cores and writes preset flags to the addresses of the predetermined registers of each of CPU2's two slave cores. Assuming the addresses of the predetermined registers of CPU2's two slave cores are p1 and p2, respectively, the preset flags are written to p1 and p2, respectively.

[0039] It should be noted that the preset flag is used to indicate that the RAM initialization state is complete. The embodiment of the present invention does not limit the specific content of the preset flag. The preset flag can be a preset value or string, etc. For example, in the above example, the preset flag 5a5a can be written to p1 and p2 respectively.

[0040] In an optional embodiment of the present invention, after the slave core cyclically monitors whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM, the method may further include:

[0041] When the slave core finds that the preset flag exists in its own predetermined register, it determines that the initialization state of the RAM is completed, and then the slave core jumps the running address from the read-only memory ROM to the RAM.

[0042] The execution address refers to the execution address of a basic input / output system instruction. With the embodiments of the present invention, the slave core can obtain the initialization status of the RAM by cyclically monitoring its own predetermined registers, and can then jump its execution address from the read-only memory (ROM) to the RAM without repeatedly accessing the HT bus. This prevents the slave core from accessing the HT bus while disconnecting the bus during initialization.

[0043] In an optional embodiment of the present invention, obtaining the initialization state of the random access memory RAM includes:

[0044] The main core obtains the RAM initialization state of the specified segment address, and the preset flag is used to indicate that the RAM initialization state of the specified segment address is in a completed state.

[0045] Currently, the main computer architectures can be divided into two categories, CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing).

[0046] Taking one computer architecture as an example, the division and naming of the address space are fixed. The address space consists of physical space and virtual space (also known as logical space). For example, in a 64-bit architecture, the address space is divided into four segments: kuseg, kseg0, kseg1, and kseg2. Kuseg represents the address space available in user mode. Kuseg and kseg2 are mapped addresses. This means that the correspondence between the logical and physical space of this address space segment is determined by the Translation Lookaside Buffer (TLB) entries in the Memory Management Unit (MMU). Accessing this physical space requires a TLB translation. kseg0 and kseg1 are unmapped addresses; accessing this physical space does not require a TLB translation. For example, kseg0 represents the address space from 0x80000000 to 0x9fffffff (512MB). Access to this physical space does not require a TLB translation and instead goes through the cache. Usually the boot loader and kernel use the kseg0 address space.

[0047] In the embodiment of the present invention, the designated segment address refers to the kseg0 segment address.

[0048] The CPU determines the routing of lower-level accesses based on the execution address of the current instruction. The kesg0 segment is a portion of the execution address. The characteristic of this portion is that all accesses first pass through RAM (also known as the cache). The CPU's interaction with RAM is several orders of magnitude faster than that with ROM. Therefore, after the CPU initializes RAM, it redirects the CPU's execution address from ROM to RAM.

[0049] In an embodiment of the present invention, after the main CPU of the multi-processor platform is powered on, during the basic input and output system startup phase, after the RAM initialization of the kesg0 segment address is completed, the main core of the main CPU can broadcast information to all slave cores and write preset flags such as 5a5a into the predetermined registers of all slave cores.

[0050] Furthermore, in order to prevent the occurrence of inter-core communication deadlock, in an embodiment of the present invention, the master core writes a preset flag into the predetermined register of the slave core through the HT bus when it determines that the RAM initialization of the kesg0 segment address is completed and the connection status of the HT bus meets the preset conditions. It can be seen that the master core has confirmed that the HT bus connection is stable before writing the preset flag, so it can be considered that the HT bus at this time is reliable and available, and no abnormalities will occur. The slave core can obtain the RAM initialization status of the kesg0 segment address by cyclically monitoring whether there is a preset flag in its own predetermined register. When the slave core queries its own predetermined register for the presence of the preset flag, it determines that the RAM initialization status of the kesg0 segment address is completed, and then the slave core jumps the running address from the read-only memory ROM to the RAM.

[0051] Through the embodiment of the present invention, the flag information that the master core originally needs to store in its own predetermined register is written to the predetermined register of all slave cores via the HT bus when the master core determines that the HT bus connection is stable and the RAM at the kesg0 segment address is initialized. This allows the slave core to query the available time of the RAM at the kesg0 segment address by cyclically monitoring its own predetermined register, thereby avoiding the slave core's repeated access to the HT bus. Therefore, through the embodiment of the present invention, while ensuring that the slave core can jump normally, it can avoid the slave core's access time to the HT bus coinciding with the HT bus disconnection time, and can avoid the slave core from locking and losing response, thereby improving the stability and performance of the multi-processor platform.

[0052] In an optional embodiment of the present invention, determining whether the connection state of the bus satisfies a preset condition includes:

[0053] The main core performs software initialization on the bus after the bus is powered on for the first time and the hardware is automatically connected;

[0054] After the bus software initialization is completed, the main core tests the stability of the bus connection. If the bus connection is detected to be stable, it is determined that the bus connection status meets the preset conditions. If the bus connection is detected to be unstable, the bus stabilization operation continues.

[0055] After the HT bus is initially powered on and the hardware is automatically connected, the main core performs software initialization on the HT bus. After the HT bus software initialization is complete, the main core tests the stability of the HT bus connection. Because the main core executes completely single-threaded and linearly, if the main core detects an unstable HT bus connection, it will continue to stabilize the HT until the HT bus connection is stable.

[0056] In an optional embodiment of the present invention, the stability of the bus connection can be tested by a cyclic redundancy check (CRC). Cyclic redundancy check is a calculation method used to verify the accuracy of data transmission on a communication link. The basic idea of ​​CRC check is that before the data sender sends the data, it generates a CRC check code, attaches it to the end of the valid data, and sends it to the receiver in a serial manner. After receiving the data, the receiver performs a CRC check, and can know whether the data is incorrect based on the check result. The embodiment of the present invention can randomly generate data to be transmitted, generate a CRC check code for the data, attach it to the end of the data, transmit the data in a serial manner through the bus, and perform a CRC check after receiving the data. If the check result is correct, it can be determined that the HT bus connection is stable; otherwise, it is determined that the HT bus connection is unstable.

[0057] It should be noted that the above-mentioned cyclic redundancy check is only used as an example of an application of the present invention, and the present invention does not limit the method of testing the stability of the bus connection. For example, a parity check, a Hamming check, etc. can also be used.

[0058] If the bus connection is detected to be stable, a preset flag is written into a predetermined register of the slave core via the bus. If the bus connection is detected to be unstable, a stabilization operation is performed on the bus.

[0059] Optionally, the stabilizing operation on the bus includes: adopting an 8b / 10b encoding method and / or reducing a connection rate of the bus.

[0060] In one optional embodiment, if the bus connection is detected as unstable, 8b / 10b encoding can be used to stabilize the bus. Using 8b / 10b encoding to transmit data ensures a consistent number of transmitted "0s" and "1s," with no more than five consecutive "1s" or "0s" occurring. This ensures DC signal balance. 8b / 10b encoding ensures that the transmitted data stream is correctly restored at the receiving end, preventing further errors and improving bus connection stability.

[0061] Furthermore, when the 8b / 10b encoding method is adopted, if it is detected that the bus connection is still unstable, the bus connection rate can be reduced to stabilize the bus.

[0062] It is understandable that, in specific implementations, the bus stabilization operation can be performed by using only the 8b / 10b encoding method or by reducing the bus connection rate, or a combination of the two. This embodiment of the present invention does not limit this.

[0063] Reference Figure 2 , shows a schematic diagram comparing the process of the method for inter-processor core communication according to an embodiment of the present invention and the conventional method for inter-processor core communication. Figure 2 As shown, the predetermined register is the MAILBOX register. It can be seen that through the embodiment of the present invention, the master core broadcasts the RAM initialization completion information (i.e., the preset flag mentioned above) and stores it in the MAILBOX register of the slave core. The slave core can obtain the RAM initialization status by cyclically monitoring its own MAILBOX register, and then can jump the running address from the read-only memory ROM to the RAM. In the startup process of the slave core, the embodiment of the present invention can avoid the slave core from accessing the HT bus in an unknown state, so that the slave core can stably jump into the kesg0 segment RAM to continue working. The embodiment of the present invention can send the RAM initialization information required by the slave core directly to the MAILBOX register of the slave core itself without changing the hardware of the multi-processor platform, thereby avoiding the overlap between the slave core's access time to the HT bus and the HT bus disconnection time, and avoiding the occurrence of the slave core locking and loss of response, thereby improving the stability and performance of the multi-processor platform.

[0064] In an optional embodiment of the present invention, the multi-processor platform may include a master CPU and at least one slave CPU, the master core is located on the master CPU, and when the master CPU also includes at least one slave core, writing the preset flag into a predetermined register of the slave core in the multi-processor platform through a bus includes:

[0065] The master core writes a preset flag into a predetermined register of a slave core of the master CPU in the multi-processor platform;

[0066] The master core writes the preset flag into a predetermined register of the slave core of the slave CPU in the multi-processor platform through a bus.

[0067] In practical applications, multi-processor platforms mostly use one core among the multiple cores as the master core, which is responsible for major resource management and complex logical operations, and the other cores as slave cores, which are responsible for tasks with simple logic but large data volumes.

[0068] In an embodiment of the present invention, a multi-processor platform may include a master CPU and at least one slave CPU. The master CPU may be a multi-core CPU including a master core and at least one slave core. The cores of the slave CPUs in the multi-processor platform are all referred to as slave cores.

[0069] In an embodiment of the present invention, the main core may write a preset flag into a predetermined register of a slave core of a slave CPU in the multi-processor platform through the bus when it determines that RAM initialization is completed and that the connection status of the bus meets the preset conditions; or, the main core may write a preset flag into a predetermined register of a slave core of a slave CPU in the multi-processor platform when it determines that RAM initialization is completed and that the connection status of the bus meets the preset conditions, and the main core may write a preset flag into a predetermined register of a slave core of a slave CPU in the multi-processor platform through the bus.

[0070] In one example, a multi-processor platform includes the following two CPUs: CPU1 and CPU2. Among them, CPU1 is the master CPU, CPU1 includes a master core and a slave core, CPU2 is the slave CPU, CPU2 includes two slave cores. When the master core determines that the RAM initialization is completed and that the connection status of the bus meets the preset conditions, it obtains the address of the predetermined register of the slave core of CPU1 and the address of the predetermined register of the two slave cores of CPU2, and writes preset flags to the address of the predetermined register of the slave core of CPU1 and the address of the register of the two slave cores of CPU2 respectively. Assuming that the address of the predetermined register of the slave core of CPU1 is recorded as p1, and the addresses of the predetermined registers of the two slave cores of CPU2 are recorded as p2 and p3 respectively, the preset flags are written to p1, p2, and p3 respectively.

[0071] In summary, the embodiment of the present invention improves the method of communication between processor cores without changing the hardware of the multi-processor platform. When the master core determines that the RAM initialization is completed and that the connection status of the bus meets the preset conditions, the master core writes a preset flag into the predetermined register of the slave core through the bus, so that the slave core can obtain the initialization status of the RAM by cyclically monitoring whether the preset flag exists in its own predetermined register. While ensuring that the running address of the slave core can jump normally, it can avoid the slave core accessing the bus in an unknown state, thereby avoiding the slave core's access time to the bus coinciding with the bus disconnection time, avoiding the slave core from being locked or losing response, and thus improving the stability and performance of the multi-processor platform.

[0072] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0073] Device embodiment

[0074] Reference Figure 3 , shows a structural block diagram of an embodiment of a multi-processor platform 300 of the present invention, wherein the multi-processor platform 300 includes a master core 301 and at least one slave core 302. In an embodiment of the present invention, the multi-processor platform may include a master core and at least one slave core, wherein the at least one slave core is on a CPU different from the CPU where the master core is located.

[0075] The main core 301 includes a status acquisition unit for acquiring the initialization status of the random access memory RAM and the connection status of the bus during the basic input and output system startup phase;

[0076] The master core 301 further includes a flag writing unit, configured to write a preset flag into a predetermined register of the slave core via the bus when determining that RAM initialization is completed and the bus connection status satisfies a preset condition, wherein the preset flag is used to indicate that the RAM initialization status is completed;

[0077] The slave core 302 includes a flag monitoring unit configured to cyclically monitor whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM.

[0078] The multi-processor platform 300 may include a master CPU and at least one slave CPU. The master core is located on the master CPU, and the cores of the slave CPUs in the multi-processor platform are all referred to as slave cores.

[0079] Optionally, the slave core further includes an address jump unit for determining that the initialization state of the RAM is completed when the preset flag is found in its own predetermined register, and the slave core then jumps the running address from the read-only memory ROM to the RAM.

[0080] Optionally, the main core further comprises a bus initialization unit for performing software initialization on the bus after the bus is powered on for the first time and the hardware is automatically connected; and

[0081] The main core also includes a connection test unit for testing the stability of the bus connection after the bus software initialization is completed. If the bus connection is detected to be stable, it is determined that the bus connection status meets the preset conditions. If the bus connection is detected to be unstable, the bus stabilization operation is continued.

[0082] Optionally, the connection test unit is further configured to test the stability of the bus connection by a cyclic redundancy check, and / or to perform a bus stabilization operation by adopting an 8b / 10b encoding method and / or by reducing the bus connection rate.

[0083] Optionally, the status acquisition unit is further used to acquire the RAM initialization status of the specified segment address, and the preset flag is used to indicate that the RAM initialization status of the specified segment address is a completed state.

[0084] Optionally, the master CPU may be a multi-core CPU. In this case, the master CPU also includes at least one slave core. In this case, the flag writing unit includes:

[0085] A first writing unit, configured to write a preset flag into a predetermined register of a slave core of the master CPU in the multi-processor platform;

[0086] The second writing unit is configured to write the preset flag into a predetermined register of the slave core of the slave CPU in the multi-processor platform through a bus.

[0087] Optionally, the bus includes an HT bus and / or a PCIE bus.

[0088] Optionally, the predetermined register may be a MAILBOX register.

[0089] In summary, the embodiment of the present invention improves the method of communication between processor cores without changing the hardware of the multi-processor platform. When the master core determines that the RAM initialization is completed and that the connection status of the bus meets the preset conditions, the master core writes a preset flag into the predetermined register of the slave core through the bus, so that the slave core can obtain the initialization status of the RAM by cyclically monitoring whether the preset flag exists in its own predetermined register. While ensuring that the running address of the slave core can jump normally, it can avoid the slave core accessing the bus in an unknown state, thereby avoiding the slave core's access time to the bus coinciding with the bus disconnection time, avoiding the slave core from being locked or losing response, and thus improving the stability and performance of the multi-processor platform.

[0090] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0091] An embodiment of the present invention provides a readable storage medium. When instructions in the storage medium are executed by a program or processor of a terminal, the terminal is enabled to execute a method for communication between processor cores. The method is applied to a multi-processor platform, and the multi-processor platform includes a master core and at least one slave core. The method includes: the master core obtains the initialization status of a random access memory RAM and the connection status of a bus during the startup phase of a basic input and output system; when the master core determines that RAM initialization is complete and that the connection status of the bus meets preset conditions, the master core writes a preset flag into a predetermined register of the slave core via the bus, and the preset flag is used to indicate that the initialization status of the RAM is completed; the slave core cyclically monitors whether the preset flag exists in its own predetermined register to obtain the initialization status of the RAM.

[0092] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0093] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0095] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0097] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0098] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0099] The above is a detailed introduction to a method for inter-processor core communication, a multi-processor platform, and a readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A method for communication between processor cores, characterized in that: Applied to a multi-processor platform, the multi-processor platform includes a master core and at least one slave core, the at least one slave core being on a CPU different from the CPU where the master core is located, the method comprising: During the basic input and output system startup phase, the main core obtains the initialization status of the random access memory RAM and the connection status of the bus; When the master core determines that the RAM initialization is completed and the bus connection status satisfies a preset condition, the master core writes a preset flag into a predetermined register of the slave core via the bus, where the preset flag is used to indicate that the RAM initialization status is completed; The slave core monitors in a loop whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM.

2. The method according to claim 1, characterized in that After the slave core cyclically monitors whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM, the method further includes: When the slave core finds that the preset flag exists in its own predetermined register, it determines that the initialization state of the RAM is completed, and then the slave core jumps the running address from the read-only memory ROM to the RAM.

3. The method according to claim 1, characterized in that Determining that the connection state of the bus meets a preset condition includes: The main core performs software initialization on the bus after the bus is powered on for the first time and the hardware is automatically connected; After the bus software initialization is completed, the main core tests the stability of the bus connection. If the bus connection is detected to be stable, it is determined that the bus connection status meets the preset conditions. If the bus connection is detected to be unstable, the bus stabilization operation continues.

4. The method according to claim 3, characterized in that The main core tests the stability of the bus connection, including: the main core tests the stability of the bus connection through a cyclic redundancy check; and / or the bus stabilization operation includes: using 8b / 10b encoding and / or performing the bus stabilization operation by reducing the bus connection rate.

5. The method according to claim 1, characterized in that The obtaining of the initialization state of the random access memory RAM includes: The main core obtains the RAM initialization state of the specified segment address, and the preset flag is used to indicate that the RAM initialization state of the specified segment address is in a completed state.

6. The method according to claim 1, characterized in that The multi-processor platform includes a master CPU and at least one slave CPU, the master core is located on the master CPU, and when the master CPU also includes at least one slave core, writing a preset flag into a predetermined register of the slave core in the multi-processor platform through a bus includes: The master core writes a preset flag into a predetermined register of a slave core of the master CPU in the multi-processor platform; The master core writes the preset flag into a predetermined register of the slave core of the slave CPU in the multi-processor platform through a bus.

7. The method according to any one of claims 1 to 6, characterized in that: The bus includes a high-speed transmission end-to-end bus technology HT bus and / or a high-speed serial computer expansion bus standard PCIE bus.

8. The method according to any one of claims 1 to 6, characterized in that: The predetermined register is the MAILBOX register.

9. A multi-processor platform, characterized in that: The multi-processor platform includes a master core and at least one slave core, wherein the at least one slave core is on a CPU different from the CPU where the master core is located, wherein: The main core includes a state acquisition unit for acquiring the initialization state of the random access memory RAM and the connection state of the bus during the basic input and output system startup phase; The master core further includes a flag writing unit, configured to write a preset flag into a predetermined register of the slave core via the bus when it is determined that the RAM initialization is completed and the bus connection status satisfies a preset condition, wherein the preset flag is used to indicate that the RAM initialization status is completed; The slave core includes a flag monitoring unit, which is used to cyclically monitor whether the preset flag exists in its own predetermined register to obtain the initialization state of the RAM.

10. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method for inter-processor core communication according to any one of claims 1 to 8 are implemented.

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