Three-Dimensional Modeling Method, System, Medium and Device for Chip Layout Deposition Structure

Abstract

The present invention discloses a three-dimensional modeling method, system, medium and device for a chip layout deposition structure. The method includes: determining a modeling area of the chip layout, and obtaining a first pattern and a second pattern that are partially overlapped within the modeling area on the chip layout, where the first pattern and the second pattern are used to define the shape of the deposition; determining an overlapping area and a non-overlapping area between the second pattern and the first pattern; determining a reference plane in three-dimensional space, and constructing a first block with a first thickness on the reference plane with the first pattern as the bottom surface; constructing a second block with a second thickness on the reference plane with the second pattern as the bottom surface, and placing the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second pattern in the modeling area. The present invention solves the problem that the two-dimensional layout in the prior art cannot meet the three-dimensional scale analysis, and can convert the two-dimensional layout into a three-dimensional model, which is convenient for intuitively performing three-dimensional scale analysis.

Description

Technical Field

[0001] The present invention relates to the field of chip layout design, and in particular to a three-dimensional modeling method, system, medium and device for a chip layout deposition structure. Background Art

[0002] The chip layout is the basis for chip fabrication. For some chips, it is necessary to fabricate a deposition structure such as a thin film on a plane through a deposition process. Correspondingly, in chip layout design, it is necessary to draw a graph representing the deposition range. However, since all the graphs of the chip layout are drawn on a plane, which is a two-dimensional layout, the visualization degree of the two-dimensional layout is low, and it is impossible to visually perform three-dimensional scale analysis to check the accuracy of the layout. One can only rely on subjective judgment to determine the positions of the deposition structures on the chip layout in the horizontal and vertical directions. If the two-dimensional layout can be converted into a three-dimensional model, more subjective three-dimensional scale analysis can be performed. However, currently, the software on the market that supports drawing chip layouts does not support this function. Therefore, it is urgent to implement the function of converting a two-dimensional layout into a three-dimensional model. Summary of the Invention

[0003] The purpose of the present invention is to provide a three-dimensional modeling method, system, medium and device for a chip layout deposition structure, so as to solve the problem that the two-dimensional layout in the prior art cannot meet the three-dimensional scale analysis, and be able to convert the two-dimensional layout into a three-dimensional model, which is convenient for intuitive three-dimensional scale analysis.

[0004] To solve the above technical problems, the present invention provides a three-dimensional modeling method for a chip layout deposition structure, including:

[0005] Determine the modeling area of the chip layout, and obtain a first graph and a second graph that partially overlap within the modeling area on the chip layout, where the first graph and the second graph are used to define the shape of the deposition;

[0006] Determine the overlapping area and non-overlapping area between the second graph and the first graph;

[0007] Determine a reference plane in three-dimensional space, and construct a first block with a first thickness on the reference plane with the first graph as the bottom surface;

[0008] Construct a second block with a second thickness on the reference plane with the second graph as the bottom surface, and place the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second graph in the modeling area.

[0009] Preferably, the step of determining the overlapping area and non-overlapping area between the second graph and the first graph includes:

[0010] Perform a Boolean intersection operation on the first graphic and the second graphic to obtain the overlapping area of the second graphic and the first graphic;

[0011] Perform a Boolean subtraction operation on the first graphic and the second graphic to obtain the non-overlapping area of the second graphic and the first graphic.

[0012] Preferably, the step of constructing a first block with a first thickness on the reference plane with the first graphic as the bottom surface includes:

[0013] Construct a first bottom surface on the reference plane that has the same shape as the first graphic;

[0014] Perform geometric stretching on the first bottom surface in a direction perpendicular to the reference plane according to the first thickness to obtain the first block.

[0015] Preferably, the step of constructing a second block with a second thickness on the reference plane with the second graphic as the bottom surface, and placing the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second graphic in the modeling area includes:

[0016] On the reference plane, construct a first deposition block with a second thickness with the overlapping area as the bottom surface and a second deposition block with the second thickness with the non-overlapping area as the bottom surface;

[0017] Place the first deposition block on the first block and place the second deposition block on the reference plane according to the position of the second graphic in the modeling area.

[0018] Preferably, the method further includes:

[0019] On the reference plane, construct a foundation block with a preset thickness with the modeling area as the bottom surface;

[0020] Place the first block on the foundation block according to the position of the first graphic in the modeling area.

[0021] Preferably, the method further includes:

[0022] When the first thickness is greater than the second thickness, construct a bridging block that contacts both the part of the second block corresponding to the overlapping area and the part of the second block corresponding to the non-overlapping area.

[0023] Preferably, the height of the bridging block does not exceed the first thickness, and the projection on the reference plane does not exceed the range of the non-overlapping area.

[0024] To solve the above technical problems, the present invention further provides a three-dimensional modeling system for a chip layout deposition structure, including:

[0025] A graphic acquisition module, configured to determine a modeling area of the chip layout and acquire a first graphic and a second graphic that are partially overlapped within the modeling area on the chip layout, where the first graphic and the second graphic are used to define a deposited shape;

[0026] A graphic determination module, configured to determine an overlapping area and a non-overlapping area between the second graphic and the first graphic;

[0027] A first construction module, configured to determine a reference plane in three-dimensional space and construct a first block with a first thickness on the reference plane with the first graphic as the bottom surface;

[0028] A second construction module, configured to construct a second block with a second thickness on the reference plane with the second graphic as the bottom surface, and place the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second graphic in the modeling area.

[0029] To solve the above technical problems, the present invention further provides a storage medium, in which a computer program is stored, and the computer program is configured to execute the three-dimensional modeling method of the chip layout deposition structure described in any one of the foregoing when running.

[0030] To solve the above technical problems, the present invention further provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the three-dimensional modeling method of the chip layout deposition structure described in any one of the foregoing.

[0031] Different from the prior art, the three-dimensional modeling method of the chip layout deposition structure provided by the present invention acquires a first graphic and a second graphic that are at least partially overlapped within the modeling area on the chip layout, then determines the overlapping area and the non-overlapping area between the second graphic and the first graphic, and finally constructs a first block with the first graphic as the bottom surface on the reference plane in three-dimensional space first, and then constructs a second block with the second graphic as the bottom surface, and places the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second graphic in the modeling area, so as to be able to convert a two-dimensional layout into a three-dimensional model and facilitate intuitive three-dimensional scale analysis.

[0032] The three-dimensional modeling system, storage medium and electronic device of the chip layout deposition structure provided by the present invention belong to the same inventive concept as the three-dimensional modeling method of the chip layout deposition structure, and therefore have the same beneficial effects, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic flow chart of a three-dimensional modeling method for a chip layout deposition structure provided by an embodiment of the present invention.

[0034] Figure 2 It is a schematic diagram of the positional relationship between the modeling area on the chip layout and the first pattern and the second pattern.

[0035] Figure 3 It is a schematic diagram of the first tile constructed on the reference plane.

[0036] Figure 4 It is a schematic diagram of the positional relationship between the first tile and the second tile.

[0037] Figure 5 It is a schematic diagram of the positional relationship between the foundation tile constructed on the reference plane and the first tile.

[0038] Figure 6 For Figure 1 It is a specific schematic flow chart of step S2 in the three-dimensional modeling method shown.

[0039] Figure 7 For Figure 1 It is a specific schematic flow chart of step S3 in the three-dimensional modeling method shown.

[0040] Figure 8 It is a schematic diagram of the first bottom surface constructed on the reference plane.

[0041] Figure 9 For Figure 1 It is a specific schematic flow chart of step S4 in the three-dimensional modeling method shown.

[0042] Figure 10 It is a schematic diagram of the positional relationship between the first deposition tile, the second deposition tile and the first tile in three-dimensional space.

[0043] Figure 11 It is a schematic diagram of the positional relationship between the bridging tile and the first deposition tile and the second deposition tile in three-dimensional space.

[0044] Figure 12 It is a principle block diagram of a three-dimensional modeling system for a chip layout deposition structure provided by another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The following will describe the specific embodiments of the present invention in more detail with reference to the schematic diagrams. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0046] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0047] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0048] Please refer to Figure 1 , the embodiment of the present invention provides a three-dimensional modeling method for a chip layout deposition structure. The method includes the following steps:

[0049] S1: Determine the modeling area of the chip layout, and obtain a first pattern and a second pattern that partially overlap within the modeling area on the chip layout. The first pattern and the second pattern are used to define the shape of the deposition.

[0050] Among them, the modeling area is the area representing the modeling scope. The modeling area can be the entire chip layout or a certain part of the chip layout. Considering that the chip layout is usually drawn on a rectangular interface, the shape of the modeling area is preferably rectangular.

[0051] The modeling area can be determined according to the user's operation. For example, the user inputs the coordinates of four vertices, and the four vertices are sequentially connected according to the coordinates of the four vertices to form a rectangular frame. The area enclosed by the rectangular frame is the modeling area. Or the user manually selects two vertices on the chip layout and forms a rectangular frame with the two vertices as diagonal vertices. The area enclosed by the rectangular frame is the modeling area. Or the user performs a box selection operation on the chip layout and forms a rectangular frame according to the box selection operation. The area enclosed by the rectangular frame is the modeling area.

[0052] Regardless of how the modeling area is determined, it is necessary to ensure that the first pattern and the second pattern are within the modeling area. Both the first pattern and the second pattern represent the shape of the deposition, indicating that a deposition structure such as a thin film needs to be formed on the chip through a deposition process. And the deposition process sequence of the first pattern is before the deposition process sequence of the second pattern.

[0053] Such as Figure 2As shown in the figure, the rectangular box BOX in the figure represents the modeling area, the graphic A represents the first graphic, the graphic B represents the second graphic, the first graphic A and the second graphic B partially overlap, and both are located within the modeling area BOX.

[0054] S2: Determine the overlapping area and non-overlapping area between the second graphic and the first graphic.

[0055] Among them, since the second graphic and the first graphic partially overlap, there are overlapping parts and non-overlapping parts between the two. The part of the second graphic that overlaps with the first graphic is the overlapping area, and the part of the second graphic that does not overlap with the first graphic is the non-overlapping area. As Figure 2 shown, the graphic B1 represents the overlapping area, and the graphic B2 represents the non-overlapping area.

[0056] S3: Determine a reference plane in three-dimensional space, and construct a first block with a first thickness on the reference plane with the first graphic as the bottom surface.

[0057] Among them, the three-dimensional space is a 3D display interface, and the reference plane is a plane in the three-dimensional space. This plane can be the plane where the XY coordinate axes are located in the three-dimensional coordinate system XYZ, or the plane where the XZ coordinate axes are located, or the plane where the YZ coordinate axes are located, or it can be a custom plane. After creating or invoking the three-dimensional space, it is necessary to determine a reference plane. The first block constructed on the reference plane is a structure with parallel upper and lower surfaces and a height of the first thickness. The first thickness is the modeling thickness set by the user or the default. As Figure 3 shown, the three-dimensional structure D1 in the figure represents the first block. The first block D1 is constructed on the XY plane. The top view shape of the first block D1 is the same as that of the first graphic. The height of the first block D1 is the first thickness h1. The first block D1 visually shows the three-dimensional structure after the deposition process.

[0058] S4: Construct a second block with a second thickness on the reference plane with the second graphic as the bottom surface, and place the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second graphic in the modeling area.

[0059] Among them, the second block constructed on the reference plane is a structure with parallel upper and lower surfaces and a height of the second thickness. The second thickness is the modeling thickness set by the user or the default. Since the second graphic and the first graphic partially overlap, the part of the second block corresponding to the overlapping area is located on the first block, indicating deposition on the first block. However, the part of the second block corresponding to the non-overlapping area is not directly above the first block, and corresponding to the physical structure of the actual chip, the part of the second block corresponding to the non-overlapping area cannot be suspended, so the part of the second block corresponding to the non-overlapping area is placed on the reference plane. As Figure 4As shown, the three-dimensional structure D2 in the figure represents the second tile. The top-down shape of the second tile D2 is the same as the second figure. The height of the second tile D2 is the second thickness h2. The second tile D2 visually shows the three-dimensional structure after the deposition process. The second tile D2 is divided into two parts, corresponding to the overlapping area and the non-overlapping area respectively. The part corresponding to the non-overlapping area and the first tile D1 are both located on the reference plane, and the part corresponding to the overlapping area is located on the first tile D1. Moreover, the combined top-down shape of the two parts is the same as the second figure.

[0060] Through the above method, the three-dimensional modeling method of the chip layout deposition structure in the embodiment of the present invention converts the graph representing the deposition shape from a two-dimensional planar graph into a three-dimensional solid graph. The three-dimensional structure of the two depositions before and after can be visually shown through the three-dimensional solid graph. Therefore, the present invention can convert the two-dimensional layout into a three-dimensional model, which is convenient for intuitive three-dimensional scale analysis.

[0061] In some embodiments of the present application, please refer to Figure 1 again, the three-dimensional modeling method of the chip layout deposition structure further includes:

[0062] S5: Construct a foundation tile with a preset thickness on the reference plane with the modeling area as the bottom surface;

[0063] S6: Place the first tile on the foundation tile according to the position of the first figure in the modeling area.

[0064] Since the chip layout usually does not draw the chip substrate, and all the structures of the actual chip are formed on the substrate. In order to more realistically display the deposition structure, this embodiment constructs a foundation tile to represent the substrate. The foundation tile is a structure with parallel upper and lower surfaces and a height of the preset thickness. The shapes of the upper and lower surfaces are both the same as the modeling area. As Figure 5 shown, the three-dimensional structure F in the figure represents the foundation tile. The thickness of the foundation tile F is h. The first tile D1 is placed on the foundation tile F. The position of the first tile D1 on the foundation tile F is determined according to the position of the first figure in the modeling area, and then the two are attached to each other up and down.

[0065] In some embodiments of the present application, please refer to Figure 6 again, the steps of determining the overlapping area and the non-overlapping area between the second figure and the first figure, that is, step S2 includes:

[0066] S21: Perform a Boolean intersection operation on the first figure and the second figure to obtain the overlapping area between the second figure and the first figure.

[0067] S22: Perform a Boolean subtraction operation on the first figure and the second figure to obtain the non-overlapping area between the second figure and the first figure.

[0068] Among them, Boolean operations are a type of logical operation in the field of computers, including logical AND, OR, and NOT operations on Boolean types. In computer geometry, it represents set operations such as union, intersection, and difference between polygons or polyhedra. The Boolean intersection operation is to calculate the intersection of two graphics, which is a Boolean AND operation. The Boolean subtraction operation is to calculate the difference set of two graphics, which is a Boolean NOT operation.

[0069] In some embodiments of the present application, please refer to Figure 7 , the step of constructing a first block with a first thickness on a reference plane with the first graphic as the bottom surface, that is, step S3 includes:

[0070] S31: Construct a first bottom surface on the reference plane that has the same shape as the first graphic.

[0071] Among them, the first bottom surface has the same shape as the first graphic, and the first bottom surface is also a two-dimensional planar graphic. The difference is that the first bottom surface is constructed in a three-dimensional space. As Figure 8 shown, the first bottom surface U1 is constructed on the XY plane of the three-dimensional space coordinate system XYZ.

[0072] S32: Geometrically stretch the first bottom surface in the direction perpendicular to the reference plane according to the first thickness to obtain the first block.

[0073] Among them, the first bottom surface is composed of many points. Geometrically stretching each point is to transform the point into a line, and the length of the line is the first thickness. The lines transformed from each point form the first block. As Figure 3 shown, after geometrically stretching the first bottom surface U1, the first block D1 is obtained. The shapes of the upper and lower surfaces of the first block D1 are both the same as the characteristic bottom surface U1, and the height of the first block D1 is the first thickness h1. Similar to the first block, the second block and / or the foundation block can also be obtained by the same construction process.

[0074] In some embodiments of the present application, please refer to Figure 9 , the step of constructing a second block with a second thickness on the reference plane with the second graphic as the bottom surface, and placing the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second graphic in the modeling area, that is, step S4 includes:

[0075] S41: Construct a first deposited block with a second thickness on the reference plane with the overlapping area as the bottom surface and a second deposited block with a second thickness on the reference plane with the non-overlapping area as the bottom surface.

[0076] Among them, the first deposition block is a structure with parallel upper and lower surfaces and a height of the second thickness, and the second deposition block is also a structure with parallel upper and lower surfaces and a height of the second thickness. The shapes of the upper and lower surfaces of the first deposition block are the same as the overlapping area, and the shapes of the upper and lower surfaces of the second deposition block are the same as the non-overlapping area.

[0077] S42: Place the first deposition block on the first block according to the position of the second figure in the modeling area, and place the second deposition block on the reference plane.

[0078] Among them, the overlapping area of the second figure is located within the first figure, and the first figure is the area deposited first. Therefore, the first deposition block is just located on the first block, corresponding to the physical structure of the actual chip. The second deposition block cannot be suspended, so the second deposition block is placed on the reference plane. As Figure 10 shown, the three-dimensional structure C1 in the figure represents the first deposition block, and the three-dimensional structure C2 represents the second deposition block. Both the first deposition block C1 and the second deposition block C2 are structures with parallel upper and lower surfaces and a height of the second thickness h2. The first deposition block C1 is located on the first block D1, and the second deposition block C2 is placed on the reference plane.

[0079] In some embodiments of the present application, the three-dimensional modeling method of this embodiment further includes:

[0080] When the first thickness is greater than the second thickness, construct a bridging block that is in contact with both the part corresponding to the overlapping area of the second block and the part corresponding to the non-overlapping area of the second block.

[0081] Among them, if the first thickness is greater than the second thickness, there will be a disconnection between the part corresponding to the overlapping area of the second block (corresponding to the first deposition block in this embodiment) and the part corresponding to the non-overlapping area of the second block (corresponding to the second deposition block in this embodiment). In fact, when depositing a thin film by a deposition process, the two parts of the second block are continuous. In order to more realistically display the three-dimensional structure of the chip layout, this embodiment constructs a bridging block to represent the physical connection of the two parts. As Figure 10 shown, the three-dimensional structure C3 represents the bridging block. When the first thickness h1 is greater than the second thickness h2, there is a disconnection between the first deposition block C1 and the second deposition block C2, and the physical connection between the two can be achieved through the bridging block C3.

[0082] The bridging block is only used to represent the physical connection between the first deposition block and the second deposition block, and its physical structure may not be consistent with that of the actual chip. In order to prevent the bridging block from affecting the three-dimensional view of the chip layout, in this embodiment, the height of the bridging block does not exceed the first thickness, and its projection on the reference plane does not exceed the range of the non-overlapping area. As Figure 11As shown, the height of the bridging block C3 is less than the first thickness h1, and any cross-section of the bridging block C3 does not exceed the range of the non-overlapping area B2.

[0083] Please refer to Figure 12 , Another embodiment of the present invention provides a three-dimensional modeling system for a chip layout deposition structure. The system includes:

[0084] The graphics acquisition module 1 is used to determine the modeling area of the chip layout and acquire the first graphics and the second graphics that are partially overlapped within the modeling area on the chip layout. The first graphics and the second graphics are used to define the shape of the deposition. Among them, the modeling area is the area representing the modeling range. The modeling area can be the entire chip layout or a certain part of the chip layout. Considering that the chip layout is usually drawn on a rectangular interface, the shape of the modeling area is preferably rectangular.

[0085] The modeling area can be determined according to the user's operation. For example, the user inputs the coordinates of four vertices, and the four vertices are sequentially connected according to the coordinates of the four vertices to form a rectangular frame. The area enclosed by the rectangular frame is the modeling area. Or the user manually selects two vertices on the chip layout and forms a rectangular frame with the two vertices as the diagonal vertices. The area enclosed by the rectangular frame is the modeling area. Or the user performs a selection operation on the chip layout and forms a rectangular frame according to the selection operation. The area enclosed by the rectangular frame is the modeling area.

[0086] Regardless of how the modeling area is determined, it is necessary to ensure that the first graphics and the second graphics are within the modeling area. Both the first graphics and the second graphics represent the shape of the deposition, indicating that a deposition structure such as a thin film needs to be formed on the chip through a deposition process. And the deposition process sequence of the first graphics is before the deposition process sequence of the second graphics.

[0087] The graphics determination module 2 is used to determine the overlapping area and the non-overlapping area between the second graphics and the first graphics. Among them, the second graphics and the first graphics are partially overlapped, so there are overlapping parts and non-overlapping parts between the two. The part of the second graphics that overlaps with the first graphics is the overlapping area, and the part of the second graphics that does not overlap with the first graphics is the non-overlapping area.

[0088] The first construction module 3 is used to determine a reference plane in a three-dimensional space, and construct a first block with a first thickness on the reference plane with the first figure as the bottom surface. Herein, the three-dimensional space is a 3D display interface, and the reference plane is a plane in the three-dimensional space, which can be the plane where the XY coordinate axes are located in the three-dimensional coordinate system XYZ, can also be the plane where the XZ coordinate axes are located, can also be the plane where the YZ coordinate axes are located, or can be a custom plane. After creating or calling the three-dimensional space, it is necessary to determine a reference plane, and the first block constructed on the reference plane is a structure with parallel upper and lower surfaces and a height of the first thickness. The first thickness is the modeling thickness set by the user or by default.

[0089] The second construction module 4 is used to construct a second block with a second thickness on the reference plane with the second figure as the bottom surface, and place the part of the corresponding overlapping area of the second block on the first block and the part of the corresponding non-overlapping area on the reference plane according to the position of the second figure in the modeling area. Herein, the second block constructed on the reference plane is a structure with parallel upper and lower surfaces and a height of the second thickness. The second thickness is the modeling thickness set by the user or by default. Since the second figure partially overlaps with the first figure, the part of the second block corresponding to the overlapping area is located on the first block, indicating deposition on the first block. However, the part of the second block corresponding to the non-overlapping area is not directly above the first block, and corresponding to the physical structure of the actual chip, the part of the second block corresponding to the non-overlapping area cannot be suspended, so the part of the second block corresponding to the non-overlapping area is placed on the reference plane.

[0090] The three-dimensional modeling system of this embodiment may further include other technical features of the three-dimensional modeling method of the foregoing chip layout deposition structure, implement all method steps of the three-dimensional modeling method of the foregoing embodiment, and have the same technical effects as the three-dimensional modeling method of the foregoing embodiment, which will not be elaborated here.

[0091] The present invention also provides a storage medium, in which a computer program is stored, and the computer program is set to execute the three-dimensional modeling method of the chip layout deposition structure of any foregoing embodiment when running.

[0092] Specifically, in this embodiment, the foregoing storage medium may include but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0093] The present invention also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is set to run the computer program to execute the three-dimensional modeling method of the chip layout deposition structure of any embodiment.

[0094] Specifically, the memory and the processor can be connected via a data bus. In addition, the above-mentioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the above-mentioned processor, and the input / output device is connected to the above-mentioned processor.

[0095] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example" or "specific example" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0096] The above are only the preferred embodiments of the present invention and do not impose any limiting effect on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed in the present invention, which are still within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A three-dimensional modeling method for a chip layout deposition structure, characterized in that Including: Determine the modeling area of the chip layout, and obtain a first pattern and a second pattern that are partially overlapped within the modeling area on the chip layout, where the first pattern and the second pattern are used to define the shape of the deposition; Determine the overlapping area and non-overlapping area between the second pattern and the first pattern; Determine a reference plane in three-dimensional space, and construct a first block with a first thickness on the reference plane with the first pattern as the bottom surface; Construct a second block with a second thickness on the reference plane with the second pattern as the bottom surface, and place the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second pattern within the modeling area.

2. The method according to claim 1, wherein The step of determining the overlapping area and non-overlapping area between the second pattern and the first pattern includes: Perform a Boolean intersection operation on the first pattern and the second pattern to obtain the overlapping area between the second pattern and the first pattern; Perform a Boolean subtraction operation on the first pattern and the second pattern to obtain the non-overlapping area between the second pattern and the first pattern.

3. The method according to claim 1, wherein The step of constructing a first block with a first thickness on the reference plane with the first pattern as the bottom surface includes: Construct a first bottom surface on the reference plane with the same shape as the first pattern; Geometrically stretch the first bottom surface in a direction perpendicular to the reference plane according to the first thickness to obtain the first block.

4. The method according to claim 1, wherein The step of constructing a second block with a second thickness on the reference plane with the second pattern as the bottom surface, and placing the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second pattern within the modeling area includes: Construct a first deposition block with a second thickness on the reference plane with the overlapping area as the bottom surface, and construct a second deposition block with the second thickness on the reference plane with the non-overlapping area as the bottom surface; Place the first deposition block on the first block and place the second deposition block on the reference plane according to the position of the second pattern within the modeling area.

5. The method according to claim 1, wherein The method further includes: Construct a foundation block with a preset thickness on the reference plane with the modeling area as the bottom surface; Place the first block on the foundation block according to the position of the first pattern within the modeling area.

6. The method according to claim 1 or 4, characterized in that, The method further includes: When the first thickness is greater than the second thickness, construct a bridging block that is in contact with both the part of the second block corresponding to the overlapping area and the part of the second block corresponding to the non-overlapping area.

7. The method according to claim 6, characterized in that, The height of the bridging block does not exceed the first thickness, and the projection on the reference plane does not exceed the range of the non-overlapping area.

8. A three-dimensional modeling system for a chip layout deposition structure, characterized in that, Including: A pattern acquisition module, configured to determine the modeling area of the chip layout, and obtain a first pattern and a second pattern that are partially overlapped within the modeling area on the chip layout, where the first pattern and the second pattern are used to define the shape of the deposition; A pattern determination module, configured to determine the overlapping area and non-overlapping area between the second pattern and the first pattern; The first construction module is used to determine a reference plane in a three-dimensional space, and construct a first block with a first thickness on the reference plane with the first figure as the bottom surface; The second construction module is used to construct a second block with a second thickness on the reference plane with the second figure as the bottom surface, and place the part of the second block corresponding to the overlapping area on the first block and the part corresponding to the non-overlapping area on the reference plane according to the position of the second figure in the modeling area.

9. A storage medium, characterized in that, A computer program is stored in the storage medium, and the computer program is set to execute the three-dimensional modeling method of the chip layout deposition structure according to any one of claims 1 to 7 when running.

10. An electronic device, characterized in that, It includes a memory and a processor. A computer program is stored in the memory, and the processor is set to run the computer program to execute the three-dimensional modeling method of the chip layout deposition structure according to any one of claims 1 to 7.

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