Gate driver and electroluminescent display device comprising the same

Abstract

A gate driver and an electroluminescent display apparatus including the same are disclosed. Each gate stage of the gate driver can be implemented to operate based on a clock, a set signal, and a reset signal without a driving power source, and thus can not be connected to the driving power source. Accordingly, since a driving power source line is omitted, a mounting area of the gate driver can be reduced, and thus a narrow bezel can be easily implemented. Each gate stage can be implemented based on a clock without a driving power source, and thus a configuration thereof can be simplified. In this case, since each gate stage includes a leakage current blocker, operation stability thereof can be ensured even when the gate stage is manufactured based on an oxide transistor having a depletion characteristic.

Description

Technical Field

[0001] This disclosure relates to a gate driver and an electroluminescent display device including the gate driver. Background Technology

[0002] An electroluminescent display device includes multiple pixels arranged in a matrix and provides image data synchronized with a scan signal to the pixels, thereby adjusting the brightness of the pixels. The electroluminescent display device generates the scan signal using a gate driver comprising multiple gate stages. Each gate stage of the gate driver is connected to a gate line of the display panel. Each gate stage includes multiple transistors and outputs a scan signal, which oscillates between a scan on-state voltage and a scan off-state voltage, to the gate line of the display panel.

[0003] Because the number of gate lines in a display of a given size increases with increasing resolution, the number of gate levels increases in high-resolution display devices. As the number of gate levels increases, the area of ​​the bezel region including the gate levels may inevitably increase, thus limiting the reduction of bezel size in electroluminescent display devices. Summary of the Invention

[0004] In order to overcome the above-mentioned problems of the prior art, this disclosure can provide a gate driver that simplifies the configuration of the gate level and thus enables a narrow bezel and an electroluminescent display device including the gate driver.

[0005] Furthermore, this disclosure may provide a gate driver and an electroluminescent display device including the gate driver, wherein the gate stages are configured to operate based on a clock without a driving power supply and each gate stage includes a leakage current blocker, thereby increasing operational stability.

[0006] To achieve these objectives and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, the gate driver comprises multiple stages. Each of the plurality of stages includes: a first series-connected transistor, which is turned on in a first time period based on a first clock with an on level to apply a set signal with an on level to a first control node; a pull-up transistor, which is turned on in a second time period after the first time period based on a voltage of the first control node boots from the on level to apply a second clock to an output node, the second clock being later than the first clock in the on level phase; a second series-connected transistor, which is turned on in a fourth time period later than the second time period based on a reset signal with an on level and a voltage of the second control node to apply a second clock with a cut-off level to the first control node; and a leakage current blocker, which blocks leakage current of the first series-connected transistor and the second series-connected transistor based on the second clock with an on level and the third clock with an on level in the second time period and in a third time period in which the first control node is floating, wherein the third time period is arranged between the second time period and the fourth time period. Attached Figure Description

[0007] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0008] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0009] Figure 2 This is a schematic illustration of the setting. Figure 1 A diagram of the equivalent circuit of pixels in the display panel;

[0010] Figure 3 It is shown Figure 1 A diagram of a first embodiment of the gate driver;

[0011] Figure 4 This is a diagram illustrating an example of a gate driver outputting a scan signal based on a clock according to a first embodiment;

[0012] Figure 5 This is a diagram illustrating the circuit configuration of the gate stage included in the gate driver according to the first embodiment;

[0013] Figure 6 It is shown Figure 5 A diagram of the gate-level operation waveform;

[0014] Figure 7A It is shown Figure 6 A diagram of the gate stage operating states during the first time period;

[0015] Figure 7B It is shown Figure 6 A diagram of the gate stage operation states during the second time period;

[0016] Figure 7C It is shown Figure 6 A diagram of the gate-level operating states during the third time period;

[0017] Figure 7D It is shown Figure 6 A diagram of the gate-level operating states during the fourth time period;

[0018] Figure 8 This is a diagram illustrating another circuit configuration including the gate stage in the gate driver according to the first embodiment;

[0019] Figure 9 It is shown Figure 8 A diagram of the gate-level operation waveform;

[0020] Figure 10 It is shown Figure 1 A diagram of a second embodiment of the gate driver;

[0021] Figure 11 This is a diagram illustrating the circuit configuration of the gate stage included in the gate driver according to the second embodiment;

[0022] Figure 12 It is shown Figure 11 A diagram of the gate-level operation waveform;

[0023] Figure 13A It is shown Figure 12 A diagram of the gate stage operating states during the first time period;

[0024] Figure 13B It is shown Figure 12 A diagram of the gate stage operation states during the second time period;

[0025] Figure 13C It is shown Figure 12 A diagram of the gate-level operating states during the third time period;

[0026] Figure 13D It is shown Figure 12 A diagram of the gate-level operating states during the fourth time period;

[0027] Figure 14 This is a diagram illustrating another circuit configuration including the gate stage in the gate driver according to the second embodiment; and

[0028] Figure 15 It is shown Figure 14 The diagram shows the operating waveform of the gate stage. Detailed Implementation

[0029] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concepts of the present disclosure to those skilled in the art.

[0030] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0031] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. The same reference numerals consistently denote the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, unless the term "only" is used, the terms "comprising," "having," "including," etc., implicitly suggest the addition of other components. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0032] Even without explicit statement, elements in the various embodiments of this disclosure will be interpreted as including tolerances.

[0033] When describing positional relationships, for example, when the positional relationship between two components is described as “~above,” “~above,” “~below,” and “adjacent to~,” one or more other components may be positioned between the two components unless “only” or “direct” is used.

[0034] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0035] In this disclosure, the pixel circuitry and gate driver disposed on the substrate of the display panel can be implemented using, but are not limited to, transistors of the type of N-metal-oxide-semiconductor field-effect transistor (MOSFET). The transistor can be a three-electrode element comprising a gate, a source, and a drain. The source can be the electrode that provides charge carriers to the transistor. In the transistor, charge carriers can begin to flow out from the source. The drain can be the electrode that allows charge carriers to flow out of the transistor. That is, in a MOSFET, charge carriers flow from the source to the drain. In an N-MOS, because the charge carriers are holes, the drain voltage can be higher than the source voltage, causing holes to flow from the source to the drain. In an N-MOS, because holes flow from the drain to the source, current can flow from the drain to the source. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be switched between them. Therefore, in the embodiments described in this disclosure, one of the source and drain can be described as a first electrode, and the other of the source and drain can be described as a second electrode.

[0036] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this description, within the context of electroluminescent display devices, organic light-emitting display devices comprising organic light-emitting materials will be primarily described. However, it should be noted that the concept of the present invention is not limited to organic light-emitting display devices, but can be applied to inorganic light-emitting display devices comprising inorganic light-emitting materials.

[0037] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 This is a schematic illustration of the setting. Figure 1 A diagram of the equivalent circuit of pixels in a display panel.

[0038] Reference Figure 1 The display device according to this disclosure may include a display panel 100, a timing controller 110, a data driver 120, a gate driver 130, and a level shifter 150.

[0039] In the display panel 100, such as Figure 2 As shown, pixels PXL connected to data line 14 and gating line 15 can be arranged in a matrix to form a pixel array. Multiple horizontal pixel lines can be included in the pixel array, and multiple pixels PXL that are horizontally adjacent to each other and jointly connected to gating line 15 can be arranged in multiple pixels PXL. Here, a horizontal pixel line can represent a group of pixels forming a horizontal line, rather than a physical signal line. The pixel array can include power lines that transmit a high-level source voltage EVDD to the pixels PXL. Furthermore, pixels PXL can also be connected to a low-level source voltage EVSS.

[0040] like Figure 2 As shown, each pixel PXL may include an OLED light-emitting device and a pixel driving circuit PCC for driving the OLED. The pixel driving circuit PCC may include a driving element for generating a driving current to be applied to the OLED and a switching circuit connected to the driving element. The switching circuit can set and maintain the gate-source voltage of the driving element. For this purpose, a data voltage Vdata can be provided to the switching circuit via data line 14, a scan signal SCAN can be provided to the switching circuit via gating line 15, and a high-level source voltage EVDD can be provided to the switching circuit via a power line, thereby setting the gate-source voltage of the driving element. The gate electrode of the switching element included in the switching circuit can be connected to gating line 15, and the first electrode (or second electrode) of the switching element included in the switching circuit can be connected to the data line.

[0041] Each pixel PXL can be one of a red pixel, a green pixel, a blue pixel, and a white pixel. Red, green, blue, and white pixels can constitute a unit pixel and can achieve various colors. The color achieved in a unit pixel can be determined by the emissivity of each of the red, green, blue, and white pixels. Furthermore, white pixels can be omitted, and in this case, the unit pixel can be configured with red, green, and blue pixels. Additionally, the number of gate lines 15 connected to pixel PXL can be singular or plural.

[0042] Reference Figure 1 The data driver 120 can receive image data DATA and a source timing control signal DDC from the timing controller 110. In response to the source timing control signal DDC from the timing controller 110, the data driver 120 can convert the image data DATA into a gamma-compensated voltage to generate a data voltage Vdata, and can provide the data voltage Vdata to the data line 14 of the display panel 100 based on the timing provided by the scan signal SCAN. The data driver 120 can be connected to the data line 14 of the display panel 100 via a chip-on-glass (COG) process or a tape-on-bond (TAB) process. The data driver 120 can be divided into multiple data drivers and configured, but is not limited to this, and can be configured as a single driver.

[0043] Reference Figure 1The level shifter 150 can generate a gate timing control signal GDC for driving the switching elements of a pixel based on an on / off control clock with transistor-transistor-logic (TTL) levels input from the timing controller 110. The gate timing control signal GDC may include a start signal and a clock signal that swing between an on level (e.g., a first logic level for turning on a transistor) and an off level (e.g., a second logic level for turning off a transistor). The level shifter 150 can provide the gate timing control signal GDC to the gate driver 130.

[0044] Reference Figure 1 and Figure 2 The gate driver 130 can operate based on the gate timing control signal GDC input from the level shifter 150 to generate the scan signal SCAN required to drive the pixel PXL. Furthermore, the gate driver 130 can provide the scan signal SCAN to the gating line 15.

[0045] The gate driver 130 can be directly mounted on the lower substrate of the display panel 100 using an in-panel gate driver (GIP) type. The gate driver 130 can be positioned in a non-display area outside the screen (i.e., the bezel area BZ) of the display panel 100. In the GIP type, the level shifter 150 can be mounted on the printed circuit board (PCB) 140 together with the timing controller 110.

[0046] In gate driver 130, multiple gate stages can be connected to each other in a cascading scheme to configure a gate shift register. The first gate stage among the multiple gate stages can begin operation based on a start signal. Furthermore, each of the other gate stages, excluding the first gate stage, can begin operation based on the output (i.e., carry signal) of the previous gate stage that operated before it.

[0047] Each gate stage can be implemented to operate based on clock, set, and reset signals without a drive power supply, and therefore does not need to be connected to a drive power supply. Thus, by omitting the drive power supply lines, the mounting area of ​​the gate driver 130 can be reduced, making it easier to achieve a narrow bezel.

[0048] Each gate stage can be implemented based on a clock without a drive power supply, thus simplifying its configuration. In this case, because each gate stage includes a leakage current blocker, operational stability can be ensured even when the gate stages are fabricated based on oxide transistors with depletion characteristics. The depletion characteristic of an oxide transistor can be described as the phenomenon where the threshold voltage of the oxide transistor gradually decreases from its initial value due to external light. When the threshold voltage of the oxide transistor is lower than the gate-source voltage of 0V used for cutoff, the oxide transistor may not be sufficiently cut off, and leakage current may occur in the oxide transistor. When the multiple transistors connected to the first control node (hereinafter referred to as node Q) are in the cutoff state, the leakage current blocker included in each gate stage can apply a clock with a sufficiently high on-state to the source of each of the multiple transistors, and therefore, the gate-source voltage of each of the multiple transistors can be sufficiently lower than its threshold voltage. Therefore, when node Q is floating in the on-state, the leakage current blocker can prevent leakage current from flowing through the multiple transistors. The on-state voltage charged to node Q can be stably maintained by the leakage current blocker, thereby preventing distortion of the scan signal caused by voltage changes at node Q.

[0049] The gate driver 130 can be located in two bezel areas BZ in the display panel 100 and can provide the scan signal to each gate line based on a double feeding scheme, thereby minimizing signal distortion caused by load deviation of each gate line.

[0050] Reference Figure 1 The timing controller 110 can be connected to an external host system via various interface types known to those skilled in the art. The timing controller 110 can receive video data DATA from the host system, correct the video data DATA to compensate for brightness deviations caused by differences in electrical characteristics, and transmit the corrected video data to the data driver 120.

[0051] The timing controller 110 can receive timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK from the host system, and can generate a control clock based on the timing signals based on the source timing control signal DDC and the gate timing control signal GDC.

[0052] Figure 3 It is shown Figure 1 A diagram of a first embodiment of the gate driver. Figure 4 This is a diagram illustrating an example of a gate driver outputting a clock-based scan signal according to a first embodiment.

[0053] Reference Figure 3According to a first embodiment of the present disclosure, the gate driver 130 may include a plurality of gate stages SG1 to SG5 respectively connected to the gate line.

[0054] Each of gate stages SG1 to SG5 may include: a first terminal to which a set signal SET is input, a second terminal to which a start signal VST is input, and a third terminal to which a start signal VST is input. Furthermore, each of gate stages SG1 to SG5 may include a first terminal to which a first clock CLK1 is input, a second terminal to which a second clock CLK2 is input, a third terminal to which a third clock CLK3 is input, and a fourth terminal to which a fourth clock CLK4 is input. Each of gate stages SG1 to SG5 may not require a power supply input terminal, thus simplifying its configuration.

[0055] Gate stages SG1 to SG5 can be connected to each other in a cascaded manner and can transmit and receive carry signals CRY between them. Gate stages SG1 to SG5 can be connected to the start line through which the start signal VST is provided and the clock lines L1 to L4 through which the first phase clock CLK-P1 to the fourth phase clock CLK-P4 are provided.

[0056] The first gate stage SG1 of gate stages SG1 through SG5 can begin operation based on a start signal VST input to its first terminal. The set signal SET of the first gate stage SG1 can be the start signal VST. Each of the other gate stages SG2 through SG5, besides the first gate stage SG1, can begin operation based on a carry signal CRY (referred to as the previous carry signal CRY for descriptive purposes) input from the previous stage to its first terminal (e.g., node Q can be activated at the on level). The set signal SET of each of the other gate stages SG2 through SG5 can be the previous carry signal CRY from the previous stage. The operation of each of the gate stages SG1 through SG5 can be reset based on a carry signal CRY (referred to as the next carry signal CRY for descriptive purposes) input from the next stage to its third terminal (e.g., node Q can be disabled at the off level). The reset signal RESET of each of the other gate stages SG1 through SG5 can be the next carry signal CRY from the previous stage. Here, for the nth gate level, the previous carry signal CRY can be the scan signal SCAN(n-1) of the (n-1)th gate level, and the next carry signal CRY can be the scan signal SCAN(n+1) of the (n+1)th gate level.

[0057] Each of the gate stages SG1 to SG5 can be connected to the strobe line, the first terminal of the next gate stage, and the third terminal of the previous gate stage via the output node NO.

[0058] The first phase clock CLK-P1 can be provided to the first clock line L1. The second phase clock CLK-P2, whose phase is later than the first phase clock CLK-P1, can be provided to the second clock line L2. The third phase clock CLK-P3, whose phase is later than the second phase clock CLK-P2, can be provided to the third clock line L3. The fourth phase clock CLK-P4, whose phase is later than the third phase clock CLK-P3, can be provided to the fourth clock line L4. The conduction phases of the first phase clock CLK-P1 to the fourth phase clock CLK-P4 do not need to overlap.

[0059] The 4K-3 gate stage (where K is a natural number) can receive the first phase clock CLK-P1, the second phase clock CLK-P2, the third phase clock CLK-P3, and the fourth phase clock CLK-P4 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively.

[0060] The 4K-2 gate stage can receive the second phase clock CLK-P2, the third phase clock CLK-P3, the fourth phase clock CLK-P4 and the first phase clock CLK-P1 as the first clock CLK1, the second clock CLK2, the third clock CLK3 and the fourth clock CLK4 respectively.

[0061] The 4K-1 gate stage can receive the third phase clock CLK-P3, the fourth phase clock CLK-P4, the first phase clock CLK-P1, and the second phase clock CLK-P2 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively.

[0062] In addition, the 4K gate stage can receive the fourth phase clock CLK-P4, the first phase clock CLK-P1, the second phase clock CLK-P2, and the third phase clock CLK-P3 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively.

[0063] Gate stages SG1 to SG4 can be configured to output based on the above connections, as shown below. Figure 4 The scan signals SCAN1 to SCAN4 are shown with phase shifts. Figure 4 In this process, the start signal VST, the first phase clock CLK-P1 to the fourth phase clock CLK-P4, and the scan signals SCAN1 to SCAN4 can oscillate between on and off levels. Figure 4 (as well as Figure 6 , Figure 9 , Figure 12 and Figure 15In the example, the on-level is a high logic level used to turn on the corresponding transistor, and the off-level is a low logic level used to turn off the transistor, or insufficient to turn on the corresponding transistor. This example does not limit the range of transistors. In some implementations, the on-level can be low and the off-level can be high, depending on the type of transistor used. Each of the first phase clocks CLK-P1 through the fourth phase clocks CLK-P4 can have multiple on-level periods in a frame. On the other hand, each of the start signal VST and the scan signals SCAN1 through SCAN4 can have one on-level period in a frame. In particular, the start signal VST can have an on-level period overlapping with the first on-level period of the first phase clock CLK-P1 in a frame, and can have an off-level in other periods.

[0064] Figure 5 This is a diagram illustrating the circuit configuration of the gate stage included in the gate driver according to the first embodiment. Figure 6 It is shown Figure 5 The diagram shows the operating waveform of the gate stage.

[0065] Reference Figure 5 and Figure 6 The gate-level SG can operate based on a first clock CLK1 to a fourth clock CLK4, a start signal VST, a set signal SET, and a reset signal RESET to output the scan signal SCAN to the output node NO. In other words, the gate-level SG can receive the set signal SET and a first clock CLK1 with a first phase on-level. A second clock CLK2 has a second phase on-level later than the first phase, a third clock CLK3 has a third phase on-level later than the second phase, the reset signal RESET and the fourth clock CLK4 have a fourth phase on-level later than the third phase, and it can output the scan signal SCAN with a second phase on-level to the output node NO. The on-level phase of the start signal VST can be earlier than or equal to the set signal SET.

[0066] The gate stage SG may include: first series-connected transistors T1 and T2, which are used to apply a second clock signal CLK2 with an on level to node Q based on a first clock CLK1; second series-connected transistors T3 and T4, which are used to apply a second clock signal CLK2 with an off level to node Q based on a reset signal RESET and the voltage of a second control node (hereinafter referred to as node Qb); a fifth transistor T5, which is used to apply a fourth clock CLK4 with an on level to node Qb; a sixth transistor T6, which is used to apply a fourth clock CLK4 with an off level to node Qb based on a set signal SET; a pull-up transistor T7, which is used to apply the second clock CLK2 to output node NO based on the voltage of node Q; a pull-down transistor T8, which is used to apply a start signal VST with an off level to output node NO based on the voltage of node Qb; and a leakage current blocker LCB, which is used to block the leakage current of the first series-connected transistors T1 and T2 and the second series-connected transistors T3 and T4 during the period when node Q is floating. Here, the first series-connected transistors T1 and T2 may include a first transistor T1 and a second transistor T2 connected in series with each other, and the second series-connected transistors T3 and T4 may include a third transistor T3 and a fourth transistor T4 connected in series with each other.

[0067] The leakage current blocker LCB can apply a second clock CLK2 with a conduction level to the first node NA between the first series-connected transistors T1 and T2, and can apply a third clock CLK3 with a conduction level to the second node NB between the second series-connected transistors T3 and T4 during the floating period of node Q, thereby preventing abnormal discharge of node Q and the resulting distortion of the scan signal SCAN. In this case, the second clock CLK2 with a conduction level can not overlap with the third clock CLK3 with a conduction level, thus achieving an effect of increasing the reverse bias application period relative to the series-connected transistors. In some embodiments (e.g., Figure 9 As shown in the diagram, based on the clock design, the second clock CLK2 with a conduction level can partially overlap with the third clock CLK3 with a conduction level.

[0068] The leakage current blocker LCB may include a first blocking transistor TA and a second blocking transistor TB. The first blocking transistor TA applies a second clock CLK2 with an on level to a first node NA between the first transistor T1 and the second transistor T2, and the second blocking transistor TB applies a third clock CLK3 with an on level to a second node NB between the third transistor T3 and the fourth transistor T4. For example, when the second clock signal CLK2 is at an on level, the first blocking transistor TA is on, and when the third clock signal CLK3 is at an on level, the second blocking transistor TB is on.

[0069] In some implementations, the gate electrode and first electrode of the first blocking transistor TA can be connected to the input terminal of the second clock CLK2, and the second electrode of the first blocking transistor TA can be connected to the first node NA. The gate electrode and first electrode of the second blocking transistor TB can be connected to the input terminal of the third clock CLK3, and the second electrode of the second blocking transistor TB can be connected to the second node NB.

[0070] The first clock CLK1 can have a cutoff level during the period when node Q is floating, and in this case, when the second clock CLK2 with a conduction level is applied to the first node NA, the gate-source voltage of each of the first transistor T1 and the second transistor T2 can be sufficiently negative (-). Therefore, even when the threshold voltage of each of the first transistor T1 and the second transistor T2 is shifted in the negative (-) direction due to peripheral light, the first transistor T1 and the second transistor T2 can remain in the cutoff state, and abnormal leakage current in the first transistor T1 and the second transistor T2 can be prevented.

[0071] Furthermore, the reset signal RESET and the voltage of node Qb can have a cutoff level during the period when node Q is floating. In this case, when the third clock CLK3 with a conduction level is applied to the second node NB, the gate-source voltage of each of the third transistor T3 and the fourth transistor T4 can be sufficiently negative (-). Therefore, even when the threshold voltage of each of the third transistor T3 and the fourth transistor T4 is shifted in the negative (-) direction due to peripheral light, the third transistor T3 and the fourth transistor T4 can remain in the cutoff state, and abnormal leakage current in the third transistor T3 and the fourth transistor T4 can be prevented.

[0072] In some embodiments, the channel size of the first blocking transistor TA is smaller than the channel size of each of the first transistor T1 and the second transistor T2, and the channel size of the second blocking transistor TB is smaller than the channel size of each of the third transistor T3 and the fourth transistor T4. Furthermore, for operational stability and a narrow formation region of the gate stage, the channel size of each of the first blocking transistor TA and the second blocking transistor TB can be designed to be smaller than the channel size of each of the first transistor T1 to the sixth transistor T6. For example, the channel size of each of the first blocking transistor TA and the second blocking transistor TB can be designed to be 1 / 10 to 1 / 5 times the channel size of each of the first transistor T1 to the sixth transistor T6. Furthermore, to improve the output response characteristics of the scan signal, the channel size of each of the pull-up transistor T7 and the pull-down transistor T8 can be designed to be larger than the channel size of each of the first transistor T1 to the sixth transistor T6. For example, the channel size of each of the pull-up transistor T7 and the pull-down transistor T8 can be designed to be 10 times the channel size of each of the first transistor T1 to the sixth transistor T6.

[0073] Figure 7A It is shown Figure 6 A diagram of the gate stage operating states during the first time period. Figure 7B It is shown Figure 6 A diagram showing the operating states of the gate stage during the second time period. Figure 7C It is shown Figure 6 A diagram showing the operating states of the gate stage during the third time period. Figure 7D It is shown Figure 6 A diagram showing the operating states of the gate stage in the fourth time period.

[0074] Combining Figure 6 Reference Figures 7A to 7D The configuration and operation of the gate level (SG) are described in detail.

[0075] Reference Figure 6 and Figure 7A The first series-connected transistors T1 and T2 can be turned on during the first time period P1 based on a first clock CLK1 with an on-level, and a set signal SET with an on-level can be applied to node Q. The first clock CLK1 and the set signal SET can both have on-levels during the first time period P1. The sixth transistor T6 can be turned on during the first time period P1 based on the set signal SET with an on-level, and a fourth clock CLK4 with a off-level can be applied to node Qb.

[0076] Reference Figure 6 and Figure 7BThe pull-up transistor T7 can be turned on in the second time period P2 after the first time period P1, based on the voltage of node Q which is bootstrapping from the on-level. It can also apply a second clock CLK2 to the output node NO, the on-level of which is later than the first clock CLK1. The second clock CLK2 can be on-level in the second time period P2. In the second time period P2, the output node NO can output a scan signal SCAN with an on-level based on the second clock CLK2.

[0077] Reference Figure 6 and Figure 7C The third time period P3 can be positioned between the second time period P2 and the fourth time period P4. During the second time period P2 and the third time period P3, node Q can be floating because the first series-connected transistors T1 and T2 and the second series-connected transistors T3 and T4 are off. During the second time period P2 and the third time period P3 with node Q floating, based on the second clock CLK2 with a conduction level and the third clock CLK3 with a conduction level, the leakage current blocker LCB can block the leakage current through the first series-connected transistors T1 and T2 and the second series-connected transistors T3 and T4.

[0078] Reference Figure 6 and Figure 7D Each of the second series-connected transistors T3 and T4 can be turned on in the fourth time period P4 based on the voltage of the reset signal RESET with an on-level and the voltage of node Qb, and a second clock CLK2 with an off-level can be applied to node Q. The voltage of the reset signal RESET and the voltage of node Qb can have an on-level in the fourth time period P4.

[0079] In the fourth time period P4, the fifth transistor T5 can apply the fourth clock CLK4 with the on level to node Qb, and the phase of the fourth clock CLK4 with the on level can be later than the third clock CLK3 with the on level.

[0080] The pull-down transistor T8 can be turned on based on the voltage of node Qb using the fourth clock CLK4 with an on level, and can apply a start signal VST with a cutoff level to the output node NO. The start signal VST can remain on for a specific period within a frame and can remain off for other periods within a frame. This specific period can be the first on level period of the first clock CLK1, or it can be earlier than the first on level period of the first clock CLK1.

[0081] Figure 8 This is a diagram illustrating another circuit configuration of the gate stage included in the gate driver according to the first embodiment. Figure 9 It is shown Figure 8 The diagram shows the operating waveform of the gate stage.

[0082] Reference Figure 8 and Figure 9 The gate stage (SG) can operate based on the overlapping phase portions of the conduction levels of adjacent phase clocks, specifically the first to sixth phase clocks. The gate stage (SG) can receive the first phase clock (CLK-P1), the third phase clock (CLK-P3), the fourth phase clock (CLK-P4), and the fifth phase clock (CLK-P5) as the first clock (CLK1), the third clock (CLK3), the fourth clock (CLK4), and the fifth clock (CLK5), respectively.

[0083] and Figure 5 Compared to the gate-level SG, Figure 8 The difference in the gate level SG is that the third clock CLK3 is applied to transistor TA, the third clock CLK3 is applied to transistor T7, the fourth clock CLK4 is applied to transistor TB, the third clock CLK3 is applied to transistor T4, and the fifth clock CLK5 is applied to transistor T5, but other components can be essentially the same. During the period when node Q is floating, including Figure 8 The leakage current blocker LCB in the gate stage SG can apply a third clock CLK3 with an on level to the first node NA between the first series-connected transistors T1 and T2, and can apply a fourth clock CLK4 with an on level to the second node NB between the second series-connected transistors T3 and T4, thereby preventing abnormal discharge of node Q and the resulting distortion of the scan signal SCAN.

[0084] Figure 10 It is shown Figure 1 A figure of a second embodiment of the gate driver.

[0085] Reference Figure 10 According to a second embodiment of the present disclosure, the gate driver 130 may include a plurality of gate stages SG1 to SG4 respectively connected to the gate line pairs.

[0086] Each of the gate stages SG1 to SG4 can generate two scan signals with different phases, providing a first scan signal to a first gating line included in the gating line pair and a second scan signal to a second gating line included in the gating line pair.

[0087] Each of the gate stages SG1 to SG4 may include a first additional output node NO1 and a second additional output node NO2, through which a first scan signal is output and a second scan signal is output. Because the carry output node CNO, through which the carry signal CRY is output, is divided into the first additional output node NO1 and the second additional output node NO2, distortion of the carry signal CRY due to panel load can be prevented.

[0088] Each of gate stages SG1 to SG4 may include a first terminal to which a set signal SET is input, a second terminal to which a start signal VST is input, and a third terminal to which a reset signal RESET is input. Furthermore, each of gate stages SG1 to SG4 may include a first clock terminal to which a first clock CLK1 is input, a second clock terminal to which a second clock CLK2 is input, a third clock terminal to which a third clock CLK3 is input, and a fourth clock terminal to which a fourth clock CLK4 is input. The second clock CLK2 may function as the output of a carry signal CRY, but may not function as the output of a first scan signal or a second scan signal. Each of gate stages SG1 to SG4 may also receive scan clock 1 and scan clock 2 (in the example of SG1) for the output of the first scan signal and the second scan signal via the first additional output node (NO1) and the second additional output node NO2. When node Q is activated, the carry signal CRY and the first scan signal may be output to the output node and the first additional output node, respectively, and subsequently, the second scan signal may be output to the second additional output node. Each of the gate stages SG1 to SG4 may not require a power input terminal, thus simplifying its configuration.

[0089] Gate stages SG1 to SG4 can be connected to each other in a cascaded manner, and carry signals CRY can be transmitted and received between them. Gate stages SG1 to SG4 can be connected to a start line through which a start signal VST is provided, clock lines L1 to L4 through which the first phase clock CLK-P1 to the fourth phase clock CLK-P4 are provided, and additional clock lines L5 to L12 through which the first phase scan clock SCLK-P1 to the eighth phase scan clock SCLK-P are provided.

[0090] The first gate stage SG1 of gate stages SG1 to SG4 can begin operation based on a start signal VST input to its first terminal. The set signal SET of the first gate stage SG1 can be the start signal VST. Each of the other gate stages SG2 to SG4, excluding the first gate stage SG1, can begin operation based on a previous carry signal CRY input to its first terminal (i.e., node Q can be activated at the on level). The set signal SET of each of the other gate stages SG2 to SG4 can be the previous carry signal CRY. The operation of each of the gate stages SG1 to SG4 can be reset based on a next carry signal CRY input to its third terminal (i.e., node Q can be deactivated at the off level). The reset signal RESET of each of the other gate stages SG1 to SG4 can be the next carry signal CRY. Here, for the nth gate stage, the previous carry signal CRY can be output from the (n-1)th gate stage, and the next carry signal CRY can be output from the (n+2)th gate stage.

[0091] Each of the gate stages SG1 to SG4 can be connected to the first terminal of the next gate stage via the carry output node CNO, to the first gate line included in the gate line pair via the first additional output node NO1, and to the second gate line included in the gate line pair via the second additional output node NO2.

[0092] The first phase clock CLK-P1 can be provided to the first clock line L1, the second phase clock CLK-P2 (later than the first phase clock CLK-P1) can be provided to the second clock line L2, the third phase clock CLK-P3 (later than the second phase clock CLK-P2) can be provided to the third clock line L3, and the fourth phase clock CLK-P4 (later than the third phase clock CLK-P3) can be provided to the fourth clock line L4. The conduction phases of the first phase clock CLK-P1 to the fourth phase clock CLK-P4 do not need to overlap. On the other hand, the conduction phases of adjacent phase scan clocks among the first phase scan clocks SCLK-P1 to the eighth phase scan clocks SCLK-P8 can overlap. Each of the first phase scan clocks SCLK-P1 to the eighth phase scan clocks SCLK-P8 can be sequentially applied to two adjacent gate stages based on a phase asymmetry scheme.

[0093] Gate stage 4K-3 (where K is a natural number) can receive the first phase clock CLK-P1, the second phase clock CLK-P2, the third phase clock CLK-P3, and the fourth phase clock CLK-P4 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively. Gate stage 4K-3 can also receive the first phase scan clock SCLK-P1 and the second phase scan clock SCLK-P2 as scan clock 1 and scan clock 2, respectively.

[0094] Gate stage 4K-2 can receive the second phase clock CLK-P2, the third phase clock CLK-P3, the fourth phase clock CLK-P4, and the first phase clock CLK-P1 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively. Gate stage 4K-2 can also receive the third phase scan clock SCLK-P3 and the fourth phase scan clock SCLK-P4 as scan clock 1 and scan clock 2, respectively.

[0095] Gate stage 4K-1 can receive the third phase clock CLK-P3, the fourth phase clock CLK-P4, the first phase clock CLK-P1, and the second phase clock CLK-P2 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively. Gate stage 4K-1 can also receive the fifth phase scan clock SCLK-P5 and the sixth phase scan clock SCLK-P6 as scan clock 1 and scan clock 2, respectively.

[0096] Furthermore, the 4K gate stage can receive the fourth phase clock CLK-P4, the first phase clock CLK-P1, the second phase clock CLK-P2, and the third phase clock CLK-P3 as the first clock CLK1, the second clock CLK2, the third clock CLK3, and the fourth clock CLK4, respectively. The 4K gate stage can also receive the seventh phase scan clock SCLK-P7 and the eighth phase scan clock SCLK-P8 as scan clock 1 and scan clock 2, respectively.

[0097] Each of the gate stages SG1 to SG4 can output a first scan signal and a second scan signal, separated from the carry signal CRY, based on the connection configuration described above. Because each gate stage outputs two scan signals by using one node Q and one node Qb, the number of stages can be reduced by half the number of gate lines, and therefore the area of ​​the bezel region occupied by the gate driver 130 can be reduced.

[0098] Figure 11 This is a diagram illustrating the circuit configuration of the gate stage included in the gate driver according to the second embodiment. Figure 12 It is shown Figure 11The diagram shows the operating waveform of the gate stage.

[0099] Reference Figure 11 and Figure 12 The gate-level SG can operate based on the first clock CLK1 to the fourth clock CLK4, the scan clock 1SCLK3, the scan clock 2SCLK4, the start signal VST, the set signal SET, and the reset signal RESET to output the carry signal CRY to the carry output node CNO, output the scan signal 1SCAN3 to the first additional output node NO1, and output the scan signal 2SCAN4 to the second additional output node NO2. In other words, the gate-level SG can receive the set signal SET and the first clock CLK1 with a first phase on-level, the second clock CLK2 with a second phase on-level later than the first phase, the third clock CLK3 with a third phase on-level later than the second phase, and the reset signal RESET and the fourth clock CLK4 with a fourth phase on-level later than the third phase, and can output the carry signal CRY with a second phase on-level to the carry output node CNO. The gate stage SG can receive a scan clock 1SCLK3 with a second-phase on-level to output a scan signal 1SCAN3 with a second-phase on-level to the first additional output node NO1, and can receive a scan clock 2SCLK4 with an on-level of an intermediate phase overlapping the second and third phases to output a scan signal 2SCAN4 with an intermediate phase on-level to the second additional output node NO2. In this case, the on-level phase of the start signal VST can be earlier than or equal to the set signal SET.

[0100] The gate stage SG may include: first series-connected transistors T1a, T1, and T2, which are used to apply a second clock signal CLK2 with a conduction level to node Q based on a first clock CLK1; second series-connected transistors T3 and T4, which are used to apply a second clock signal CLK2 with a cutoff level to node Q based on a reset signal RESET and the voltage of node Qb; a fifth transistor T5, which is used to apply a fourth clock CLK4 with a conduction level to node Qb; a sixth transistor T6, which is used to apply a fourth clock CLK4 with a cutoff level to node Qb based on a set signal SET; a pull-up transistor T7, which is used to apply the second clock CLK2 to the carry output node CNO based on the voltage of node Q; and a pull-down transistor T8, used for... A start signal VST with a cutoff level is applied to the carry output node CNO based on the voltage of node Qb; a first additional pull-up transistor T7A is used to apply scan clock 1SCLK3 to the first additional output node NO1 based on the voltage of node Q; a first additional pull-down transistor T8A is used to apply the start signal VST with a cutoff level to the first additional output node NO1 based on the voltage of node Qb; a second additional pull-up transistor T7B is used to apply scan clock 2SCLK4 to the second additional output node NO2 based on the voltage of node Q; and a leakage current blocker LCB is used to block the leakage current of the first series-connected transistors T1a, T1, and T2 and the second series-connected transistors T3 and T4 during the period when node Q is floating. Here, the first series-connected transistors T1a, T1, and T2 may include the first additional transistor T1a, the first transistor T1, and the second transistor T2 connected in series with each other, and the second series-connected transistors T3 and T4 may include the third transistor T3 and the fourth transistor T4 connected in series with each other.

[0101] The leakage current blocker LCB applies a second clock CLK2 with an on-level to the first node NA between the first series-connected transistors T1 and T2, applies a third clock CLK3 with an on-level to the second node NB between the second series-connected transistors T3 and T4, and applies the third clock CLK3 with an on-level to the third node NC between the second series-connected transistors T1a and T1 during the floating period of node Q, thereby preventing abnormal discharge of node Q and the resulting distortion of the scan signal SCAN. In this case, the second clock CLK2 with an on-level can not overlap with the third clock CLK3 with an on-level, thus achieving an increased reverse bias application period relative to the series-connected transistors. Furthermore, based on the clock design, the second clock CLK2 with an on-level can partially overlap with the third clock CLK3 with an on-level.

[0102] The leakage current blocker LCB may include a first blocking transistor TA, a second blocking transistor TB, and a third blocking transistor TC. The first blocking transistor TA applies a second clock CLK2 with a conduction level to a first node NA between the first transistor T1 and the second transistor T2. The second blocking transistor TB applies a third clock CLK3 with a conduction level to a second node NB between the third transistor T3 and the fourth transistor T4. The third blocking transistor TC applies a third clock CLK3 with a conduction level to a third node NC between the first auxiliary transistor T1a and the first transistor T1.

[0103] The gate and first electrode of the first blocking transistor TA can be connected to the input terminal of the second clock CLK2, and the second electrode of the first blocking transistor TA can be connected to the first node NA. The gate and first electrode of the second blocking transistor TB can be connected to the input terminal of the third clock CLK3, and the second electrode of the second blocking transistor TB can be connected to the second node NB. The gate and first electrode of the third blocking transistor TC can be connected to the input terminal of the third clock CLK3, and the second electrode of the third blocking transistor TC can be connected to the third node NC.

[0104] The first clock CLK1 can have a cutoff level during the period when node Q is floating, and in this case, when the second clock CLK2 with a conduction level is applied to the first node NA, the gate-source voltage of each of the first transistor T1 and the second transistor T2 can be sufficiently negative (-). Therefore, even when the threshold voltage of each of the first transistor T1 and the second transistor T2 is shifted in the negative (-) direction due to peripheral light, the first transistor T1 and the second transistor T2 can remain in the cutoff state, and abnormal leakage current in the first transistor T1 and the second transistor T2 can be prevented.

[0105] Furthermore, the first clock CLK1 can have a cutoff level during the period when node Q is floating, and in this case, when the third clock CLK3 with a conduction level is applied to the third node NC, the gate-source voltage of each of the first auxiliary transistor T1a and the first transistor T1 can be a sufficiently negative (-) voltage. Therefore, even when the threshold voltage of each of the first auxiliary transistor T1a and the first transistor T1 is shifted in the negative (-) direction due to peripheral light, the first auxiliary transistor T1a and the first transistor T1 can remain in the cutoff state, and abnormal leakage current in the first auxiliary transistor T1a and the first transistor T1 can be prevented.

[0106] Furthermore, the reset signal RESET and the voltage of node Qb can have a cutoff level during the period when node Q is floating. In this case, when the third clock CLK3 with a conduction level is applied to the second node NB, the gate-source voltage of each of the third transistor T3 and the fourth transistor T4 can be sufficiently negative (-). Therefore, even when the threshold voltage of each of the third transistor T3 and the fourth transistor T4 is shifted in the negative (-) direction due to peripheral light, the third transistor T3 and the fourth transistor T4 can remain in the cutoff state, and abnormal leakage current in the third transistor T3 and the fourth transistor T4 can be prevented.

[0107] In some embodiments, the channel size of the first blocking transistor TA is smaller than the channel size of each of the first transistor T1, the second transistor T2, and the first additional transistor T1a. The channel size of the second blocking transistor TB is smaller than the channel size of each of the third transistor T3 and the fourth transistor T4. The channel size of the third blocking transistor TC is smaller than the channel size of each of the first transistor T1, the second transistor T2, and the first additional transistor T1a. Furthermore, for operational stability and a narrow formation region of the gate stage, the channel size of each of the first to third blocking transistors TA, TB, and TC can be configured to be smaller than the channel size of each of the first transistor T1 to the sixth transistor T6. For example, the channel size of each of the first blocking transistor TA and the second blocking transistor TB can be designed to be 1 / 10 to 1 / 5 times the channel size of each of the first transistor T1 to the sixth transistor T6. Furthermore, to improve the output response characteristics of the scan signal, the channel size of each of the pull-up transistor T7 and the pull-down transistor T8 can be designed to be larger than the channel size of each of the first transistor T1 to the sixth transistor T6. For example, the channel size of each of the pull-up transistor T7 and the pull-down transistor T8 can be designed to be 10 times the channel size of each of the first transistor T1 to the sixth transistor T6.

[0108] Figure 13A It is shown Figure 12 A diagram of the gate stage operating states during the first time period. Figure 13B It is shown Figure 12 A diagram showing the operating states of the gate stage during the second time period. Figure 13C It is shown Figure 12 A diagram showing the operating states of the gate stage during the third time period. Figure 13D It is shown Figure 12 A diagram showing the operating states of the gate stage in the fourth time period.

[0109] Combining Figure 12 Reference Figures 13A to 13D Additional description of the configuration and operation of the gate level (SG).

[0110] Reference Figure 12 The first series-connected transistors T1a, T1, and T2 can be turned on during the first time period P1 based on a first clock CLK1 with an on-level, and can apply a set signal SET with an on-level to node Q. The first clock CLK1 and the set signal SET can both have on-levels during the first time period P1. The sixth transistor T6 can be turned on during the first time period P1 based on the set signal SET with an on-level, and can apply a fourth clock CLK4 with a off-level to node Qb.

[0111] Reference Figure 12 and Figure 13B The pull-up transistor T7 can be turned on in the second time period P2, following the first time period P1, based on the voltage of node Q, which is bootstrapping from the on-level. It can also apply a second clock CLK2 to the carry output node CNO, the on-level of which is later than the first clock CLK1. The second clock CLK2 can be on-level in the second time period P2. In the second time period P2, the carry output node CNO can output a carry signal CRY with an on-level based on the second clock CLK2.

[0112] Furthermore, the first additional pull-up transistor T7A can be turned on based on the voltage of node Q during the second time period P2, and a scan clock 1SCLK3 with the same turn-on level phase as the second clock CLK2 can be applied to the first additional output node NO1. During the second time period P2, the first additional output node NO1 can output a turn-on level scan signal 1SCAN3 based on the scan clock 1SCLK3.

[0113] Furthermore, the second additional pull-up transistor T7B can be turned on based on the voltage of node Q during the second time period P2 and the third time period P3, and can apply the second clock CLK2 and the third clock CLK3, which have on-level phases, to the second additional output node NO2. During the second time period P2 and the third time period P3, the second additional output node NO2 can output the on-level scan signal 2SCAN4 based on the scan clock 2SCLK4.

[0114] Reference Figure 12 and Figure 13CThe third time period P3 can be positioned between the second time period P2 and the fourth time period P4. During the second time period P2 and the third time period P3, node Q can be floating because the first series-connected transistors T1a, T1, and T2, and the second series-connected transistors T3 and T4 are off. During the second time period P2 and the third time period P3, when node Q is floating, the leakage current blocker LCB can block the leakage current through the first series-connected transistors T1a, T1, and T2, and the second series-connected transistors T3 and T4, based on the second clock CLK2 and the third clock CLK3, which have on-level signals.

[0115] Reference Figure 12 and Figure 13D Each of the second series-connected transistors T3 and T4 can be turned on in the fourth time period P4 based on the voltage of the reset signal RESET with an on-level and the voltage of node Qb, and a second clock CLK2 with an off-level can be applied to node Q. The voltage of the reset signal RESET and the voltage of node Qb can have an on-level in the fourth time period P4.

[0116] In the fourth time period P4, the fifth transistor T5 can apply the fourth clock CLK4 with the on level to node Qb, and the phase of the fourth clock CLK4 with the on level can be later than the third clock CLK3 with the on level.

[0117] The pull-down transistor T8 can be turned on using the voltage of node Qb based on the fourth clock CLK4 with the turn-on voltage, and can apply the start signal VST with the cut-off level to the carry output node CNO.

[0118] Furthermore, in the fourth time period P4, the first additional pull-down transistor T8A can be turned on using the voltage of node Qb and can apply a start signal VST with a cutoff level to the first additional output node NO1, and the second additional pull-down transistor T8B can be turned on using the voltage of node Qb and can apply a start signal VST with a cutoff level to the second additional output node NO2.

[0119] The start signal VST can remain on for a specific period of time within a frame and can remain off for other periods of time within a frame besides the specific period of time. The specific period of time can be the first on-level period of the first clock CLK1 or can be earlier than the first on-level period of the first clock CLK1.

[0120] Figure 14 This is a diagram illustrating another circuit configuration of the gate stage included in the gate driver according to the second embodiment. Figure 15 It is shown Figure 14The diagram shows the operating waveform of the gate stage.

[0121] Reference Figure 14 and Figure 15 ,and Figure 11 Compared to the gate-level SG, the gate-level SG can differ only in the connection configuration of the leakage current blocker LCB, and other components can be the same. Figure 11 The gate-level SG components are basically the same. And... Figure 11 Compared to the gate-level SG, Figure 14 The configuration can be further simplified.

[0122] The leakage current blocker LCB included in the gate stage SG can apply a second clock CLK2 with an on-level and a third clock CLK3 with an on-level to the first node NA between the first series-connected transistors T1 and T2, and can apply the third clock CLK3 with an on-level to the second node NB between the second series-connected transistors T3 and T4 during the second period P2 and the third period P3 when node Q is floating, thereby preventing abnormal discharge of node Q and the resulting distortion of the scan signal SCAN. In this case, the second clock CLK2 with an on-level can not overlap with the third clock CLK3 with an on-level, thus achieving an effect of increasing the reverse bias application period relative to the series-connected transistors. Furthermore, based on the clock design, the second clock CLK2 with an on-level can partially overlap with the third clock CLK3 with an on-level.

[0123] The leakage current blocker LCB may include: a first blocking transistor TA, which applies a second clock CLK2 with an on level to a first node NA between the first transistor T1 and the second transistor T2 during a second time period P2; a third blocking transistor TC, which applies a third clock CLK3 with an on level to the first node NA during a third time period P3; and a second blocking transistor TB, which applies a third clock CLK3 with an on level to a second node NB between the third transistor T3 and the fourth transistor T4.

[0124] The gate and first electrode of the first blocking transistor TA can be connected to the input terminal of the second clock CLK2, and the second electrode of the first blocking transistor TA can be connected to the first node NA. The gate and first electrode of the second blocking transistor TB can be connected to the input terminal of the third clock CLK3, and the second electrode of the second blocking transistor TB can be connected to the second node NB. The gate and first electrode of the third blocking transistor TC can be connected to the input terminal of the third clock CLK3, and the second electrode of the third blocking transistor TC can be connected to the first node NA.

[0125] During the floating period of node Q, the first clock CLK1 can have a cutoff level, and in this case, when the second clock CLK2 and the third clock CLK3, which have on-levels, are applied to the first node NA, the gate-source voltage of each of the first transistor T1 and the second transistor T2 can be sufficiently negative (-). Therefore, even when the threshold voltage of each of the first transistor T1 and the second transistor T2 is shifted in the negative (-) direction due to peripheral light, the first transistor T1 and the second transistor T2 can remain in the cutoff state, and abnormal leakage current in the first transistor T1 and the second transistor T2 can be prevented.

[0126] Furthermore, the reset signal RESET and the voltage of node Qb can have a cutoff level during the period when node Q is floating. In this case, when the third clock CLK3 with a conduction level is applied to the second node NB, the gate-source voltage of each of the third transistor T3 and the fourth transistor T4 can be sufficiently negative (-). Therefore, even when the threshold voltage of each of the third transistor T3 and the fourth transistor T4 is shifted in the negative (-) direction due to peripheral light, the third transistor T3 and the fourth transistor T4 can remain in the cutoff state, and abnormal leakage current in the third transistor T3 and the fourth transistor T4 can be prevented.

[0127] Furthermore, to ensure operational stability and a narrow formation region at the gate level, the channel size of each of the first to third blocking transistors TA, TB, and TC can be designed to be smaller than the channel size of each of the first to sixth transistors T1. For example, the channel size of each of the first blocking transistor TA and the second blocking transistor TB can be designed to be 1 / 10 to 1 / 5 times the channel size of each of the first to sixth transistors T6. Additionally, to improve the output response characteristics of the scan signal, the channel size of each of the pull-up transistor T7 and the pull-down transistor T8 can be designed to be larger than the channel size of each of the first to sixth transistors T6. For example, the channel size of each of the pull-up transistor T7 and the pull-down transistor T8 can be designed to be 10 times the channel size of each of the first to sixth transistors T6.

[0128] In the gate driver and the electroluminescent display device including the gate driver according to the embodiments of the present disclosure, the configuration of the gate level can be simplified, and thus a narrow bezel can be achieved.

[0129] In the gate driver and the electroluminescent display device including the gate driver according to embodiments of the present disclosure, the gate stages can be configured to operate based on a clock without a driving power supply, and each gate stage can include a leakage current blocker to increase operational stability.

[0130] The effects of this disclosure are not limited to the examples above, and various other effects may be included in this specification.

[0131] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0132] Cross-references to related applications

[0133] This application claims the benefit of Korean Patent Application No. 10-2021-0185479, filed on December 22, 2021, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A gate driver comprising multiple stages, each of the multiple stages comprising: First series-connected transistors, each of the first series-connected transistors being configured to be turned on during a first time period based on a first clock signal having an on level to apply a set signal having an on level to a first control node; A pull-up transistor is configured to turn on in a second period following the first period based on the voltage of the first control node bootstrapping from the on-level to apply a second clock signal to the output node, the on-level phase of the second clock signal being later than that of the first clock signal. The second series-connected transistor is turned on in a fourth period later than the second period based on a reset signal with an on level and the voltage of the second control node to apply the second clock signal with an off level to the first control node. as well as A leakage current blocker is used to block the leakage current of the first series-connected transistor and the second series-connected transistor when the first control node is floating, based on a second clock signal having a conduction level in the second time period and a third clock signal having a conduction level in the third time period between the second time period and the fourth time period.

2. The gate driver according to claim 1, wherein, The first series-connected transistor includes a first transistor and a second transistor connected in series with each other. The second series-connected transistor includes a third transistor and a fourth transistor connected in series with each other, and The leakage current blocker includes: A first blocking transistor, configured to apply a second clock signal having the on-level to a first node between the first transistor and the second transistor during the second time period; and A second blocking transistor is configured to apply the third clock signal having the on level to a second node between the third transistor and the fourth transistor during the third time period.

3. The gate driver according to claim 2, wherein, The gate electrode and first electrode of the first blocking transistor are connected to an input terminal for receiving the second clock signal, and the second electrode of the first blocking transistor is connected to the first node. The gate electrode and the first electrode of the second blocking transistor are connected to the input terminal for receiving the third clock signal, and the second electrode of the second blocking transistor is connected to the second node.

4. The gate driver according to claim 2, wherein, The channel size of the first blocking transistor is smaller than the channel size of each of the first transistor and the second transistor, and The channel size of the second blocking transistor is smaller than the channel size of each of the third and fourth transistors.

5. The gate driver according to claim 1, wherein, The output node includes a first additional output node and a second additional output node, and each of the plurality of stages further includes: A first additional pull-up transistor, configured to turn on based on the voltage of the first control node during the second time period to apply a first additional clock signal to the first additional output node; and A second additional pull-up transistor is configured to turn on based on the voltage of the first control node during the second and third time periods to apply a second additional clock signal to the second additional output node. Wherein, the first additional clock signal has the same conduction level phase as the second clock signal, and The second additional clock signal overlaps with the second clock signal and the third clock signal in the conduction level phase.

6. The gate driver according to claim 5, wherein, The first series-connected transistor includes a first additional transistor, a first transistor, and a second transistor connected in series with each other. The second series-connected transistor includes a third transistor and a fourth transistor connected in series with each other, and The leakage current blocker includes: A first blocking transistor is configured to apply a second clock signal having the on level to a first node between the first transistor and the second transistor during the second time period; A second blocking transistor, configured to apply the third clock signal having the on level to a second node between the third transistor and the fourth transistor during the third time period; and A third blocking transistor is configured to apply a third clock signal having the on level to a third node between the first additional transistor and the first transistor during the third time period.

7. The gate driver according to claim 6, wherein, The gate electrode and first electrode of the first blocking transistor are connected to an input terminal for receiving the second clock signal, and the second electrode of the first blocking transistor is connected to the first node. The gate electrode and first electrode of the second blocking transistor are connected to the input terminal for receiving the third clock signal, and the second electrode of the second blocking transistor is connected to the second node. The gate electrode and the first electrode of the third blocking transistor are connected to the input terminal for receiving the third clock signal, and the second electrode of the third blocking transistor is connected to the third node.

8. The gate driver according to claim 6, wherein, The channel size of the first blocking transistor is smaller than the channel size of each of the first transistor, the second transistor, and the first additional transistor. The channel size of the second blocking transistor is smaller than the channel size of each of the third and fourth transistors, and The channel size of the third blocking transistor is smaller than the channel size of each of the first transistor, the second transistor, and the first additional transistor.

9. The gate driver according to claim 5, wherein, The first series-connected transistor includes a first transistor and a second transistor connected in series with each other. The second series-connected transistor includes a third transistor and a fourth transistor connected in series with each other, and The leakage current blocker includes: A first blocking transistor is configured to apply a second clock signal having the on level to a first node between the first transistor and the second transistor during the second time period; A second blocking transistor, configured to apply the third clock signal having the on level to a second node between the third transistor and the fourth transistor during the third time period; and A third blocking transistor is configured to apply the third clock signal having the on level to the first node during the third time period.

10. The gate driver according to claim 9, wherein, The gate electrode and first electrode of the first blocking transistor are connected to an input terminal for receiving the second clock signal, and the second electrode of the first blocking transistor is connected to the first node. The gate electrode and first electrode of the second blocking transistor are connected to the input terminal for receiving the third clock signal, and the second electrode of the second blocking transistor is connected to the second node. The gate electrode and the first electrode of the third blocking transistor are connected to an input terminal for receiving the third clock signal, and the second electrode of the third blocking transistor is connected to the first node.

11. The gate driver according to claim 9, wherein, The channel size of the first blocking transistor is smaller than the channel size of each of the first transistor and the second transistor. The channel size of the second blocking transistor is smaller than the channel size of each of the third and fourth transistors, and The channel size of the third blocking transistor is smaller than the channel size of each of the first transistor and the second transistor.

12. The gate driver according to claim 1, wherein, The second clock signal having the on level is offset from the third clock signal having the on level.

13. The gate driver according to claim 1, wherein, The second clock signal having the said conduction level partially overlaps with the third clock signal having the said conduction level.

14. The gate driver according to claim 1, wherein, Each of the plurality of levels includes: A fifth transistor is configured to apply a fourth clock signal having an on level to the second control node during the fourth time period, the fourth clock signal having the on level and a phase later than that of the third clock signal having the on level; A pull-down transistor configured to turn on during the fourth time period according to the voltage of the second control node based on the fourth clock signal having an on level, so as to apply a start signal having an off level to the output node; and A sixth transistor, configured to be turned on during the first time period based on a set signal having an on level, to apply a fourth clock signal having an off level to the second control node. The start signal is configured to maintain an on level only during one period of a frame and to maintain an off level during another period of the same frame. The time period in the frame is the first on-level time period of the first clock signal.

15. The gate driver according to claim 1, wherein, Each of the plurality of levels also includes: A first additional pull-up transistor is configured to turn on based on the voltage of the first control node in the second time period to apply a first scan clock signal to a first additional output node, wherein the on-level phase of the first scan clock signal is the same as the on-level phase of the second clock signal. A second additional pull-up transistor is configured to be turned on based on the voltage of the first control node in the second and third time periods to apply a second scan clock signal to a second additional output node, wherein the on-level phase of the second scan clock signal partially overlaps with the second clock signal and the third clock signal. A fifth transistor is configured to apply a fourth clock signal having an on level during the fourth time period to the second control node, the phase of the on level of the fourth clock signal being later than the phase of the on level of the third clock signal; A pull-down transistor configured to turn on according to the voltage of the second control node of the fourth clock signal having an on level in the fourth time period to apply a start signal having the off level to the output node; A first additional pull-down transistor is configured to turn on based on the voltage of the second control node according to the voltage of the fourth clock signal having an on level in the fourth time period to apply the start signal having an off level to the first additional output node. A second additional pull-down transistor, configured to turn on according to the voltage of the second control node based on the fourth clock signal having an on level during the fourth time period, to apply the start signal having the off level to the second additional output node; and A sixth transistor, configured to be turned on based on a set signal having an on level during the first time period, to apply a fourth clock signal having an off level to the second control node. The start signal is maintained at an on level only during one period of a frame and at an off level during another period of the same frame. The time period in the frame is the first on-level time period of the first clock signal.

16. An electroluminescent display device, the electroluminescent display device comprising: The gate driver according to any one of claims 1 to 15; as well as Multiple pixels, each including a switching element that operates based on a scan signal from the output node of the gate driver. The scan signal is provided to the gate electrode of the switching element included in each of the plurality of pixels.

17. A gate driver comprising multiple stages, each of the multiple stages operatively receiving: a set signal and a first clock signal having an on-level at a first phase, a second clock signal having an on-level at a second phase later than the first phase, a third clock signal having an on-level at a third phase later than the second phase, and a reset signal and a fourth clock signal having an on-level at a fourth phase later than the third phase, for outputting a scan signal having an on-level at the second phase to an output node. in, Each of the plurality of levels includes: A first series-connected transistor is configured to apply a set signal having an on level to a first control node based on the first clock signal; The second series-connected transistor is configured to apply a second clock signal with a cutoff level to the first control node based on the reset signal and the voltage of the second control node. A fifth transistor, configured to apply the fourth clock signal having an on level to the second control node; A sixth transistor, the sixth transistor being configured to apply the fourth clock signal having a cutoff level to the second control node based on the set signal; A pull-up transistor configured to apply the second clock signal to the output node based on the voltage of the first control node; A pull-down transistor configured to apply a start signal with a cutoff level to the output node based on the voltage of the second control node; and A leakage current blocker is configured to apply a second clock signal having the on level to a first node between the first series-connected transistors during a period when the first control node is floating, and to apply a third clock signal having the on level to a second node between the second series-connected transistors.

18. The gate driver of claim 17, wherein, The first series-connected transistor includes a first transistor and a second transistor connected in series with each other. The second series-connected transistor includes a third transistor and a fourth transistor connected in series with each other, and The leakage current blocker includes: A first blocking transistor, configured to apply a second clock signal having the on-level to the first node between the first transistor and the second transistor; and A second blocking transistor is configured to apply the third clock signal having the on level to the second node between the third transistor and the fourth transistor.

19. The gate driver of claim 18, wherein, The gate electrode and first electrode of the first blocking transistor are connected to an input terminal for receiving the second clock signal, and the second electrode of the first blocking transistor is connected to the first node. The gate electrode and the first electrode of the second blocking transistor are connected to the input terminal for receiving the third clock signal, and the second electrode of the second blocking transistor is connected to the second node.

20. The gate driver of claim 18, wherein, The channel size of the first blocking transistor is smaller than the channel size of each of the first transistor and the second transistor, and The channel size of the second blocking transistor is smaller than the channel size of each of the third and fourth transistors.

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