Drive Circuit and Driving Method of a Display Panel

Abstract

The present application discloses a driving circuit and a driving method for a display panel. The display panel includes a plurality of data lines and a plurality of fan-out lines. The plurality of data lines are respectively connected to the plurality of fan-out lines in one-to-one correspondence. The driving circuit includes: a plurality of compensation circuits and a signal input unit. The compensation circuit includes an input end and an output end. The plurality of output ends are respectively connected to the plurality of fan-out lines. At least two gears are set in the compensation circuit. When the gear of the compensation circuit is increased, the capacitance value or the resistance value of the compensation circuit gradually decreases; the signal input unit outputs a data signal to the input ends of the plurality of compensation circuits; wherein, the compensation circuit selects a gear according to the gray scale of the data signal or the scanning time when the display panel scans line by line. Through the above solution, a low-cost solution for dynamically compensating different resistance values of the fan-out lines can be achieved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a driving circuit for a display panel and a driving method thereof. Background Art

[0002] A liquid crystal display (LCD) device includes an LCD panel for displaying images and a panel driving circuit for driving the LCD panel. The LCD panel generally includes an array substrate, on which are provided: switching elements, scan lines for transmitting gate voltage signals to the switching elements, and data lines for transmitting data voltage signals to the switching elements.

[0003] Among them, due to wiring problems, the data lines provide a plurality of fan-out wirings with different lengths at the data line and the bonding part. Each fan-out line binds and connects the corresponding output terminal of the driving chip to a corresponding one of the data lines in a fan-out manner. As the resolution of the display panel increases, the number of data lines increases, and the number of fan-out wirings also increases accordingly, thereby causing a greater degree of resistance and capacitance differences. In the prior art, it is proposed to make the lengths or impedances of the fan-out wirings at each position equal by winding the fan-out wirings. However, for the currently required narrow-bezel display panel, the above approach will affect the realization of the narrow bezel and limit the screen-to-body ratio. And choosing to add a PPCC (Programmable Panel Charging Compensation) function in the driving chip to solve the fanout mura problem by compensating the data signals output by the driving chip. However, the compensation ability of the driving chip with the PPCC function is limited, and the cost of the driving chip with the PPCC function is very high. Therefore, those skilled in the art urgently need a new solution to solve the problem of unbalanced impedances of the fan-out wirings. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit for a display panel and a driving method thereof, which can perform dynamic compensation for different resistances of the fan-out wirings and have a relatively low cost.

[0005] The present application discloses a driving circuit for a display panel. The display panel includes a plurality of data lines and a plurality of fan-out lines. The plurality of data lines are connected to the plurality of fan-out lines in a one-to-one correspondence. The driving circuit includes: a plurality of compensation circuits and a signal input unit. The compensation circuit includes an input end and an output end. The plurality of output ends are respectively connected to the plurality of fan-out lines. At least two gears are provided in the compensation circuit. When the gear of the compensation circuit increases, the capacitance value or resistance value of the compensation circuit gradually decreases. The signal input unit outputs a data signal to the input ends of the plurality of compensation circuits. Wherein, the compensation circuit selects a gear according to the gray scale of the data signal or the scanning time when the display panel scans line by line.

[0006] Optionally, on the same data line, when the gray scale of the data signal gradually decreases, the gear of the compensation circuit gradually increases; or within the scanning time of one frame of the display panel, in the direction of scanning line by line along the scanning lines, the gear of the compensation circuit on the same data line gradually increases.

[0007] Optionally, the number of the compensation circuits is less than or equal to the number of the fan-out lines; when the number of the compensation circuits is less than the number of the fan-out lines, at least two adjacent fan-out lines share one compensation circuit.

[0008] Optionally, the compensation circuit includes a gear selection circuit and a gating circuit. The gating circuit includes a plurality of channels. The resistance values or capacitance values of the plurality of channels increase in sequence. The control end of each channel is connected to the gear selection circuit. The gear selection circuit controls the conduction of the plurality of channels, and only one channel conducts at the same time.

[0009] Optionally, the gear selection circuit includes a control input end and n control output ends; the gating circuit includes n channels, where n is a positive integer greater than or equal to 2. The first channel includes a first active switch, a first resistor and a first capacitor. The nth channel includes an nth active switch, an nth resistor and an nth capacitor; one ends of the n channels are respectively connected to the input end of the compensation circuit, and the other ends of the n channels are respectively connected to the output end of the compensation circuit; wherein, the first active switch is connected in series with the first resistor, one end of the first capacitor is connected to one end of the first resistor, and the other end of the first capacitor is grounded; the nth active switch is connected in series with the nth resistor, one end of the nth capacitor is connected to one end of the nth resistor, and the other end of the nth capacitor is grounded; the n control output ends are respectively connected to the control ends of the first active switch,..., the nth active switch.

[0010] Optionally, the gear selection circuit includes a control input end and n control output ends;

[0011] The gating circuit includes n channels, where n is a positive integer greater than or equal to 3. The first channel includes a first active switch, a first resistor, and a first capacitor. The second channel includes a second active switch, a second resistor, and a second capacitor. The nth channel includes an nth active switch, an nth resistor, and an nth capacitor. The n control output terminals are respectively connected to the control terminals of the first active switch, ……, the nth active switch. Wherein, the first active switch is connected in series with the first resistor. One end of the first capacitor is connected to one end of the first resistor, the other end of the first capacitor is grounded, one end of the first resistor is connected to the output terminal of the compensation circuit, and the input terminal of the first active switch is connected to the input terminal of the compensation circuit. The second active switch is connected in series with the second resistor. One end of the second capacitor is connected to one end of the second resistor, the other end of the second capacitor is grounded, one end of the second resistor is further connected between the first resistor and the first active switch, and the input terminal of the second active switch is connected to the input terminal of the compensation circuit. The nth active switch is connected in series with the nth resistor. One end of the nth capacitor is connected to one end of the nth resistor, the other end of the nth capacitor is grounded, one end of the nth resistor is further connected between the (n - 1)th resistor and the (n - 1)th active switch, and the input terminal of the nth active switch is connected to the input terminal of the compensation circuit.

[0012] Optionally, the resistance values of the first resistor, the second resistor, ……, the nth resistor are equal; the capacitance values of the first capacitor, the second capacitor, ……, the nth capacitor are equal.

[0013] Optionally, the driving circuit further includes a feedback circuit. The feedback circuit includes a comparator and at least two feedback signal lines. At least one of the feedback signal lines is connected to the shortest fan-out trace, and at least one of the feedback signal lines is connected to the longest fan-out trace.

[0014] The comparator respectively receives the feedback signals on the feedback signal lines, compares them with the data signals of the fan-out traces connected to the feedback signals, and outputs a comparison result. The compensation circuit selects the gear of the compensation circuit according to the comparison result.

[0015] This application also discloses a driving method for a driving circuit. The driving circuit is the driving circuit of the display panel as described above. The driving method includes the steps:

[0016] Receiving a data signal;

[0017] Selecting the gear of the compensation circuit according to the gray level of the data signal or the scanning time during the progressive scanning of the display panel;

[0018] Compensating the data signal according to the gear of the compensation circuit and then outputting it to the corresponding data line.

[0019] Optionally, before receiving the data signal, the following steps are included:

[0020] After receiving the initial data signal, output it to the corresponding data line;

[0021] Receive feedback signals on at least two feedback signal lines, compare the data signals on the data lines connected to the feedback signals, and output the comparison result;

[0022] Set the initial gears of multiple compensation circuits according to the comparison result;

[0023] In the step of selecting the gear of the compensation circuit according to the gray scale of the data signal or the scanning time during the line-by-line scanning of the display panel, the following is included:

[0024] Select to increase or decrease the initial gear according to the gray scale of the data signal or the scanning time during the line-by-line scanning of the display panel.

[0025] The compensation circuit in this application has different gear selections. At different gears, its resistance value and capacitance value are different. In different gray scales or scanning times, different gears can be selected to match the fan-out wiring. First, in different panel designs, the fan-out wiring designs are also different. The compensation circuit of this application can have multiple resistance values or capacitance values to balance the impedance differences of the fan-out wiring. Therefore, in the face of different fan-out wiring designs, this application only needs to modify different gears to balance the impedance differences of the fan-out wiring. Second, due to the wiring design of the data line, on the same data line, the pixel charging path near the data driver is short and the impedance is low, while the pixel charging path far from the data driver is long and the impedance is high. Therefore, this application gradually increases or decreases the gear to configure a compensation circuit with a lower resistance value or capacitance value for the pixel with a high charging impedance far from the data driver, thereby balancing the charging differences caused by the charging paths on the same data line. Third, since the voltage values of the data signals corresponding to different gray scales are different, on the same data line, the display unevenness caused by different voltage values is not linearly related. Therefore, for the same data line, the resistance values of the compensation circuits required for different gray scales are also different. For this application, the compensation can also be achieved by adjusting the gear, so that the display is more uniform at different gray scales. The solution for setting the compensation circuit in this application is relatively lower in cost, and can compensate for the impedance unevenness of different pixels, different gray scales, and multiple data lines on the same data line, making the display effect of the display panel better. Description of the Drawings

[0026] The accompanying drawings included are used to provide a further understanding of the embodiments of the present application, which form a part of the specification, illustrate the implementation manners of the present application, and together with the written description, explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:

[0027] Figure 1 It is a schematic diagram of the fan-out wiring and data lines of a display panel of the present application;

[0028] Figure 2 It is a schematic diagram of the driving circuit of a display panel of the present application;

[0029] Figure 3 It is a schematic diagram of the compensation circuit of the first embodiment of the present application;

[0030] Figure 4 It is a schematic diagram of the compensation circuit of the second embodiment of the present application;

[0031] Figure 5 It is a schematic diagram of a feedback circuit of the present application;

[0032] Figure 6 It is a schematic diagram of the steps of the driving method of the driving circuit of the present application.

[0033] Among them, 100, driving circuit; 110, compensation circuit; 111, input terminal; 112, output terminal; 120, gear selection circuit; 121, control input terminal; K1 / K2 / Kn, control output terminal; 130, gating circuit; 131, channel; A1, first channel; A2, second channel; An, nth channel; 140, feedback signal line; 200, display panel; 210, data line; 220, fan-out wiring; 230, scan line; T1, first active switch; T2, second active switch; Tn, nth active switch; R1, first resistor; R2, second resistor; Rn, nth resistor; C1, first capacitor; C2, second capacitor; Cn, nth capacitor. Detailed implementation manners

[0034] It should be understood that the terms, the specific structures and functional details disclosed here are only for describing specific embodiments, which are representative. However, the present application can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments set forth herein.

[0035] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating relative importance or implicitly indicating the quantity of the indicated technical features. Thus, unless otherwise specified, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. Additionally, terms indicating orientation or positional relationships such as "upper", "lower", "left", "right", "vertical", "horizontal", etc. are described based on the orientation or relative positional relationship shown in the drawings, and are only for the convenience of simplifying the description of the present application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the present application. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0036] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0037] Figure 1 is a schematic diagram of the fan-out lines and data lines of a display panel of the present application. Refer to Figure 1 As shown, the display panel 200 includes scan lines 230 and data lines 210 located in the display area, and the extending directions of the scan lines 230 and the data lines 210 are different. A plurality of fan-out lines 220 are provided in the non-display area, and the extending direction of the fan-out lines 220 is the same as that of the data lines 210. The plurality of data lines 210 are connected to the plurality of fan-out lines 220 in a one-to-one correspondence. Generally speaking, fan-out lines 220 need to be provided for both the scan lines 230 and the data lines 210 to connect both the scan lines 230 and the data lines 210 to an external driving chip. Only for the GOA display panel 200, the scan lines 230 do not require fan-out lines 220. It can be understood that the solution of the fan-out lines 220 connected to the data lines 210 in the present application is equally applicable to the fan-out lines 220 connected to the scan lines 230.

[0038] Figure 2 is a schematic diagram of a driving circuit 100 of a display panel 200 of the present application. Refer to Figure 2 As shown, the driving circuit 100 includes: a plurality of compensation circuits 110 and a signal input unit (not shown). The compensation circuit 110 includes an input end 111 and an output end 112. The plurality of output ends 112 are respectively connected to the plurality of fan-out lines 220. At least two gears are provided in the compensation circuit 110. When the gear of the compensation circuit 110 increases, the capacitance value or resistance value of the compensation circuit 110 gradually decreases; the signal input unit outputs a data signal to the input ends of the plurality of compensation circuits 110; wherein, the compensation circuit 110 selects a gear according to the gray scale of the data signal or the scanning time when the display panel 200 scans line by line.

[0039] The signal input unit can be a timing controller. The system-on-chip (SOC) or the motherboard chip receives an external image signal and sends the image signal to the timing controller (TCON). The timing controller outputs the scanning signal and the data signal in the image signal to the scanning driver and the data driver respectively. The main improvement of the driving circuit 100 in this application lies in the data driver.

[0040] The compensation circuit 110 in this application has different gear selections. At different gears, its resistance value and capacitance value are different. In different gray levels or scanning times, different gears can be selected to match the fan-out wiring 220. First, in different panel designs, the designs of the fan-out wiring 220 are also different. The compensation circuit 110 in this application can have multiple resistance values or capacitance values to balance the impedance differences of the fan-out wiring 220. Therefore, in the face of different fan-out wiring 220 designs, this application only needs to modify different gears to balance the impedance differences of the fan-out wiring 220. Second, due to the wiring design of the data line 210, on the same data line 210, the pixel charging path near the data driver is short and the impedance is low, while the pixel charging path far from the data driver is long and the impedance is high. Therefore, this application gradually increases or decreases the gear to configure the compensation circuit 110 with a lower resistance value or capacitance value for the pixels with a high charging impedance far from the data driver, thereby balancing the charging differences caused by the charging paths on the same data line 210. Third, since the voltage values of the data signals corresponding to different gray levels are different, on the same data line 210, the display unevenness caused by different voltage values is not linearly related. Therefore, for the same data line 210, the resistance values of the compensation circuit 110 required for different gray levels are also different. For this application, the compensation at different gray levels can also be achieved by adjusting the gear, thereby making the display more uniform at different gray levels. The solution of setting the compensation circuit 110 in this application is relatively lower in cost, and can compensate for the impedance inequality of different pixels and different gray levels on the same data line 210, as well as the impedance inequality of multiple data lines 210, making the display effect of the display panel 200 better.

[0041] Among them, for the gray scale, on the same data line 210, when the gray scale of the data signal gradually decreases, the gear of the compensation circuit 110 gradually increases. For the same data line 210, as the gray scale increases, that is, in the process from 0 to 255, the uneven display brightness and the gray scale are not completely linearly related. For example, in each segment of the gray scale from 0 to 31, 31 to 63, 63 to 127, and 127 to 191, it is linearly correlated within the segment, but the linear coefficients between segments are different. Therefore, for different linear relationships, different gears of the compensation circuit 110 are required for compensation, so that the situation of uneven display will not occur. It can be understood that when the gray scale of the data signal is different, the coupling degree of the common line and the adjacent data lines 210 is also different, which also causes the brightness of adjacent pixels to be uneven. This application can also solve this problem.

[0042] Among them, during the scanning time of one frame of the display panel 200, in the direction of scanning line by line along the scanning line 230, the gear of the compensation circuit 110 on the same data line 210 gradually increases. In this embodiment, it is related to the length of the data line 210. On the same data line 210, the closer to the data driver, the shorter the line length and the smaller the load; the farther from the data driver, the longer the line length and the larger the load. Therefore, for the same data line 210, in the extending direction from the data driver to the data line 210, the load of the pixel gradually increases. For this embodiment, when the scanning line 230 scans line by line in the extending direction from the data driver to the data line 210, the gear of the compensation circuit 110 can be gradually increased during the line-by-line scanning process, so that the resistance value or capacitance value of the compensation circuit 110 gradually decreases, so that for different pixels on the same data line 210, the load is generally kept consistent, and the situation of uneven brightness caused by impedance unevenness on the same data line 210 is reduced.

[0043] It can be understood that the compensation circuits 110 set corresponding to different data lines 210 may be different. For example, the compensation circuit 110 configured for the data line 210 connected to the shorter fan-out wiring 220 can have more selectable gears, and the resistance value and capacitance value can be larger. The reason for selecting more gears is that generally speaking, the compensation circuit 110 increases the total load of the data line 210, so that the load between different data lines 210 is more balanced. However, for a single data line 210, it undoubtedly increases the load and causes more power consumption. Therefore, when the impedances of multiple data lines 210 are roughly balanced, this embodiment can reduce the impedance on a single data line 210 by increasing the gear. Furthermore, in the case where the impedances of multiple data lines 210 are roughly balanced but not exactly equal, the extreme situation of uneven display will not occur.

[0044] Therefore, for the present application, for multiple data lines 210, according to the impedance curve distribution of the fan-out routing 220, different compensation circuits 110 are provided for each data line 210, and each compensation circuit 110 has different gears. After setting the initial gears of each compensation circuit 110 according to the impedance curve of the fan-out routing 220, the gear is adjusted upward or downward during different gray levels or different scanning times to achieve fine adjustment of the display of the display panel 200 and improve the display effect of the display panel 200.

[0045] Figure 3 is a schematic diagram of the compensation circuit 110 according to the first embodiment of the present application. Refer to Figure 3 As shown, the compensation circuit 110 includes a gear selection circuit 120 and a gating circuit 130. The gating circuit 130 includes a plurality of channels 131. The resistance values or capacitance values of the plurality of channels 131 increase in sequence. The control end of each channel 131 is connected to the gear selection circuit 120. The gear selection circuit 120 controls the conduction of the plurality of channels 131, and only one of the channels 131 is conducted at the same time.

[0046] Specifically, the gear selection circuit 120 includes a control input terminal 121 and n control output terminals K1 / K2... / Kn; among them, the gear selection circuit 120 is a DAC digital-to-analog converter. The control input terminal 121 receives a control signal, and the control signal is a digital signal, which can control which control output terminal of the DAC digital-to-analog converter outputs, and further control which channel 131 of the gating circuit 130 is conducted.

[0047] Among them, each channel 131 is connected to an enhancement driving module Buffer, and the enhancement driving module Buffer is used to enhance the driving ability of the data signal, and is output to the fan-out routing 220 after passing through the enhancement driving module Buffer.

[0048] Specifically, the gating circuit 130 includes n channels 131, where n is a positive integer greater than or equal to 2. The first channel A1 includes a first active switch T1, a first resistor R1, and a first capacitor C1. The nth channel An includes an nth active switch Tn, an nth resistor Rn, and an nth capacitor Cn. One ends of the n channels 131 are respectively connected to the input end of the compensation circuit 110, and the other ends of the n channels 131 are respectively connected to the output end of the compensation circuit 110. Among them, the first active switch T1 is connected in series with the first resistor R1. One end of the first capacitor C1 is connected to one end of the first resistor R1, and the other end of the first capacitor C1 is grounded. The nth active switch Tn is connected in series with the nth resistor Rn. One end of the nth capacitor Cn is connected to one end of the nth resistor Rn, and the other end of the nth capacitor Cn is grounded. The n control output ends are respectively connected to the control ends of the first active switch T1, ……, the nth active switch Tn.

[0049] Each channel 131 is respectively provided with an active switch and a matching circuit of a group of capacitors and resistors. Among them, the matching circuit of the capacitors and resistors is mainly used to configure the corresponding fan-out wiring 220 to assist the fan-out wiring 220 to maintain a series or parallel manner.

[0050] Compared with the solution of compensating for the mura problem caused by the fan-out wiring 220 by completely using software settings or preset compensation tables in this embodiment, in this application, an equivalent resistor and an equivalent capacitor, that is, a compensation circuit 110, are directly provided inside the data driving circuit 100. Through the direct compensation of the equivalent resistor and the equivalent capacitor, it is more accurate. And it is not necessary to take pictures of the display screen of the display panel 200 through a pixel-level camera during the test to test the mura existing therein, and adjust the preset compensation table according to the mura phenomenon of the screen, and its accuracy completely depends on the photographing ability of the camera. In this application, during the test, the best display compensation can be found by means of step-by-step adjustment.

[0051] Figure 4 It is a schematic diagram of the compensation circuit 110 according to the second embodiment of the present application. Refer to Figure 4 As shown, the compensation circuit 110 includes a gear selection circuit 120 and a gating circuit 130. The gating circuit 130 includes a plurality of channels 131. The resistance values or capacitance values of the plurality of channels 131 increase in sequence. The control end of each channel 131 is connected to the gear selection circuit 120. The gear selection circuit 120 controls the conduction of the plurality of channels 131, and only one of the channels 131 is conducted at the same time. The gear selection circuit 120 includes a control input end 121 and n control output ends;

[0052] The gating circuit 130 includes n channels 131, where n is a positive integer greater than or equal to 3. The first channel A1 includes a first active switch T1, a first resistor R1, and a first capacitor C1. The second channel A2 includes a second active switch T2, a second resistor R2, and a second capacitor C2. The nth channel An includes an nth active switch Tn, an nth resistor Rn, and an nth capacitor Cn. The n control output terminals are respectively connected to the control terminals of the first active switch T1, ……, the nth active switch Tn. Among them, the first active switch T1 is connected in series with the first resistor R1. One end of the first capacitor C1 is connected to one end of the first resistor R1, and the other end of the first capacitor C1 is grounded. One end of the first resistor R1 is connected to the output terminal of the compensation circuit 110, and the input terminal of the first active switch T1 is connected to the input terminal of the compensation circuit 110. The second active switch T2 is connected in series with the second resistor R2. One end of the second capacitor C2 is connected to one end of the second resistor R2, and the other end of the second capacitor C2 is grounded. One end of the second resistor R2 is also connected between the first resistor R1 and the first active switch T1, and the input terminal of the second active switch T2 is connected to the input terminal of the compensation circuit 110. The nth active switch Tn is connected in series with the nth resistor Rn. One end of the nth capacitor Cn is connected to one end of the nth resistor Rn, and the other end of the nth capacitor Cn is grounded. One end of the nth resistor Rn is also connected between the (n - 1)th resistor and the (n - 1)th active switch, and the input terminal of the nth active switch Tn is connected to the input terminal of the compensation circuit 110.

[0053] What is different in this embodiment compared with the previous embodiment is that each channel 131 shares the design of the equivalent resistor and equivalent capacitor in the previous channel 131. Refer to Figure 4 As shown, only one end of the first resistor in the first channel A1 is connected to the output terminal of the compensation circuit 110, and the other channels 131 borrow the first resistor and then output. For example, in the third channel 131, the first resistor, the second resistor, and the third resistor are connected in series and then output. In the second channel A2, the first resistor and the second resistor are connected in series and then output. The circuit design of this embodiment makes the circuit more concise. On the one hand, it can reduce the number of resistor designs, and on the other hand, it can improve the utilization rate of the circuit.

[0054] Specifically, the resistance values of the first resistor, the second resistor, ……, the nth resistor are equal; the capacitance values of the first capacitor, the second capacitor, ……, the nth capacitor are equal. In this embodiment, resistors with the same resistance value or capacitors with the same capacitance value can be set. From the first channel A1 to the nth channel An, as the number of levels of the channel 131 increases, each channel 131 has the same additional resistor and capacitor compared to the previous channel 131. That is, as the number of levels increases, the equivalent resistance or equivalent capacitance of the channel 131 increases with the level, forming an arithmetic progression. In this embodiment, the resistance value of each resistor is the minimum difference for adjusting each gear position. When the resistance value is smaller, that is, the difference between different gear positions is smaller, the gear position accuracy is higher. When the resistance value is larger, the difference between different gear positions is larger, and the gear position adjustment range is larger.

[0055] It can be understood that in this embodiment, the solution combining the first resistor, the second resistor, ……, the nth resistor and the capacitor can replace the solution of only setting capacitors, or can be replaced by the solution of only setting resistors, which can be specifically selected according to the actual situation.

[0056] In this embodiment, the compensation circuit 110 is disposed on a Chip On Film (COF) or a Printed Circuit Board (PCB). In circuit design, it can be disposed in the data driver, and can also be disposed on the panel. However, for the solution designed on the panel, it is difficult to achieve narrow border display. Disposing it in the data driver not only does not affect the narrow border, but also it is easier to process and implement adding the compensation circuit 110 in the data driver, and the cost is lower.

[0057] It can be understood that the compensation circuits 110 in the above two embodiments can be used in combination.

[0058] Specifically, the number of the compensation circuits 110 is less than or equal to the number of the fan-out wirings 220; when the number of the compensation circuits 110 is less than the number of the fan-out wirings 220, at least two adjacent fan-out wirings 220 share one compensation circuit 110.

[0059] As the resolution of the display panel 200 increases, the number of its data lines 210 also increases significantly. For example, for a display panel 200 with a resolution of 1920*1080, the number of its data lines 210 is 1920. If a compensation circuit 110 is provided for each data line 210, it may require a higher-cost circuit design and the circuit complexity is also higher. Therefore, in an embodiment, when the number of compensation circuits 110 is selected to be less than the number of fan-out traces 220, the fan-out traces 220 corresponding to adjacent data lines 210 share a compensation circuit 110. When compensating in a shared manner, it can be controlled by a gear selection circuit 120 for multiple compensation circuits 110, or the same compensation circuit 110 is connected to multiple fan-out traces 220. The connection methods include parallel or series. In parallel, multiple fan-out traces 220 select the same gear for compensation. The series connection method is more complex and requires the combination of the compensation circuits 110 of the above two embodiments. For example, after the first channel A1 of the compensation circuit 110 in the first embodiment, a compensation circuit 110 of the second embodiment is added. In essence, it is the reuse of the compensation circuit 110 of the second embodiment. Figure 4 For example, three channels 131 are provided, and taking three channels 131 as a group, multiple groups are provided in a compensation circuit 110, and each group of channels 131 is respectively connected to multiple fan-out traces 220, thereby realizing the reuse method. Of course, in this embodiment, the number of the compensation circuits 110 may be equal to the number of data lines 210, thereby realizing more accurate adjustment.

[0060] Figure 5 is a schematic diagram of a feedback circuit of the present application. Refer to Figure 5 As shown, the driving circuit 100 further includes a feedback circuit. The feedback circuit includes a comparator and at least two feedback signal lines 140. At least one of the feedback signal lines 140 is connected to the shortest fan-out trace 220, and at least one of the feedback signal lines 140 is connected to the longest fan-out trace 220; the comparator is used to respectively receive the feedback signals on the feedback signal lines 140 and compare them with the data signals of the fan-out traces 220 connected to the feedback signals, and then output a comparison result. The compensation circuit 110 selects the gear of the compensation circuit 110 according to the comparison result. It can be understood that the feedback signal lines can be only arranged in the fan-out trace area or extended to the data lines. If it is for detecting the impedance non-uniformity of the fan-out trace area, it can be arranged in the fan-out traces. If it is for reducing the total length of the data lines and fan-out traces, it is extended to the data lines for setting.

[0061] In this embodiment, a feedback circuit is also designed. During the testing process, after initial data is input, the data driver outputs an initial data signal. The data driver receives a feedback signal and calculates the difference between the feedback signal of the shortest fan-out trace 220 and the initial data signal, as well as the difference between the feedback signal of the longest fan-out trace 220 and the initial data signal. Based on the differences between the two, the initial gear positions of each compensation circuit 110 are preliminarily adjusted.

[0062] After the testing is completed, when powering on after entering the preset initial gear position, the data driver outputs a target data signal and performs compensation at the preset initial gear position. The data driver receives the feedback signal again, and the comparator compares the difference between the target data signal and the feedback signal, and then controls the gear selector to increase or decrease the gear position of the compensation circuit 110 one by one.

[0063] Secondly, according to the difference change between the longest fan-out trace 220 and the shortest fan-out trace 220, generally it can be regarded as linear. For example, from left to right, the impedance decreases from the longest fan-out trace 220 to the shortest fan-out trace 220. From left to right, the impedance increases from the shortest fan-out trace 220 to the longest fan-out trace 220. Therefore, in this embodiment, by only calculating the impedance difference between the two endpoints, it can be used to detect the difference of the feedback signal, and more accurately realize the gear selection of the compensation circuit 110.

[0064] Figure 6 It is a schematic diagram of the steps of the driving method of the driving circuit of the present application. Refer to Figure 6 As shown, the present application discloses a driving method of a driving circuit, the driving circuit includes the driving circuit of the above display panel, and the driving method includes the steps:

[0065] S100: Receive a data signal;

[0066] S200: Select the gear position of the compensation circuit according to the gray level of the data signal or the scanning time when the display panel scans line by line;

[0067] S300: Output the compensated data signal to the corresponding data line according to the gear position of the compensation circuit.

[0068] The compensation circuit in the present application has different gear selections, and its resistance and capacitance are different at different gears. In different grayscales or scanning times, different gears can be selected to match the fan-out routing. First, in different panel designs, the designs of the fan-out routing are also different. The compensation circuit of the present application can have a variety of resistance values ​​or capacitance values ​​to balance the impedance differences of the fan-out routing. Therefore, in the face of different fan-out routing designs, the present application only needs to modify different gears to balance the impedance differences of the fan-out routing. Second, due to the wiring design of the data line, on the same data line, the pixel charging path close to the data driver is short and the impedance is low, while the pixel charging path far away from the data driver is long and the impedance is high. Therefore, the present application gradually increases or decreases the gear to realize the configuration of the pixel with high charging impedance far away from the data driver with a compensation circuit with a lower resistance value or capacitance value, thereby balancing the charging difference caused by the charging path on the same data line. Third, since the voltage values ​​of the data signals corresponding to different grayscales are different, on the same data line, the display unevenness caused by different voltage values ​​is not linearly related. Therefore, for the same data line, the resistance values ​​of the compensation circuits required for different grayscales are also different. For the present application, compensation at different grayscales can be achieved by adjusting the gear position, thereby making the display at different grayscales more uniform. The scheme of setting up the compensation circuit in the present application is relatively low in cost, and the impedance unevenness of multiple data lines can be compensated for different pixels and different grayscales of the same data line, so that the display effect of the display panel is better.

[0069] Moreover, the feedback signal in this embodiment can be used for automatic gear adjustment, specifically including:

[0070] The steps before S100 include:

[0071] S001: After receiving the initial data signal, output it to the corresponding data line;

[0072] S002: receiving feedback signals on at least two feedback signal lines and data signals on the data lines connected to the feedback signals, and outputting comparison results after comparison;

[0073] S003: setting initial gears of multiple compensation circuits according to the comparison results;

[0074] The steps of S200 include:

[0075] S201: Selecting to increase or decrease an initial gear according to the gray scale of a data signal or the scanning time when a display panel is scanned line by line.

[0076] In this embodiment, in addition to including the design of the initial gear position, it is also capable of selecting the gear position according to the gray scale of different data signals and the time when different rows are in the scanning period. The specific circuit is also provided with the above-mentioned feedback circuit, and the gear position is selected according to the feedback signal in terms of the gray scale of the same data signal and the time when different rows are in the scanning period.

[0077] For example: at the initial gear position, the data signal on the same data line changes from a low gray scale to a high gray scale, and the gear position is selected according to the difference information of the two feedback signals.

[0078] For example: at the initial gear position, when the data signal on the same data line is scanned row by row from the current row to the nth row, the gear position is selected according to the difference information of the two feedback signals of the data signal when the current row and the nth row are scanned.

[0079] Regarding the number of feedbacks of the feedback signal, considering the power consumption problem, this application is generally adjusted during testing. Generally speaking, during normal display, the feedback signal can be fed back multiple times within one frame.

[0080] It should be noted that the inventive concept of this application can form a very large number of embodiments. However, due to the limited space of the application documents, it is impossible to list them all. Therefore, on the premise of no conflict, the above-described embodiments or various technical features can be combined arbitrarily to form new embodiments. After the combination of each embodiment or technical feature, the original technical effect will be enhanced.

[0081] The above content is a further detailed description of this application in combination with specific optional implementation manners. It cannot be determined that the specific implementation of this application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, without departing from the concept of this application, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of this application.

Claims

1. A driving circuit for a display panel, the display panel including a plurality of data lines and a plurality of fan-out lines, the plurality of data lines being connected to the plurality of fan-out lines in a one-to-one correspondence. Characterized in that: The driving circuit includes: A plurality of compensation circuits, including an input end and an output end, the plurality of output ends being respectively connected to the plurality of fan-out lines, at least two gears being provided in the compensation circuit, and when the gear of the compensation circuit increases, the capacitance value or resistance value of the compensation circuit gradually decreases; and A signal input unit for outputting a data signal to the input ends of the plurality of compensation circuits; Wherein, the compensation circuit selects a gear according to the gray level of the data signal or the scanning time when the display panel scans line by line; The compensation circuit includes a gear selection circuit and a gating circuit, the gating circuit including a plurality of channels, the resistance values or capacitance values of the plurality of channels increasing in sequence, the control end of each channel being connected to the gear selection circuit, the gear selection circuit controlling the conduction of the plurality of channels, and only one of the channels being conductive at the same time; The gear selection circuit includes a control input end and n control output ends; The gating circuit includes n channels, n being a positive integer greater than or equal to 3, the first channel including a first active switch, a first resistor and a first capacitor, the second channel including a second active switch, a second resistor and a second capacitor, and the nth channel including an nth active switch, an nth resistor and an nth capacitor; The n control output ends are respectively connected to the control ends of the first active switch, ……, the nth active switch; Wherein, the first active switch is connected in series with the first resistor, one end of the first capacitor is connected to one end of the first resistor, the other end of the first capacitor is grounded, one end of the first resistor is connected to the output end of the compensation circuit, and the input end of the first active switch is connected to the input end of the compensation circuit; The second active switch is connected in series with the second resistor, one end of the second capacitor is connected to one end of the second resistor, the other end of the second capacitor is grounded, one end of the second resistor is further connected between the first resistor and the first active switch, and the input end of the second active switch is connected to the input end of the compensation circuit; The nth active switch is connected in series with the nth resistor, one end of the nth capacitor is connected to one end of the nth resistor, the other end of the nth capacitor is grounded, one end of the nth resistor is further connected between the (n - 1)th resistor and the (n - 1)th active switch, and the input end of the nth active switch is connected to the input end of the compensation circuit.

2. The driving circuit for a display panel according to claim 1, Characterized in that: On the same data line, when the gray level of the data signal gradually decreases, the gear of the compensation circuit gradually increases; Or within the scanning time of one frame of the display panel, in the direction of scanning line by line along the scanning lines, the gear of the compensation circuit on the same data line gradually increases.

3. The driving circuit for a display panel according to claim 1, Characterized in that: The number of the compensation circuits is less than or equal to the number of the fan-out lines; When the number of the compensation circuits is less than the number of the fan-out wirings, at least two adjacent ones of the fan-out wirings share one of the compensation circuits.

4. The driving circuit of the display panel according to claim 1, wherein, the resistance values of the first resistor, the second resistor, ……, the nth resistor are equal; the capacitance values of the first capacitor, the second capacitor, ……, the nth capacitor are equal.

5. The driving circuit of the display panel according to claim 1, wherein, the driving circuit further includes a feedback circuit, the feedback circuit includes a comparator and at least two feedback signal lines, at least one of the feedback signal lines is connected to the shortest one of the fan-out wirings, and at least one of the feedback signal lines is connected to the longest fan-out wiring; the comparator is configured to respectively receive the feedback signals on the feedback signal lines, compare with the data signals of the fan-out wirings connected to the feedback signals, and output a comparison result, and the compensation circuit selects the gear of the compensation circuit according to the comparison result.

6. A driving method of a driving circuit, wherein, the driving circuit is the driving circuit of the display panel according to any one of claims 1-5 above, and the driving method includes the steps of: receiving a data signal; selecting the gear of the compensation circuit according to the gray level of the data signal or the scanning time when the display panel scans line by line; compensating the data signal according to the gear of the compensation circuit and then outputting the compensated data signal to the corresponding data line.

7. The driving method of the driving circuit according to claim 6, wherein, before the step of receiving the data signal, the method includes the steps of: after receiving an initial data signal, outputting the initial data signal to the corresponding data line; receiving the feedback signals on at least two feedback signal lines, comparing with the data signals on the data lines connected to the feedback signals, and outputting a comparison result; setting the initial gears of a plurality of compensation circuits according to the comparison result; in the step of selecting the gear of the compensation circuit according to the gray level of the data signal or the scanning time when the display panel scans line by line, the step includes: selecting to increase or decrease the initial gear according to the gray level of the data signal or the scanning time when the display panel scans line by line.

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