Antifuse Memory Layout and Its Circuit, Antifuse Memory and Its Design Method

Abstract

An embodiment of the present disclosure provides an anti-fuse memory layout and its circuit, an anti-fuse memory and its design method. The anti-fuse memory layout includes: active regions that extend along a first direction and are discretely arranged along a second direction. Each active region includes at least two memory cell regions arranged along the first direction. Each memory cell region includes an anti-fuse region and a control region arranged along the first direction. In the first direction, the control regions of adjacent memory cell regions are adjacent to each other; a word line region that extends along the second direction and intersects with the control region; an electrical connection region that extends along the second direction and intersects with the anti-fuse region; a programming control region that extends along a third direction and is located on one side of the corresponding active region, and the programming control region intersects with the electrical connection regions arranged along the first direction. The embodiments of the present disclosure are at least beneficial to reducing the layout area of the anti-fuse memory layout.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor circuit design, and particularly to an anti-fuse memory layout and its circuit, an anti-fuse memory, and its design method. Background Art

[0002] An anti-fuse memory can be implemented through an anti-fuse memory cell array. The gate oxide medium of the anti-fuse memory cell will break down after applying a high voltage, and the impedance of the path decreases after breakdown; the information stored in the anti-fuse memory cell can be read by detecting the resistance state of the path after breakdown.

[0003] However, when programming a certain memory cell area by applying a high voltage, the high voltage will interfere with or damage adjacent memory cell areas. Moreover, during the data programming stage of the anti-fuse memory, the discharge transistor for discharging the transmission wire needs to discharge quickly. Therefore, the discharge transistor is usually designed as a transistor with a relatively thick gate dielectric layer, which is not conducive to reducing the layout area of the anti-fuse memory layout and is not conducive to reducing the size of the anti-fuse memory. Summary of the Invention

[0004] Embodiments of the present disclosure provide an anti-fuse memory layout and its circuit, an anti-fuse memory, and its design method, which are at least conducive to reducing the layout area of the anti-fuse memory layout.

[0005] According to some embodiments of the present disclosure, on the one hand, an anti-fuse memory layout is provided, including: an active region, the active region extends along a first direction and is discretely arranged along a second direction, each active region includes at least two memory cell regions arranged along the first direction, each memory cell region includes an anti-fuse region and a control region arranged along the first direction, in the first direction, the control regions of adjacent memory cells are adjacent to each other, the anti-fuse region is used to define an anti-fuse transistor, and the control region is used to define a control transistor; a word line region, the word line region extends along the second direction and intersects with the control region, the word line region is used to define a word line electrically connected to the gate of the control transistor; an electrical connection region, the electrical connection region extends along the second direction and intersects with the anti-fuse region, the electrical connection region is used to define an electrical connection layer electrically connected to the gate of the anti-fuse transistor; a programming control region, the programming control region extends along a third direction and is located on one side of the corresponding active region, and the programming control region intersects with the electrical connection regions arranged along the first direction, the programming control region is used to define a programming control layer, and the programming control layer is electrically connected to the electrical connection layers arranged along the first direction.

[0006] In some embodiments, the programming control region and the electrical connection region are on the same layer, and the programming control region is adjacent to the electrical connection region.

[0007] In some embodiments, the programming control region and the electrical connection region are in different layers, and the programming control region and the electrical connection region have an opposing region.

[0008] In some embodiments, the antifuse memory layout further includes: a via region, the via region being located in the opposing region between the programming control region and the electrical connection region, for defining a conductive pillar, and the conductive pillar electrically connecting the electrical connection layer and the programming control layer.

[0009] In some embodiments, the first direction is the same as the third direction.

[0010] In some embodiments, the first direction is perpendicular to the second direction.

[0011] In some embodiments, the active region is used to define an N-type active layer.

[0012] In some embodiments, the antifuse memory layout further includes: a bit line region, the bit line region extending along the first direction to define a bit line electrically connected to control transistors arranged along the first direction.

[0013] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides an antifuse memory, including: at least two memory cells arranged along a first direction and a second direction, each of the memory cells including an antifuse transistor and a control transistor arranged along the first direction, the gate structure of the antifuse transistor including a first gate dielectric layer and a first gate layer stacked, and the gate structure of the control transistor including a second gate dielectric layer and a second gate layer stacked; a word line layer extending along the second direction and electrically connected to the second gate layer of the control transistors arranged along the second direction; an electrical connection layer extending along the second direction and electrically connected to the first gate layer of the antifuse transistor; and a programming control layer extending along a third direction and electrically connected to the first gate layer arranged along the first direction through the electrical connection layer.

[0014] In some embodiments, the electrical connection layer and the programming control layer are in the same layer.

[0015] In some embodiments, the electrical connection layer and the programming control layer are in different layers; the antifuse memory further includes: a conductive pillar, the conductive pillar being located between the electrical connection layer and the programming control layer and electrically connecting the electrical connection layer and the programming control layer.

[0016] In some embodiments, the thickness of the first gate dielectric layer is less than or equal to 30 angstroms; the thickness of the second gate dielectric layer is less than or equal to 30 angstroms.

[0017] In some embodiments, the antifuse memory further includes: a bit line layer extending along the first direction, and the bit line layer is electrically connected to the control transistors arranged along the first direction.

[0018] According to some embodiments of the present disclosure, on the other hand, an antifuse memory design method is further provided for designing the antifuse memory described in any one of the above, including: defining the memory cell programmed in two adjacent memory cells along the first direction as the first memory cell, and the memory cell not programmed as the second memory cell, defining the node where the control transistor in the second memory cell is connected to the antifuse transistor as the connection node, and there is a first parasitic capacitance between the first gate layer and the connection node, and a second parasitic capacitance between the second gate layer and the connection node. Defining that during programming, there is a voltage difference threshold between the first gate layer and the connection node in the second memory cell, and the voltage difference threshold is the voltage difference between the first gate layer and the connection node corresponding to the breakdown of the antifuse transistor, and the voltage of the programming control layer corresponding to the first memory cell is the programming voltage; based on the programming voltage and the voltage difference threshold, obtaining the relationship between the first parasitic capacitance and the second parasitic capacitance; based on the relationship between the first parasitic capacitance and the second parasitic capacitance, designing the channel size and / or the thickness of the first gate dielectric layer of the antifuse transistor in the second memory cell, and designing the channel size and / or the thickness of the second gate dielectric layer of the control transistor in the second memory cell.

[0019] In some embodiments, the first parasitic capacitance, the second parasitic capacitance, the programming voltage, and the voltage difference threshold satisfy the following relationship: U = R1*U0 / (R1 + R2), where U is any value less than or equal to the voltage difference threshold, U0 is the programming voltage, R1 is the first capacitive reactance corresponding to the first parasitic capacitance, and R2 is the second capacitive reactance corresponding to the second parasitic capacitance.

[0020] According to some embodiments of the present disclosure, on the other hand, the present disclosure embodiments further provide an anti-fuse memory circuit, including: a plurality of memory cells, each of the memory cells including an anti-fuse transistor and a control transistor connected to each other, and a connection node of the anti-fuse transistor and the control transistor is defined as a reference node; bit lines, the bit lines are connected to the anti-fuse transistors arranged in a first direction, and each of the anti-fuse transistors is electrically connected to the bit line through the control transistor; word lines, the word lines are connected to gates of the control transistors arranged in a second direction, and are used to turn on the selected control transistors according to a row selection signal, so that the bit lines are electrically connected to the anti-fuse transistors; a programming control line, the programming control line is connected to gates of the anti-fuse transistors arranged in the first direction, and the anti-fuse transistors are used to be programmed according to a programming signal provided by the programming control line; wherein, there is a first parasitic capacitance between the gate of the anti-fuse transistor and the reference node, and there is a second parasitic capacitance between the gate of the control transistor and the reference node. During programming of the anti-fuse transistor of a selected memory cell, the reference nodes of adjacent anti-fuse transistors are coupled to a preset voltage, and a difference between the preset voltage and a voltage of the programming signal is less than or equal to a voltage difference threshold, and the voltage difference threshold is a voltage difference between the gate and the drain of the anti-fuse transistor corresponding to breakdown of the anti-fuse transistor.

[0021] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0022] In the above anti-fuse memory layout, the word line region extends along the second direction, and the programming control region extends along the third direction. The arrangement direction of the word line region is staggered with the arrangement direction of the programming control region, so that while the anti-fuse transistors in adjacent memory cell regions sharing the active region are electrically connected to the same programming control region, the control transistors in adjacent memory cell regions sharing the active region are electrically connected to different word line regions. In this way, when programming the anti-fuse transistors in a certain memory cell region among adjacent memory cell regions by using the programming control region, the control transistors in this memory cell region can be turned on by using the word line region electrically connected to this memory cell region, while the control transistors in another memory cell region sharing the active region with this memory cell region are electrically connected to another word line region, so the control transistors in another memory cell region sharing the active region with this memory cell region will not be turned on, and thus the anti-fuse transistors in another memory cell region sharing the active region with this memory cell region will not be programmed, avoiding interference or damage to adjacent memory cell regions when programming a certain memory cell region. In addition, to protect the memory cell regions adjacent to the memory cell region to be programmed, the anti-fuse memory layout provided by the embodiments of the present disclosure does not need to be provided with a pre-charge region. On the one hand, it is beneficial to reduce the layout area of the anti-fuse memory layout, thereby facilitating reducing the cost of the anti-fuse memory prepared according to the anti-fuse memory layout and reducing the size of the anti-fuse memory; on the other hand, when programming a certain memory cell region, there is no need to perform a pre-charge operation, which is beneficial to simplifying the operation timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0024] Figure 1 is a schematic circuit diagram of an anti-fuse memory circuit;

[0025] Figure 2 is for Figure 1 the corresponding layout structure diagram of the anti-fuse memory circuit;

[0026] Figures 3 to 6 is a schematic structural diagram of four anti-fuse memory layouts provided by an embodiment of the present disclosure;

[0027] Figure 7 is forFigure 6 Schematic cross-sectional structure diagram of an anti-fuse memory corresponding to the provided anti-fuse memory layout along the X direction;

[0028] Figure 8 and Figure 9 is Figure 6 Two schematic cross-sectional structure diagrams of an anti-fuse memory corresponding to the provided anti-fuse memory layout along the Y direction;

[0029] Figure 10 Schematic diagram of a partial circuit structure corresponding to an anti-fuse memory provided in another embodiment of the present disclosure. Detailed implementation manners

[0030] Figure 1 Schematic circuit structure diagram of an anti-fuse memory circuit; Figure 2 is for Figure 1 Corresponding layout structure diagram of an anti-fuse memory circuit.

[0031] Referring to Figure 1 , the anti-fuse memory circuit includes: a plurality of memory cells 10, each memory cell 10 includes an anti-fuse transistor 11 and a control transistor 12 connected thereto; a bit line BL, the bit line BL is connected to the anti-fuse transistors 11 arranged along the first direction X, and each anti-fuse transistor 11 is electrically connected to the bit line BL through the control transistor 12; a word line WL, the word line WL is connected to the gates of the control transistors 12 arranged along the second direction Y, and is used to turn on the selected control transistor 12 according to a row selection signal, so that the bit line BL is electrically connected to the anti-fuse transistor 11; a programming control line FsBln, the programming control line FsBln is connected to the gates of the anti-fuse transistors 11 arranged along the second direction Y, and the anti-fuse transistor 11 is used to perform programming according to the programming signal provided by the programming control line FsBln; a pre-charge circuit 13, which is used to set the bit line BL to a preset voltage, so that when the control transistor 12 connected to the bit line BL at the preset voltage is turned on, no high voltage will be generated between the gate and the drain of the anti-fuse transistor 11 in the same memory cell 10 as the turned-on control transistor 12, thereby obtaining protection.

[0032] Referring to Figure 2 , the anti-fuse memory layout may include: an active region 14, the active region 14 extends along the first direction X and is discretely arranged along the second direction Y, each active region 14 includes at least two memory cell regions 15 arranged along the first direction X, and each memory cell region 15 includes an anti-fuse transistor <11> and a control transistor <12>; a word line region 16, the word line region 16 extends along the second direction Y and is electrically connected to the control transistor <12>; a programming control region 17, the programming control region 17 also extends along the second direction Y and the programming control region 17 is electrically connected to the anti-fuse transistors <11> arranged along the second direction Y.

[0033] It is not difficult to find that in the anti-fuse array of the prior art, the programming control line FsBln and the word line WL extend in the same direction, that is, both are in the second direction Y. That is, there are at least two gate electrodes of the control transistors 12 in the adjacent memory cells 10 arranged along the second direction Y electrically connected to the same word line WL, and at least two gate electrodes of the anti-fuse transistors 11 are electrically connected to the same programming control line FsBln.

[0034] Thus, when programming an anti-fuse transistor 11 in an adjacent memory cell 10 arranged along the second direction Y, the programming control line FsBln electrically connected to the anti-fuse transistor 11 is set to a high voltage, such as 5V - 6V. The bit line BL electrically connected to the anti-fuse transistor 11 is pulled down to a low potential, and the word line WL electrically connected to the anti-fuse transistor 11 is set to a high level. At this time, the voltage difference between the gate and the drain of the anti-fuse transistor 11 will reach 5V - 6V, breaking down the gate dielectric layer of the anti-fuse transistor 11 to generate a low-resistance path. However, to protect another anti-fuse transistor 11 sharing the programming control line FsBln with this anti-fuse transistor 11, it is necessary to set the bit line BL electrically connected to the other anti-fuse transistor 11 to a preset voltage through the pre-charge circuit 13, so that the drain of the other anti-fuse transistor 11 is at the preset voltage, reducing the voltage difference between the gate and the drain of the other anti-fuse transistor 11 and avoiding breakdown of the other anti-fuse transistor 11, so as to achieve the purpose of protecting the memory cell 10 adjacent to the memory cell 10 to be programmed.

[0035] In addition, the control transistor 12 usually uses a transistor with a relatively thick gate dielectric layer, such as a transistor with a gate dielectric layer thickness of 60 angstroms. In this way, it is beneficial to make the gate voltage larger when the control transistor 12 is turned on, and then fully transmit the voltage of the pre-charge circuit to the drain of the anti-fuse transistor 11 to achieve protection of the anti-fuse transistor 11. The anti-fuse transistor 11 usually uses a transistor with a relatively thin gate dielectric layer, such as a transistor with a gate dielectric layer thickness of 30 angstroms, to ensure that when the control transistor 12 is turned on, the gate-drain voltage difference of the anti-fuse transistor 11 can break down the target gate dielectric layer to achieve programming. With the evolution of semiconductor manufacturing processes, there is an urgent hope to use transistors with relatively thin gate dielectric layers as the control transistors 12 to reduce the area of the anti-fuse unit and the manufacturing cost of the anti-fuse memory. However, based on the existing anti-fuse array, if the control transistor 12 uses a transistor with a relatively thin gate dielectric layer, when the control transistor 12 is turned on, the preset voltage provided by the pre-charge circuit 13 cannot be fully transmitted to the drain of the anti-fuse transistor 11, that is, the voltage difference between the gate and the drain of the anti-fuse transistor 11 cannot be effectively reduced, making it easy to damage the memory cell 10 adjacent to a certain memory cell 10 during programming.

[0036] The present disclosure provides an anti-fuse memory layout and its circuit, an anti-fuse memory and its design method. In the anti-fuse memory layout, when programming the anti-fuse transistors in a certain memory cell area using the programming control area, it will not program another memory cell area sharing the active area with this memory cell area, which helps to avoid interference or damage to the adjacent memory cell area when programming a certain memory cell area. In addition, to protect the memory cell area adjacent to the memory cell area that needs to be programmed, the anti-fuse memory layout provided by the embodiments of the present disclosure does not require a pre-charge area. On the one hand, it helps to reduce the layout area of the anti-fuse memory layout, which is beneficial to reducing the cost of the anti-fuse memory prepared according to the anti-fuse memory layout and reducing the size of the anti-fuse memory. On the other hand, when programming a certain memory cell area, there is no need for a pre-charge operation, which is beneficial to simplifying the operation timing.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present disclosure can still be implemented.

[0038] An embodiment of the present disclosure provides an anti-fuse memory layout. The following will detail the anti-fuse memory layout provided by an embodiment of the present disclosure with reference to the accompanying drawings. Figures 3 to 6 It is a schematic structural diagram of four anti-fuse memory layouts provided by an embodiment of the present disclosure.

[0039] Refer to Figure 3 and Figure 4, the antifuse memory layout includes: an active region 100, the active regions 100 extend along a first direction X and are arranged separately along a second direction Y. Each active region 100 includes at least two memory cell regions 101 arranged along the first direction X. Each memory cell region 101 includes an antifuse region 111 and a control region 121 arranged along the first direction X. In the first direction X, the control regions 121 of adjacent memory cell regions 101 are adjacent to each other. The antifuse region 111 is used to define an antifuse transistor <131>, and the control region 121 is used to define a control transistor <141>; a word line region 102, the word line region 102 extends along the second direction Y and intersects with the control region 121. The word line region 102 is used to define a word line electrically connected to the gate of the control transistor <141>; an electrical connection region 103, the electrical connection region 103 extends along the second direction Y and intersects with the antifuse region 111. The electrical connection region 103 is used to define an electrical connection layer electrically connected to the gate of the antifuse transistor <131>; a programming control region 104, the programming control region 104 extends along a third direction Z and is located on one side of the corresponding active region 100, and the programming control region 104 intersects with the electrical connection regions 103 arranged along the first direction X. The programming control region 104 is used to define a programming control layer, and the programming control layer is electrically connected to the electrical connection layers arranged along the first direction X.

[0040] In this way, the extending direction of the word line region 102 is different from that of the programming control region 104, which is beneficial to electrically connecting the antifuse transistors <131> in adjacent memory cell regions 101 sharing the active region 100 to the same programming control region 104, while electrically connecting the control transistors <141> in adjacent memory cell regions 101 sharing the active region 100 to different word line regions 102. When programming the antifuse transistor <131> in a certain memory cell region 101 by using the programming control region 104 and turning on the control transistor <141> by using the word line region 102 electrically connected to the control transistor <141> in this memory cell region 101, the control transistor <141> in another memory cell region 101 sharing the programming control region 104 is electrically connected to another word line region 102, then the control transistor <141> in another memory cell region 101 sharing the programming control region 104 will not be turned on, and thus will not program the antifuse transistor <131> in the same memory cell region 101 as this non-conductive control transistor <141>, avoiding interference or damage to the adjacent memory cell region 101 when programming a certain memory cell region 101.

[0041] In addition, to protect the memory cell region 101 adjacent to the memory cell region 101 to be programmed, the anti-fuse memory layout provided by the embodiments of the present disclosure does not need to be provided with a pre-charge region. On the one hand, it is beneficial to reduce the area of the anti-fuse memory layout, thereby helping to reduce the cost of manufacturing the anti-fuse memory. On the other hand, when programming a certain memory cell region 101, there is no need for a pre-charge operation, which is beneficial to simplifying the operation timing.

[0042] In some embodiments, the programming control region 104 and the electrical connection region 103 are on the same layer, and the programming control region 104 is adjacent to the electrical connection region 103. In this way, it is beneficial to reduce the overall thickness of the anti-fuse memory prepared according to the anti-fuse memory layout.

[0043] In some embodiments, the programming control region 104 and the electrical connection region 103 are on different layers, and the programming control region 104 and the electrical connection region 103 have an alignment region, that is, the positive projection of the programming control region 104 on the active region 100 and the positive projection of the electrical connection region 103 on the active region 100 at least partially overlap.

[0044] In some embodiments, if the programming control region 104 and the electrical connection region 103 are on different layers, the anti-fuse memory layout may further include: a via region (not shown in the figure), the via region is located in the alignment region of the programming control region 104 and the electrical connection region 103, and is used to define a conductive pillar, and the conductive pillar electrically connects the electrical connection layer and the programming control layer.

[0045] It should be noted that in practical applications, the programming control region 104 and the electrical connection region 103 may not have an alignment region. Limited by the conductive materials of the programming control region 104 and the electrical connection region 103 themselves, the contact resistance of the direct contact between the programming control region 104 and the electrical connection region 103 will be relatively large. Therefore, a transition material is used for transition, that is, the electrical connection method between the programming control region 104 and the electrical connection region 103 is: programming control region 104 - transition material - conductive pillar - transition material - electrical connection region 103, so as to improve the transmission efficiency of electrical signals between the programming control region 104 and the electrical connection region 103.

[0046] In any of the above embodiments, referring to Figure 4 , the first direction X may be the same as the third direction Z (referring to Figure 3 ). In this way, it is beneficial to make the arrangement between the regions in the anti-fuse memory layout more compact and regular, and is beneficial to further reducing the total layout area of the anti-fuse memory layout. In other embodiments, there may also be an included angle between the first direction and the third direction.

[0047] In any of the above embodiments, referring to Figure 3 or Figure 4, the first direction X is perpendicular to the second direction Y. Thus, it is also beneficial to make the arrangement between each area in the anti-fuse memory layout more compact and regular, thereby further reducing the total layout area of the anti-fuse memory layout. In other embodiments, the included angle between the first direction and the second direction may also not be 90°.

[0048] In any of the above embodiments, the active region 100 can be used to define an N-type active layer. In other embodiments, the active region 100 can also be used to define a P-type active layer.

[0049] In some embodiments, referring to Figure 5 or Figure 6 , the anti-fuse memory layout may further include: a bit line region 105, which extends along the first direction X to define a bit line electrically connected to the control transistor <141> arranged along the first direction X.

[0050] Among them, in some examples, referring to Figure 5 , the bit line region 105 can be located on one side of the corresponding active region 100, that is, there is no facing region between the bit line region 105 and the active region 100. The anti-fuse memory layout further includes: a conductive region 115, which is used to define a conductive layer for electrically connecting the drain or source of the control transistor <141> and the bit line; an electrical connection post, which is located between the conductive region 115 and the bit line region 105 and is used to electrically connect the conductive layer and the bit line. In another example, referring to Figure 6 , the bit line region 105 can be located directly above the corresponding active region 100, that is, there is a facing region between the bit line region 105 and the active region 100. The anti-fuse memory layout further includes: an electrical connection post 125, which is located between the active region 100 and the bit line region 105 and is used to electrically connect the active layer defined by the active region 100 and the bit line.

[0051] It should be noted that in practical applications, when electrically connecting the active layer and the bit line, in addition to using the electrical connection post 125, a transition material can also be used for transition, that is, the electrical connection method between the active layer and the bit line is: active layer - transition material - electrical connection post 125 - transition material - bit line, so as to improve the transmission efficiency of electrical signals between the active layer and the bit line.

[0052] In summary, in the antifuse memory layout, when programming the antifuse transistor <131> in a certain memory cell region 101 using the programming control region 104, the other memory cell region 101 sharing the programming control region 104 with this memory cell region 101 will not be programmed, which helps to avoid interference or damage to the adjacent memory cell region 101 when programming a certain memory cell region 101. In addition, to protect the memory cell region 101 adjacent to the memory cell region 101 that needs to be programmed, the antifuse memory layout provided by the embodiments of the present disclosure does not need to set a precharge region. On the one hand, it helps to reduce the layout area of the antifuse memory layout, thereby helping to reduce the cost of manufacturing the antifuse memory based on the antifuse memory layout and reducing the size of the antifuse memory; on the other hand, when programming a certain memory cell region 101, there is no need to perform a precharge operation, which helps to simplify the operation timing.

[0053] Another embodiment of the present disclosure provides an antifuse memory, and the antifuse memory provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 7 For Figure 6 the schematic cross-sectional structure diagram of the antifuse memory corresponding to the provided antifuse memory layout along the X direction, Figure 8 and Figure 9 For Figure 6 the two schematic cross-sectional structure diagrams of the antifuse memory corresponding to the provided antifuse memory layout along the Y direction.

[0054] With reference to Figures 7 to 9 , the antifuse memory includes: at least two memory cells 106 arranged along the first direction X and the second direction Y. Each memory cell 106 includes an antifuse transistor 131 and a control transistor 141 arranged along the first direction X. The gate structure of the antifuse transistor 131 includes a first gate dielectric layer 151 and a first gate layer 161 stacked. The gate structure of the control transistor 141 includes a second gate dielectric layer 171 and a second gate layer 181 stacked; a word line layer 107, the word line layer 107 extends along the second direction Y and is electrically connected to the second gate layer 181 of the control transistor 141 arranged along the second direction Y; an electrical connection layer 108, the electrical connection layer 108 extends along the second direction Y and is electrically connected to the first gate layer 161 of the antifuse transistor 131; a programming control layer 109, the programming control layer 109 extends along the third direction Z (reference Figure 1 ), and is electrically connected to the first gate layer 161 arranged along the first direction X through the electrical connection layer 108.

[0055] In this way, the extending direction of the word line layer 107 is different from that of the programming control layer 109, which is beneficial to electrically connecting the first gate layer 161 arranged along the first direction X to the same programming control layer 109 while enabling the control transistors 141 in the adjacent memory cells 106 sharing the programming control layer 109 to be electrically connected to different word line layers 107. When programming the anti-fuse transistor <31 in a certain memory cell 106 by using the programming control layer 109 and turning on the control transistor 141 by using the word line layer 107 electrically connected to the control transistor 141 in this memory cell 106, if the control transistor 141 in another memory cell 106 sharing the programming control layer 109 is electrically connected to another word line layer 107, the control transistor 141 in the other memory cell 106 sharing the programming control layer 109 will not be turned on, and thus the anti-fuse transistor 131 in the same memory cell 106 as this non-conductive control transistor 141 will not be programmed, avoiding interference or damage to the adjacent memory cell 106 when programming a certain memory cell 106.

[0056] In addition, to protect the memory cells 106 adjacent to the memory cell 106 to be programmed, the anti-fuse memory provided by the embodiments of the present disclosure does not need to be provided with a pre-charge module. On the one hand, it is beneficial to reduce the overall size of the anti-fuse memory, thereby facilitating the reduction of the cost of manufacturing the anti-fuse memory; on the other hand, when programming a certain memory cell 106, there is no need for a pre-charge operation, which is beneficial to simplifying the operation timing.

[0057] In some embodiments, referring to Figure 8 , the electrical connection layer 108 and the programming control layer 109 can be on the same layer. In this way, it is beneficial to reduce the overall thickness of the anti-fuse memory and improve the integration density of each functional film layer in the anti-fuse memory.

[0058] In some embodiments, referring to Figure 9 , the electrical connection layer 108 and the programming control layer 109 are on different layers; the anti-fuse memory may further include: a conductive pillar 119, the conductive pillar 119 is located between the electrical connection layer 108 and the programming control layer 109, and electrically connects the electrical connection layer 108 and the programming control layer 109.

[0059] It should be noted that in practical applications, limited by the conductive materials of the electrical connection layer 108 and the programming control layer 109 themselves, when electrically connecting the electrical connection layer 108 and the programming control layer 109, in addition to using the conductive pillar 119, a transition material can also be used for transition, that is, the electrical connection mode between the electrical connection layer 108 and the programming control layer 109 is: electrical connection layer 108 - transition material - conductive pillar 119 - transition material - programming control layer 109, so as to improve the transmission efficiency of electrical signals between the electrical connection layer 108 and the programming control layer 109.

[0060] In some embodiments, the thickness of the first gate dielectric layer 151 is less than or equal to 30 angstroms; the thickness of the second gate dielectric layer 171 is less than or equal to 30 angstroms. In the anti-fuse memory provided by the embodiments of the present disclosure, there is no need for a pre-charge module to protect the memory cells 106 adjacent to the memory cell 106 to be programmed. Therefore, when the control transistor 141 uses a transistor with a thinner gate dielectric layer, it will not affect the anti-fuse transistor 131 in the same memory cell 106 as the control transistor 141. Thus, for any memory cell 106, both the control transistor 141 and the anti-fuse transistor 131 therein can use transistors with a thinner gate dielectric layer, which is beneficial to further reducing the overall size of the anti-fuse memory to meet the requirements of high integration density of the anti-fuse memory.

[0061] In some embodiments, continuing to refer to Figure 7 , the anti-fuse memory may further include: a bit line layer 129, the bit line layer 129 extends along the first direction X, and the bit line layer 129 is electrically connected to the control transistors 141 arranged along the first direction X.

[0062] Wherein, the anti-fuse memory may further include: an electrical connection post 139, the electrical connection post 139 is located between the bit line layer 129 and the control transistor 141, and electrically connects the bit line layer 129 and the control transistor 141. It should be noted that in practical applications, when the bit line layer 129 and the control transistor 141 are electrically connected, in addition to using the electrical connection post 139, a transition material can also be used for transition, that is, the electrical connection method between the bit line layer 129 and the control transistor 141 is: bit line layer 129 - transition material - electrical connection post 139 - transition material - control transistor 141, so as to improve the transmission efficiency of electrical signals between the bit line layer 129 and the control transistor 141.

[0063] In summary, when programming the anti-fuse transistor 131 in a certain memory cell 106 by using the programming control layer 109, it will not program another memory cell 106 sharing the programming control layer 109 with the memory cell 106, which is beneficial to avoiding interference or damage to the adjacent memory cell 106 when programming a certain memory cell 106. In addition, to protect the memory cells 106 adjacent to the memory cell 106 to be programmed, the anti-fuse memory provided by the embodiments of the present disclosure does not need to be provided with a pre-charge module. On the one hand, it is beneficial to reduce the overall size of the anti-fuse memory, thereby reducing the manufacturing cost of the anti-fuse memory; on the other hand, when programming a certain memory cell 106, there is no need for a pre-charge operation, which is beneficial to simplifying the operation timing.

[0064] Another embodiment of the present disclosure provides a design method for an antifuse memory, which is used to design the antifuse memory provided in the foregoing embodiment. The following will be combined with Figures 6 to 10 to describe in detail the design method for the antifuse memory provided in another embodiment of the present disclosure. Figure 10 It is a schematic diagram of a partial circuit structure corresponding to the antifuse memory provided in another embodiment of the present disclosure.

[0065] Referring to Figures 6 to 10 , the design method of the antifuse memory includes the following steps: Define the memory cell 106 to be programmed among two adjacent memory cells 106 along the first direction X as the first memory cell, and the memory cell 106 not programmed as the second memory cell. The node where the control transistor 141 in the second memory cell is connected to the antifuse transistor 131 is defined as the connection node 149. There is a first parasitic capacitance 159 between the first gate layer 161 and the connection node 149, and a second parasitic capacitance 169 between the second gate layer 181 and the connection node 149. Define that during programming, there is a first voltage difference threshold between the first gate layer 161 and the connection node 149 in the second memory cell. The first voltage difference threshold is the voltage difference between the first gate layer 161 and the connection node 149 corresponding to the breakdown of the antifuse transistor 131. The voltage of the programming control layer 109 corresponding to the first memory cell is the programming voltage.

[0066] Based on the programming voltage and the first voltage difference threshold, obtain the relationship between the first parasitic capacitance 159 and the second parasitic capacitance 169; based on the relationship between the first parasitic capacitance 159 and the second parasitic capacitance 169, design the channel size and / or the thickness of the first gate dielectric layer 151 of the antifuse transistor 131 in the second memory cell, and design the channel size and / or the thickness of the second gate dielectric layer 171 of the control transistor 141 in the second memory cell.

[0067] It should be noted that if the voltage difference between the first gate layer 161 and the connection node 149 of the antifuse transistor 131 is less than or equal to the first voltage difference threshold, the first gate dielectric layer 151 of the antifuse transistor 131 will not be broken down. In this way, based on the preset programming voltage and the preset first voltage difference threshold, through the coupling effect of the first parasitic capacitance 159 and the second parasitic capacitance 169 in the memory cell 106 that does not need to be programmed, the voltage at the connection node 149 is relatively high, that is, the voltage at the drain of the antifuse transistor 131 in the memory cell 106 that does not need to be programmed is relatively high, so as to achieve that the voltage difference between the first gate layer 161 and the connection node 149 in the memory cell 106 that does not need to be programmed is less than or equal to the first voltage difference threshold, and when programming a certain antifuse transistor 131, other adjacent antifuse transistors 131 will not be broken down.

[0068] In addition, during programming, a second voltage difference threshold is defined between the second gate layer 181 and the connection node 149 in the second storage unit. The second voltage difference threshold is the voltage difference between the second gate layer 181 and the connection node 149 corresponding to the breakdown of the control transistor 141. The magnitudes of the first parasitic capacitance 159 and the second parasitic capacitance 169 can be designed according to the preset programming voltage, the preset first voltage difference threshold, and the second voltage difference threshold. Further, based on the magnitudes of the first parasitic capacitance 159 and the second parasitic capacitance 169, the channel size of the antifuse transistor 131 and / or the thickness of the first gate dielectric layer 151 are designed, and the channel size of the control transistor 141 and / or the thickness of the second gate dielectric layer 171 are designed.

[0069] In some embodiments, the first parasitic capacitance 159, the second parasitic capacitance 169, the programming voltage, and the voltage difference threshold satisfy the following relationship: U = R1 * U0 / (R1 + R2); where U is any value less than or equal to the voltage difference threshold, U0 is the programming voltage, R1 is the first capacitive reactance corresponding to the first parasitic capacitance 159, and R2 is the second capacitive reactance corresponding to the second parasitic capacitance 169.

[0070] It should be noted that when the control transistor 141 in the first storage unit is turned on because the bit line WL connected thereto is set to the turn-on voltage, so that the voltage at the node where the control transistor 141 in the first storage unit is connected to the antifuse transistor 131 is at a low potential, and thus when the first gate layer 161 in the antifuse transistor 131 in the first storage unit receives the programming voltage and is turned on, the first gate layer 161 in the antifuse transistor 131 in the second storage unit is also set to the programming voltage. However, the control transistor 141 in the second storage unit will not be turned on because the bit line WL connected thereto is set to the cut-off potential. Therefore, the voltage difference between the first gate layer 161 and the second gate layer 181 of the control transistor 141 in the antifuse transistor 131 in the second storage unit is equivalent to the absolute value of the difference between the programming voltage and the cut-off voltage. The first capacitive reactance corresponding to the first parasitic capacitance 159 and the second capacitive reactance corresponding to the second parasitic capacitance 169 in the second storage unit are in series, jointly bearing the above absolute value of the difference. That is, the voltage difference across the first capacitive reactance is the voltage difference between the first gate layer 161 and the connection node 149 in the antifuse transistor 131 in the second storage unit, the voltage difference across the second capacitive reactance is the voltage difference between the second gate layer 181 and the connection node 149 of the control transistor 141 in the second storage unit, and the sum of the voltage differences across the first capacitive reactance and the second capacitive reactance is the above absolute value of the difference. Therefore, the first parasitic capacitance 159, the second parasitic capacitance 169, the programming voltage, and the voltage difference threshold satisfy the above relationship.

[0071] Thus, under the conditions of a preset programming voltage and a preset differential voltage threshold, it is beneficial to ensure that after the parasitic capacitance coupling between the antifuse transistor 131 and the control transistor 141 in the memory cell 106 that does not require programming, the programming voltage applied to the gate of the antifuse transistor 131 will not cause the first gate dielectric layer 151 of the antifuse transistor 131 to break down.

[0072] It should be noted that when the above active region is defined as an N-type active region, the turn-on voltage of the control transistor 141 is a high level and the cut-off voltage is a low level. During programming, the programming voltage can be a high level, the corresponding bit line voltage can be a low level, the turn-on voltage is much smaller than the programming voltage, and the absolute value of the above differential voltage is close to or equal to the programming voltage; when the above active region is defined as a P-type active region, the turn-on voltage of the control transistor 141 is a low level and the cut-off voltage is a high level. During programming, the programming voltage can be a high level, the corresponding bit line voltage can be a low level. Compared with the N-type active region, the absolute value of the above differential voltage becomes smaller.

[0073] In addition, in practical applications, the first capacitive reactance can also be obtained according to the channel size of the antifuse transistor 131 and the thickness of the first gate dielectric layer 151, the second capacitive reactance can be obtained according to the channel size of the control transistor 141 and the thickness of the second gate dielectric layer 171, and then the programming voltage and the differential voltage threshold are designed based on the first capacitive reactance and the second capacitive reactance, so that the differential voltage between the first gate layer 161 and the connection node 149 in the memory cell 106 that does not require programming is less than or equal to the differential voltage threshold, and when programming a certain antifuse transistor 131, other adjacent antifuse transistors 131 will not be broken down.

[0074] In summary, using the above design method of the antifuse memory is beneficial for designers to design the sizes of the control transistor 141 and the antifuse transistor 131 according to needs, improving the diversity of the designed antifuse memory. In some embodiments, both the control transistor 141 and the antifuse transistor 131 can use transistors with a relatively thin gate dielectric layer thickness, which is beneficial for further reducing the overall size of the antifuse memory to meet the requirements of high integration density of the antifuse memory.

[0075] Another embodiment of the present disclosure provides an antifuse memory circuit, which will be described in detail below in combination with Figures 6 to 10 The antifuse memory circuit provided by another embodiment of the present disclosure will be described in detail.

[0076] Refer to Figure 9, the antifuse memory circuit includes: a plurality of memory cells 106, each memory cell 106 includes an antifuse transistor 131 and a control transistor 141 connected in series, and the connection node 149 between the antifuse transistor 131 and the control transistor 141 is defined as a reference node; a bit line BL, the bit line BL is connected to the antifuse transistors 131 arranged along the first direction X, and each antifuse transistor 131 is electrically connected to the bit line BL through the control transistor 141; a word line WL, the word line WL is connected to the gates of the control transistors 141 arranged along the second direction Y, and is used to turn on the selected control transistor 141 according to the row selection signal, so that the bit line BL is electrically connected to the antifuse transistor 131; a programming control line FsBln, the programming control line FsBln is connected to the gates of the antifuse transistors 131 arranged along the first direction X, and the antifuse transistor 131 is used to perform programming according to the programming signal provided by the programming control line FsBln.

[0077] Wherein, there is a first parasitic capacitance 159 between the gate of the antifuse transistor 131 and the reference node, and a second parasitic capacitance 169 between the gate of the control transistor 141 and the reference node. During the programming of the antifuse transistor 131 of a selected memory cell 106, the reference nodes of adjacent antifuse transistors 131 are coupled to a preset voltage, and the difference between the preset voltage and the voltage of the programming signal is less than or equal to a voltage difference threshold, and the voltage difference threshold is the voltage difference between the gate and the drain corresponding to the breakdown of the antifuse transistor 131.

[0078] In some embodiments, when programming the antifuse transistor 131 in a certain memory cell 106, a high voltage, such as 5V - 6V, is applied to the programming control line FsBln. At this time, the bit line BL electrically connected to the antifuse transistor 131 to be programmed is pulled down to a low potential, and a voltage of 1.2V is applied to the word line WL electrically connected to the control transistor 141 in the memory cell 106 to be programmed, so that the control transistor 141 is turned on, and the drain of the antifuse transistor 131 to be programmed is at a low potential. Then, the voltage difference between the first gate layer 161 and the drain of the antifuse transistor 131 to be programmed is greater than the voltage difference threshold, and the antifuse transistor 131 to be programmed is turned on. In another memory cell 106 sharing the programming control line FsBln with the antifuse transistor 131 to be programmed, since the word line WL electrically connected to the control transistor 141 in the memory cell 106 is at a low potential, and due to the parasitic capacitance coupling between the antifuse transistor 131 and the control transistor 141 in the memory cell 106, the potential at the connection node 149 can reach 3V, so that the voltage difference between the first gate layer 161 of the antifuse transistor 131 not to be programmed and the connection node 149 is less than the voltage difference threshold, thereby protecting the antifuse transistor 131.

[0079] In addition, to protect the anti-fuse transistor 131 adjacent to the anti-fuse transistor 131 to be programmed, the anti-fuse memory circuit provided by the embodiments of the present disclosure does not need to be provided with a pre-charge circuit. On the one hand, it is beneficial to reduce the layout area of the anti-fuse memory circuit, thereby facilitating the reduction of the manufacturing cost of the anti-fuse memory circuit; on the other hand, when programming a certain anti-fuse transistor 131, there is no need to perform a pre-charge operation, which is beneficial to simplifying the operation timing.

[0080] Those of ordinary skill in the art can understand that the above-described embodiments are specific embodiments for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. An anti-fuse memory layout, characterized in that, it includes: Active regions, the active regions extend along a first direction and are discretely arranged along a second direction. Each active region includes at least two memory cell regions arranged along the first direction. Each memory cell region includes an anti-fuse region and a control region arranged along the first direction. In the first direction, the control regions of adjacent memory cells are adjacent to each other. The anti-fuse region is used to define an anti-fuse transistor, and the control region is used to define a control transistor; Word line regions, the word line regions extend along the second direction and intersect with the control regions. The word line regions are used to define word lines electrically connected to the gates of the control transistors; Electrical connection regions, the electrical connection regions extend along the second direction and intersect with the anti-fuse regions. The electrical connection regions are used to define electrical connection layers electrically connected to the gates of the anti-fuse transistors; Programming control regions, the programming control regions extend along a third direction and are located on one side of the corresponding active regions. The programming control regions intersect with the electrical connection regions arranged along the first direction. The programming control regions are used to define programming control layers, and the programming control layers are electrically connected to the electrical connection layers arranged along the first direction.

2. The anti-fuse memory layout according to claim 1, characterized in that, the programming control region and the electrical connection region are on the same layer, and the programming control region is adjacent to the electrical connection region.

3. The anti-fuse memory layout according to claim 1, characterized in that, the programming control region and the electrical connection region are on different layers, and the programming control region and the electrical connection region have a facing region.

4. The anti-fuse memory layout according to claim 3, characterized in that, the anti-fuse memory layout further includes: Via regions, the via regions are located in the facing regions of the programming control regions and the electrical connection regions, and are used to define conductive pillars. The conductive pillars electrically connect the electrical connection layers and the programming control layers.

5. The anti-fuse memory layout according to any one of claims 1-4, characterized in that, the first direction is the same as the third direction.

6. The anti-fuse memory layout according to any one of claims 1-4, characterized in that, the first direction is perpendicular to the second direction.

7. The anti-fuse memory layout according to any one of claims 1-4, characterized in that, the active regions are used to define N-type active layers.

8. The anti-fuse memory layout according to any one of claims 1-4, characterized in that, it further includes: Bit line regions, the bit line regions extend along the first direction to define bit lines electrically connected to the control transistors arranged along the first direction.

9. An anti-fuse memory, characterized in that, it includes: At least two memory cells arranged along a first direction and a second direction. Each memory cell includes an anti-fuse transistor and a control transistor arranged along the first direction. The gate structure of the anti-fuse transistor includes a first gate dielectric layer and a first gate layer stacked, and the gate structure of the control transistor includes a second gate dielectric layer and a second gate layer stacked; A word line layer, the word line layer extending along the second direction and being electrically connected to the first gate layer of the control transistors arranged along the second direction; An electrical connection layer, the electrical connection layer extending along the second direction and being electrically connected to the second gate layer of the antifuse transistors; A programming control layer, the programming control layer extending along a third direction and being electrically connected to the first gate layer arranged along the first direction through the electrical connection layer.

10. The antifuse memory according to claim 9, wherein, the electrical connection layer and the programming control layer are in the same layer.

11. The antifuse memory according to claim 9, wherein, the electrical connection layer and the programming control layer are in different layers; the antifuse memory further includes: A conductive pillar, the conductive pillar being located between the electrical connection layer and the programming control layer and electrically connecting the electrical connection layer and the programming control layer.

12. The antifuse memory according to claim 9, wherein, the thickness of the first gate dielectric layer is less than or equal to 30 angstroms; the thickness of the second gate dielectric layer is less than or equal to 30 angstroms.

13. The antifuse memory according to claim 9, wherein, further includes: A bit line layer, the bit line layer extending along the first direction and the bit line layer being electrically connected to the control transistors arranged along the first direction.

14. A design method for an antifuse memory, used for designing the antifuse memory according to any one of claims 9-13, wherein, includes: Defining the memory cell programmed in two adjacent memory cells along the first direction as a first memory cell, and the memory cell not programmed as a second memory cell. The node where the control transistor in the second memory cell is connected to the antifuse transistor is defined as a connection node. There is a first parasitic capacitance between the first gate layer and the connection node, and a second parasitic capacitance between the second gate layer and the connection node. During programming, it is defined that there is a voltage difference threshold between the first gate layer and the connection node in the second memory cell. The voltage difference threshold is the voltage difference between the first gate layer and the connection node corresponding to the breakdown of the antifuse transistor. The voltage of the programming control layer corresponding to the first memory cell is a programming voltage; Based on the programming voltage and the voltage difference threshold, obtaining the relationship between the first parasitic capacitance and the second parasitic capacitance; Based on the relationship between the first parasitic capacitance and the second parasitic capacitance, designing the channel size and / or the thickness of the first gate dielectric layer of the antifuse transistor in the second memory cell, and designing the channel size and / or the thickness of the second gate dielectric layer of the control transistor in the second memory cell.

15. The design method according to claim 14, wherein, the first parasitic capacitance, the second parasitic capacitance, the programming voltage, and the voltage difference threshold satisfy the following relationship: U = R1 * U0 / (R1 + R2), where U is any value less than or equal to the pressure difference threshold, U0 is the programming voltage, R1 is the first capacitive reactance corresponding to the first parasitic capacitance, and R2 is the second capacitive reactance corresponding to the second parasitic capacitance.

16. An anti-fuse memory circuit Characterized in that It includes: A plurality of memory cells, each of the memory cells includes an anti-fuse transistor and a control transistor connected together, and the connection node of the anti-fuse transistor and the control transistor is defined as a reference node; Bit lines, the bit lines are connected to the anti-fuse transistors arranged in the first direction, and each of the anti-fuse transistors is electrically connected to the bit lines through the control transistors; Word lines, the word lines are connected to the gates of the control transistors arranged in the second direction, and are used to turn on the selected control transistors according to the row selection signal, so that the bit lines are electrically connected to the anti-fuse transistors; Programming control lines, the programming control lines are connected to the gates of the anti-fuse transistors arranged in the first direction, and the anti-fuse transistors are used to perform programming according to the programming signals provided by the programming control lines; Wherein, there is a first parasitic capacitance between the gate of the anti-fuse transistor and the reference node, and a second parasitic capacitance between the gate of the control transistor and the reference node. During the programming of the anti-fuse transistor of a selected memory cell, the reference nodes of the adjacent anti-fuse transistors are coupled to a preset voltage, and the difference between the preset voltage and the voltage of the programming signal is less than or equal to a pressure difference threshold, and the pressure difference threshold is the pressure difference between the gate and the drain corresponding to the breakdown of the anti-fuse transistor.

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