Antifuse Memory and Its Control Method

Abstract

Embodiments of the present disclosure relate to the field of semiconductor technologies, and provide an anti-fuse memory and a control method therefor. The anti-fuse memory is configured to generate a programming pulse signal based on a row strobe signal. A word line of the anti-fuse memory array receives the row strobe signal, and the anti-fuse memory array is programmed in response to the programming pulse signal. Embodiments of the present disclosure are at least beneficial to improving the accuracy of reading data from the anti-fuse memory array and improving the yield of the anti-fuse memory.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to an anti-fuse memory and a control method thereof. Background Art

[0002] An anti-fuse memory can be implemented by an anti-fuse memory cell array. The gate oxide dielectric of the anti-fuse memory cell will break down when a high voltage is applied. After breakdown, the impedance of the path decreases; the information stored in the anti-fuse memory cell can be read by detecting the resistance state of the path after breakdown.

[0003] However, traditionally, programming of the anti-fuse memory is to apply a programming high voltage across the two ends of the anti-fuse memory cell. During the entire programming process, the programming high voltage level remains unchanged. After the programming high voltage is maintained for a period of time, the anti-fuse memory cell is broken down into a low-resistance state. However, the resistance in the low-resistance state is still relatively high, which still affects the accuracy of the information read from the anti-fuse memory cell. Summary of the Invention

[0004] Embodiments of the present disclosure provide an anti-fuse memory and a control method thereof, which at least help to improve the accuracy of data read from the anti-fuse memory and the yield of the anti-fuse memory.

[0005] According to some embodiments of the present disclosure, on the one hand, an anti-fuse memory is provided. The anti-fuse memory is configured to generate a programming pulse signal based on a row select signal. The word lines of the anti-fuse memory array receive the row select signal, and the anti-fuse memory array is programmed in response to the programming pulse signal.

[0006] In some embodiments, the anti-fuse memory is further configured to generate the programming pulse signal with an adjustable duty cycle based on the row select signal.

[0007] In some embodiments, the anti-fuse memory is further configured to generate the programming pulse signal based on the row select signal and a reference pulse signal.

[0008] In some embodiments, the reference pulse signal is an internal clock signal.

[0009] In some embodiments, the anti-fuse memory includes a reference pulse signal generation module configured to output the reference pulse signal with an adjustable duty cycle.

[0010] In some embodiments, the anti-fuse memory includes a pulse signal generation module. The pulse signal generation module receives the row select signal and generates the programming pulse signal.

[0011] In some embodiments, the pulse signal generation module includes: a signal generation unit, which outputs an initial pulse signal in response to the row strobe signal; a level converter, which is used to perform level conversion on the initial pulse signal to generate and output the programming pulse signal, and the level value of the programming pulse signal is greater than the level value of the initial pulse signal.

[0012] In some embodiments, the signal generation unit simultaneously responds to the row strobe signal and a reference pulse signal to output the initial pulse signal.

[0013] In some embodiments, the duty cycle of the reference pulse signal is adjustable.

[0014] In some embodiments, the signal generation unit includes: a ring oscillator circuit, and the row strobe signal is an enable signal of the ring oscillator circuit, and the output end of the ring oscillator circuit outputs the initial pulse signal.

[0015] In some embodiments, the ring oscillator circuit is configured to output the initial pulse signal with an adjustable duty cycle.

[0016] In some embodiments, the ring oscillator circuit includes: a comparison circuit, and the output end of the comparison circuit outputs the initial pulse signal; a pull-up module, connected between the working power supply and the input end of the comparison circuit, which is turned on in response to the row strobe signal and a first level signal output by the comparison circuit, and pulls up the voltage of the input end of the comparison circuit at a first rate, and the first rate is adjustable; a pull-down module, connected between the ground end and the input end of the comparison circuit, which is turned on in response to the row strobe signal and a second level signal output by the comparison circuit, and pulls down the voltage of the input end of the comparison circuit at a second rate, and the second rate is adjustable, and the level values of the first level signal and the second level signal are different.

[0017] In some embodiments, the pull-up module includes a first current source and a first switch module, the first switch module is connected between the first current source and the input end of the comparison circuit, and the first switch module is turned on in response to the row strobe signal and the first level signal; the pull-down module includes a second current source and a second switch module, the second switch module is connected between the second current source and the input end of the comparison circuit, and the second switch module is turned on in response to the row strobe signal and the second level signal, and the current magnitude of the first current source and / or the second current source is adjustable.

[0018] In some embodiments, the comparison circuit includes a comparator and a second inverter connected in series with the comparator, and an output end of the second inverter outputs the initial pulse signal; the first switch module includes a first switch tube and a second switch tube connected in series, the first current source is connected between the first switch tube and the operating power supply, a control end of the second switch tube is connected to the output end of the second inverter, and the first switch tube is turned on in response to the row strobe signal; the second switch module includes a third switch tube and a fourth switch tube connected in series, the second current source is connected between the fourth switch tube and the ground terminal, a control end of the third switch tube is connected to the output end of the second inverter, and the fourth switch tube is turned on in response to the row strobe signal.

[0019] In some embodiments, the antifuse memory further includes: a current adjustment module configured to adjust the current magnitude of the first current source and / or the second current source.

[0020] According to some embodiments of the present disclosure, on the other hand, the present disclosure embodiments further provide a control method for an antifuse memory, including: generating a programming pulse signal in response to a row strobe signal; and performing programming in response to the programming pulse signal.

[0021] In some embodiments, the generating the programming pulse signal in response to the row strobe signal includes: simultaneously generating the programming pulse signal in response to the row strobe signal and a reference pulse signal, and a duty cycle of the reference pulse signal is adjustable.

[0022] In some embodiments, the generating the programming pulse signal in response to the row strobe signal includes: generating the programming pulse signal with an adjustable duty cycle in response to the row strobe signal.

[0023] The technical solutions provided by the embodiments of the present disclosure have the following advantages:

[0024] The word line of the antifuse memory array receives the row strobe signal and generates a programming pulse signal based on the row strobe signal, and further, the antifuse memory array performs programming in response to the programming pulse signal. Thus, during the entire programming process of the antifuse memory cell, the level value of the programming voltage changes periodically, avoiding the overheating problem after the antifuse memory cell is broken down, being beneficial to reducing the probability of damage to the antifuse memory array, and being beneficial to reducing the resistance of the antifuse memory cell in the low-resistance state after being broken down, thereby being beneficial to improving the success rate of reading the antifuse memory cell, improving the accuracy of reading data from the antifuse memory cell, and improving the yield of the antifuse memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic circuit structure diagram of an anti-fuse memory circuit;

[0027] Figure 2 It is a schematic diagram of a functional module structure of an anti-fuse memory provided by an embodiment of the present disclosure;

[0028] Figure 3 It is a curve graph obtained by testing the anti-fuse memory array when the programming voltage signal is a DC signal or a pulse signal;

[0029] Figure 4 It is another schematic diagram of a functional module structure of an anti-fuse memory provided by an embodiment of the present disclosure;

[0030] Figures 5 to 11 It is a schematic diagram of 7 structures of an anti-fuse memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0031] As can be seen from the background art, the accuracy of the information read from the anti-fuse memory array needs to be improved.

[0032] Figure 1 It is a schematic circuit structure diagram of an anti-fuse memory circuit.

[0033] Refer to Figure 1 , the anti-fuse memory includes:

[0034] Antifuse memory array, including a plurality of antifuse memory cells 10. The antifuse memory cells 10 are turned on by receiving a programming voltage signal, and the programming voltage signal is labeled with FsBln0, FsBln1, FsBln2... or FsBlnN. The antifuse memory cells 10 characterize the stored 1-bit data by whether the gate oxide layer is broken down. It should be noted that, taking the antifuse memory cell 10 receiving "FsBln0" as an example, the "0" therein characterizes that the antifuse memory cell 10 is connected to the 0th word line; taking the antifuse memory cell 10 receiving "FsBln2" as an example, the "2" therein characterizes that the antifuse memory cell 10 is connected to the 2nd word line, and the "N" in "FsBlnN" characterizes that the antifuse memory cell 10 receiving "FsBlnN" is connected to the Nth word line.

[0035] A plurality of bit lines are labeled with BL0, BL1... BLN. The antifuse memory cells 10 are connected in the extending direction of the bit lines, and the antifuse memory cells 10 are connected to the bit lines through the first switching transistors 11.

[0036] Among them, the gates of the first switching transistors 11 are used to receive row selection signals, which are labeled with XAdd0, XAdd1, XAdd2... or XAddN. One end of the source or drain is connected to the antifuse memory cells 10, and the other end is connected to the bit lines. It should be noted that, taking the first switching transistor 11 receiving "XAdd0" as an example, the "0" therein characterizes that the first switching transistor 11 is connected to the 0th word line; taking the first switching transistor 11 receiving "XAdd2" as an example, the "2" therein characterizes that the first switching transistor 11 is connected to the 2nd word line, and the "N" in "XAddN" characterizes that the first switching transistor 11 receiving "XAddN" is connected to the Nth word line. It should be noted that the row selection signal is used to select and turn on the word line connected to the selected first switching transistor 11. The row selection signal is the word line selection signal, which is used to select a target word line and turn on the first switching transistor 11 connected to the target word line among many word lines.

[0037] The second switching transistor 12, the gate of the second switching transistor 12 is used to receive a column strobe signal, which is labeled with YAdd0, YAdd1... or YAddN for the column strobe signal. One end of the source or drain is connected to the bit line, and the other end is connected to the transmission wire 13. It should be noted that taking the second switching transistor 12 that receives "YAdd0" as an example, the "0" therein represents that the second switching transistor 12 is connected to the bit line BL0; taking the second switching transistor 12 that receives "YAdd1" as an example, the "1" therein represents that the second switching transistor 12 is connected to the bit line BL1, and the "N" in "YAddN" represents that the second switching transistor 12 that receives "YAddN" is connected to the bit line BLN. It should be noted that the column strobe signal is used to select and conduct the bit line connected to the selected second switching transistor 12. The column strobe signal is the bit line strobe signal, which is used to select a target bit line among many bit lines and conduct the second switching transistor 12 connected to the target bit line.

[0038] The precharge circuit 14 is connected in the extending direction of the bit line. The precharge circuit 14 is used to precharge the bit line to a precharge voltage according to a precharge signal.

[0039] The third switching transistor 15, one end of the source or drain is connected to the transmission wire 13, the other end is grounded, and the gate is used to receive a discharge signal ZAdd, which is used to discharge the charge in the transmission wire 13 according to the discharge signal ZAdd.

[0040] Next, taking the antifuse memory cell 10 that receives "FsBlnN" as an example, Figure 1 the working principle of the provided antifuse memory circuit will be described in detail as follows:

[0041] The first switching transistor 11 is turned on based on "XAddN", and the second switching transistor 12 is turned on based on "YAdd0", then the antifuse memory cell 10 that receives "FsBlnN" and is electrically connected to the bit line BL0 through the first switching transistor 11 can be selected. In the data programming stage, during the process of programming the antifuse memory cell 10 that receives "FsBlnN" based on "FsBlnN", the third switching transistor 15 is turned on based on "ZAdd", the charge in the transmission wire 13 is discharged through the third switching transistor 15, and the voltage at the source end of the antifuse memory cell 10 is made to be at a low level to ensure the accuracy of data programming for the antifuse memory cell 10 that receives "FsBlnN"; in the data readout stage, the third switching transistor 15 is turned off based on "ZAdd", the precharge circuit 14 receives a precharge signal to precharge the bit line to a precharge voltage, at this time the transmission wire 13 is electrically connected to the precharge circuit 14, and thus is precharged to the precharge voltage to read the data stored in the antifuse memory cell 10 that receives "FsBlnN"; in addition, the precharge circuit 14 is also used to charge the bit line to avoid other antifuse memory cells 10 that receive the same programming signal as the target antifuse memory cell 10 from being broken down. Specifically, the target antifuse memory cell 10 is the antifuse memory cell to be programmed. Before programming the target antifuse memory cell 10, the level of the bit line (such as BL1) connected to the target antifuse memory cell 10 is pulled down to a low level to ensure that the target antifuse memory cell 10 has a large gate-source voltage difference under the programming voltage to achieve effective programming. At the same time, other bit lines (such as BL1 and BL2) are precharged to a preset level to avoid other antifuse memory cells 10 that receive the same programming signal from being broken down due to having a large gate-source voltage difference.

[0042] However, through analysis, it is found that during the programming process, a programming voltage signal applied to each antifuse memory cell 10 in the antifuse memory array has been a high level, and the duration of maintaining the high level is also the same. Due to the non-uniformity problem of the antifuse memory cells 10, that is, there are differences in the electrical properties of different antifuse memory cells 10, this results in different times required for the insulating dielectric layers of each antifuse memory cell 10 to be broken down under the action of the same voltage, and the duration of maintaining the high level applied to each antifuse memory cell 10 is the same. For the antifuse memory cell 10 whose insulating dielectric layer has been broken down, if a programming voltage with a constant level continues to be applied, it will cause the antifuse memory cell 10 to quickly overheat, easily lead to a failure of the antifuse memory cell 10, and easily cause the resistance of the antifuse memory cell 10 in the low-resistance state after being broken down to be large, thereby reducing the accuracy of reading data from the antifuse memory cell 10 and reducing the yield of the antifuse memory.

[0043] The present disclosure provides an anti - fuse memory and its control method. The anti - fuse memory receives a row strobe signal and generates a programming pulse signal based on the row strobe signal, and performs programming in response to the programming pulse signal. In this way, during the entire programming process of the anti - fuse memory cell, the level value of the programming voltage changes periodically, avoiding the overheating problem after the anti - fuse memory cell is broken down. On the one hand, it is beneficial to reduce the probability of damage to the anti - fuse memory cell, thereby improving the yield rate of the anti - fuse memory. On the other hand, it is beneficial to reduce the resistance of the anti - fuse memory cell in the low - resistance state after being broken down, thus facilitating the improvement of the success rate when reading the anti - fuse memory cell, and improving the accuracy of reading data from the anti - fuse memory.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented for the readers to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0045] An embodiment of the present disclosure provides an anti - fuse memory, and the anti - fuse memory provided in an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 2 It is a schematic diagram of a functional module structure of the anti - fuse memory provided in an embodiment of the present disclosure; Figure 3 It is a curve graph obtained by testing the anti - fuse memory array when the programming voltage signal is a DC signal or a pulse signal; 4 is another schematic diagram of a functional module structure of the anti - fuse memory provided in an embodiment of the present disclosure; Figures 5 to 11 It is a schematic diagram of 7 structures of the anti - fuse memory provided in an embodiment of the present disclosure.

[0046] In the embodiments of the present disclosure, with reference to Figure 2 , the anti - fuse memory is configured to: generate a programming pulse signal 100b based on the row strobe signal 100a, the word line WL of the anti - fuse memory array 100 receives the row strobe signal 100a, and the anti - fuse memory array 100 performs programming in response to the programming pulse signal 100b.

[0047] It should be noted that the antifuse memory array 100 includes a plurality of antifuse memory cells. The antifuse memory cells characterize the stored 1-bit data by whether the gate oxide layer is broken down. Programming the antifuse memory array 100 means programming the target antifuse memory cell in the antifuse memory array 100. If the antifuse memory array 100 is programmed in response to the programming pulse signal 100b, for a certain antifuse memory cell, during the entire programming process of this antifuse memory cell, the level value of the programming voltage applied to the gate of this antifuse memory cell changes periodically, avoiding overheating problems after this antifuse memory cell is broken down. On the one hand, it is beneficial to reduce the probability of damage to this antifuse memory cell to improve the yield of this antifuse memory cell, thereby facilitating the improvement of the yield of the antifuse memory; on the other hand, it is beneficial to reduce the resistance of this antifuse memory cell in the low-resistance state after being broken down, thereby facilitating the improvement of the success rate when reading the data stored in this antifuse memory cell, to improve the accuracy of the overall read data of the antifuse memory array 100.

[0048] Reference Figure 3 , Figure 3 is a curve graph obtained by testing the antifuse memory array when the programming voltage signal is a DC signal or a pulse signal. Among them, curve a is a relationship curve graph between the test current of the programmed antifuse memory cell and the corresponding number of antifuse memory cells when the programming voltage signal is a DC signal, and curve b is a relationship curve graph between the test current of the programmed antifuse memory cell and the corresponding number of antifuse memory cells when the programming voltage signal is a pulse signal. It should be noted that the pulse signal is the programming pulse signal 100b.

[0049] Reference Figure 3 It can be seen that when programming the same number of antifuse memory cells, the average test current of the antifuse memory cell programmed in response to the programming pulse signal 100b is greater than the average test current of the antifuse memory cell programmed in response to the DC signal. That is to say, using the programming pulse signal 100b to program the antifuse memory cell is beneficial to reducing the resistance of the antifuse memory cell in the low-resistance state after being broken down, thereby facilitating the improvement of the accuracy of reading data from the antifuse memory cell. After programming, by applying a preset test voltage to the original gate of the antifuse memory cell, the corresponding test current can be obtained. It can be understood that the smaller the resistance of the antifuse memory cell after being broken down, the larger the test current. In other words, the larger the average test current, the smaller the average resistance after being broken down, and the higher the reading accuracy.

[0050] In some embodiments, the antifuse memory can also be configured to generate a programming pulse signal 100b with an adjustable duty cycle based on the row strobe signal 100a.

[0051] Due to some inevitable differences such as process or manual settings, there are uneven problems in different antifuse memory cells, that is, there are differences in the electrical properties of different antifuse memory cells. This results in different times required for the insulating dielectric layers of each antifuse memory cell to be broken down under the action of the same voltage. By adjusting the duty cycle of the programming pulse signal 100b, the time required for the antifuse memory cells programmed based on the programming pulse signal 100b to be broken down is controlled, so as to ensure that antifuse memory cells with different electrical properties can all be programmed based on the programming pulse signal, which is beneficial to the accuracy of reading data from the antifuse memory cells and improves the yield rate of the antifuse memory.

[0052] In some embodiments, referring to Figure 4 , the antifuse memory can also be configured to generate a programming pulse signal 100b based on the row strobe signal 100a and the reference pulse signal 100d.

[0053] It should be noted that in some examples, the duty cycle of the programming pulse signal 100b is adjustable; in other examples, the duty cycle of the programming pulse signal 100b can also be a fixed value.

[0054] Among them, regarding how to generate a programming pulse signal 100b with an adjustable duty cycle based on the row strobe signal 100a and the reference pulse signal 100d, the following will be described in detail through two embodiments.

[0055] In some examples, the duty cycle of the reference pulse signal 100d is adjustable, so that the duty cycle of the programming pulse signal 100b generated based on the row strobe signal 100a and the reference pulse signal 100d is adjustable; in some other examples, the duty cycle of the reference pulse signal 100d remains unchanged, and the duty cycle of the programming pulse signal 100b is directly adjusted.

[0056] Among them, how to generate the reference pulse signal 100d can be described in detail through the following two embodiments.

[0057] In some embodiments, the reference pulse signal 100d can be an internal clock signal. It can be understood that the internal clock signal can be a clock signal generated by an existing module in the antifuse memory, which is used as the reference pulse signal 100d to cooperate with the row strobe signal 100a to generate the programming pulse signal 100b. In this way, there is no need to provide an additional clock signal generation module, which is beneficial to reducing the manufacturing cost of the antifuse memory.

[0058] In some other embodiments, the antifuse memory may include a reference pulse signal generation module (not shown) configured to output a reference pulse signal 100d with an adjustable duty cycle. Since the programming pulse signal 100b is generated based on the row strobe signal 100a and the reference pulse signal 100d, if the duty cycle of the reference pulse signal 100d is adjustable, the duty cycle of the programming pulse signal 100b can also be adjusted by adjusting the duty cycle of the reference pulse signal 100d, so as to satisfy that antifuse memory cells with different electrical performances can be programmed based on the programming pulse signal 100b, which is conducive to improving the accuracy of reading data from the antifuse memory array and the yield rate of the antifuse memory.

[0059] The following will Figure 2 and Figures 5 to 11 describe in detail the specific structure of the antifuse memory.

[0060] Refer to Figure 2 , the antifuse memory includes a pulse signal generation module 110. The pulse signal generation module 110 receives the row strobe signal 100a and generates a programming pulse signal 100b. In this way, during the entire programming process of the antifuse memory array 100, the level value of the programming voltage formed based on the programming pulse signal 100b changes periodically, avoiding the overheating problem after the antifuse memory cell is broken down, which is conducive to improving the accuracy of reading data from the antifuse memory cell and the yield rate of the antifuse memory.

[0061] In some embodiments, refer to Figure 5 , the pulse signal generation module 110 includes a signal generation unit 101. The signal generation unit 101 outputs an initial pulse signal 100c in response to the row strobe signal 100a; a level converter 102 is used to perform level conversion on the initial pulse signal 100c to generate and output a programming pulse signal 100b, and the level value of the programming pulse signal 100b is greater than the level value of the initial pulse signal 100c.

[0062] By adjusting the level peak value of the initial pulse signal 100c through the level converter 102, a programming pulse signal 100b with a higher level peak value is obtained, that is, the programming pulse signal 100b is in the high-voltage power supply domain, so that the programming voltage formed based on the programming pulse signal 100b is higher, which is conducive to ensuring that the antifuse memory cells to be programmed in the antifuse memory are broken down, so as to improve the success rate when reading the antifuse memory. In one example, after the initial pulse signal 100c is converted by the level converter 102 to generate the programming pulse signal 100b, the highest voltage of the programming voltage formed based on the programming pulse signal 100b can reach 6V.

[0063] Among them, if the row strobe signal 100a is at a high level, the programming pulse signal 100b is a high-voltage pulse signal. When using the programming pulse signal 100b to program a certain anti-fuse memory cell in the anti-fuse memory, it is beneficial to reduce the resistance of the anti-fuse memory cell in the low-resistance state caused by breakdown, thereby facilitating the improvement of the success rate when reading the anti-fuse memory cell and improving the programming effect of the anti-fuse memory. If the row strobe signal 100a is at a low level, it indicates the end of the programming of the anti-fuse memory cell. At this time, the programming pulse signal 100b is also at a low level, and the application of high voltage to the anti-fuse memory cell is stopped to avoid overheating problems of the anti-fuse memory cell.

[0064] Regarding the specific structure of the signal generation unit 101, the following will be described in detail through two embodiments.

[0065] In some embodiments, referring to Figure 6 , the signal generation unit 101 can simultaneously respond to the row strobe signal 100a and the reference pulse signal 100d to output the initial pulse signal 100c.

[0066] Among them, the duty cycle of the reference pulse signal 100d is adjustable. Since the initial pulse signal 100c is generated based on the row strobe signal 100a and the reference pulse signal 100d, if the duty cycle of the reference pulse signal 100d is adjustable, the duty cycle of the initial pulse signal 100c can also be adjusted by adjusting the duty cycle of the reference pulse signal 100d. Subsequently, the initial pulse signal 100c is converted by the level converter 102 to generate the programming pulse signal 100b, and the duty cycle of the programming pulse signal 100b is also adjustable to meet the programming requirements of anti-fuse memory cells with different electrical properties based on the programming pulse signal 100b, thereby facilitating the improvement of the accuracy of reading data from the anti-fuse memory and the yield of the anti-fuse memory.

[0067] In some embodiments, referring to Figure 7 , the signal generation unit 101 (refer to Figure 6 ) may include an AND gate circuit 103. One input terminal of the AND gate circuit 103 receives the row strobe signal 100a, and the other input terminal receives the reference pulse signal 100d. The output terminal of the AND gate circuit 103 outputs the initial pulse signal 100c.

[0068] Among them, continuing to refer to Figure 7, the AND gate circuit 103 may include: a NAND gate 113, where the two input terminals of the NAND gate 113 respectively receive the row strobe signal 100a and the reference pulse signal 100d; a first inverter 123, and the output terminal of the NAND gate 113 is connected to the input terminal of the first inverter 123. Among them, the NAND gate 113 and the first inverter 123 work together to perform a logical AND operation on the row strobe signal 100a and the reference pulse signal 100d to form an initial pulse signal 100c.

[0069] It should be noted that Figure 7 only the series connection of the NAND gate 113 and the first inverter 123 to implement the logical AND operation of the AND gate circuit 103 is taken as an example. In practical applications, any circuit that can implement the logical AND operation and receive two signals simultaneously can be used as the AND gate circuit 103 in the embodiments of the present disclosure. That is, the embodiments of the present disclosure do not limit the specific form of the AND gate circuit 103.

[0070] In some other embodiments, referring to Figure 8 , the signal generation unit 101 (referring to Figure 6 ) may include: a ring oscillator circuit 104, and the row strobe signal 100a is the enable signal of the ring oscillator circuit 104, and the output terminal of the ring oscillator circuit 104 outputs the initial pulse signal 100c. In this way, the antifuse memory can generate a programming pulse signal 100b with an adjustable duty cycle only based on the row strobe signal 100a.

[0071] Among them, the ring oscillator circuit 104 may be configured to output an initial pulse signal 100c with an adjustable duty cycle, that is, the oscillation rate of the ring oscillator circuit 104 is adjustable. Since the duty cycle of the initial pulse signal 100c is adjustable, the duty cycle of the programming pulse signal 100b generated by converting the initial pulse signal 100c through the level converter 102 can also be adjusted, so as to satisfy that antifuse memory cells with different electrical properties can all be programmed based on the programming pulse signal 100b, which is beneficial to improving the accuracy of reading data from the antifuse memory and the yield of the antifuse memory.

[0072] In some embodiments, continue to refer to Figure 8, the ring oscillator circuit 104 includes: a comparison circuit 114, the output terminal of the comparison circuit 114 outputs an initial pulse signal 100c; a pull-up module 124, connected between the working power supply 134 and the input terminal of the comparison circuit 114, and is turned on in response to the row strobe signal 100a and the first level signal 114a output by the comparison circuit 114, and pulls up the voltage of the input terminal of the comparison circuit 114 at a first rate, and the first rate is adjustable; a pull-down module 144, connected between the ground terminal 154 and the input terminal of the comparison circuit 114, and is turned on in response to the row strobe signal 100a and the second level signal 114b output by the comparison circuit 114, and pulls down the voltage of the input terminal of the comparison circuit 114 at a second rate, and the second rate is adjustable, and the level values of the first level signal 114a and the second level signal 114b are different.

[0073] It can be understood that when programming a certain anti-fuse memory cell of the anti-fuse memory, the row strobe signal 100a is at a high level, and the pull-up module 124 is turned on based on the row strobe signal 100a and the first level signal 114a, so as to transmit the working voltage VDD of the working power supply 134 to the input terminal of the comparison circuit 114 at a first rate, and pull up the voltage of the input terminal of the comparison circuit 114. At this time, the pull-down module 144 is in an off state based on the row strobe signal 100a and the first level signal 114a; when the voltage of the input terminal of the comparison circuit 114 is pulled up to a first preset value, the output terminal of the comparison circuit 114 outputs a second level signal 114b; then, the pull-down module 144 is turned on based on the row strobe signal 100a and the second level signal 114b, so as to transmit the voltage of the ground terminal 154 to the input terminal of the comparison circuit 114 at a second rate, and pull down the voltage of the input terminal of the comparison circuit 114. At this time, the pull-up module 124 is in an off state based on the row strobe signal 100a and the second level signal 114b; when the voltage of the input terminal of the comparison circuit 114 is pulled down to a second preset value, the output terminal of the comparison circuit 114 outputs a first level signal 114a, and the pull-up module 124 is turned on again... and so on in a cycle, so that the ring oscillator circuit 104 generates an initial pulse signal 100c based on the row strobe signal 100a. In addition, since the first rate is adjustable and the second rate is adjustable, the time difference between the output of the second level signal 114b and the output of the second level signal 114b at the output terminal of the comparison circuit 114 is adjustable, so as to realize the adjustment of the duty cycle of the initial pulse signal 100c output by the output terminal of the comparison circuit 114.

[0074] Among them, the level value of the first level signal 114a is lower than that of the second level signal 114b, and the first preset value is higher than the second preset value. In practical applications, the level value of the first level signal 114a can also be higher than that of the second level signal 114b. By setting the comparison circuit 114 with the first preset value and the second preset value, it is beneficial to extend the cycle length of the initial pulse signal 100c, avoid overheating of the anti-fuse unit caused by too high a programming pulse frequency, ensure a relatively small resistance after breakdown of the anti-fuse unit, and ensure the accuracy of the resistance measurement of the anti-fuse unit.

[0075] In some embodiments, referring to Figure 9 , the pull-up module 114 may include a first current source 164 and a first switch module 174. The first switch module 174 is connected between the first current source 164 and the input end of the comparison circuit 114, and the first switch module 174 is turned on in response to the row strobe signal 100a and the first level signal 114a; the pull-down module 144 includes a second current source 184 and a second switch module 194. The second switch module 194 is connected between the second current source 184 and the input end of the comparison circuit 114, and the second switch module 194 is turned on in response to the row strobe signal 100a and the second level signal 114b, and the current magnitude of the first current source 164 and / or the second current source 184 is adjustable.

[0076] In this way, by adjusting the current magnitude of the first current source 164, the adjustment of the first rate can be achieved, that is, by adjusting the current magnitude of the first current source 164, the time required to adjust the voltage at the input end of the pull-up comparison circuit 114 to the first preset value when the first switch module 174 is turned on; by adjusting the current magnitude of the second current source 184, the adjustment of the second rate can be achieved, that is, by adjusting the current magnitude of the second current source 184, the time required to adjust the voltage at the input end of the pull-down comparison circuit 114 to the second preset value when the second switch module 194 is turned on, so as to achieve the adjustment of the duty cycle of the initial pulse signal 100c output by the output end of the comparison circuit 114.

[0077] Among them, the anti-fuse memory may further include: a current adjustment module (not shown in the figure), configured to adjust the current magnitude of the first current source 164 and / or the second current source 184.

[0078] In some embodiments, referring to Figure 10, the comparison circuit 114 includes a comparator 105 and a second inverter 115 connected in series with the comparator 105, and an initial pulse signal 100c is output from the output terminal of the second inverter 115; the first switch module 174 includes a first switch transistor 125 and a second switch transistor 135 connected in series, a first current source 164 is connected between the first switch transistor 125 and the operating power supply VDD, the control terminal of the second switch transistor 135 is connected to the output terminal of the second inverter 115, and the first switch transistor 125 is turned on in response to the row strobe signal 100a; the second switch module 194 includes a third switch transistor 145 and a fourth switch transistor 155 connected in series, a second current source 184 is connected between the fourth switch transistor 155 and the ground terminal, the control terminal of the third switch transistor 145 is connected to the output terminal of the second inverter 115, and the fourth switch transistor 155 is turned on in response to the row strobe signal 100a.

[0079] Wherein, if a certain anti-fuse memory cell of the anti-fuse memory is programmed, the row strobe signal 100a is an enable signal of the ring oscillator circuit 104, and the first switch transistor 125 and the fourth switch transistor 155 are in a conducting state in response to the row strobe signal 100a. If a first level signal 114a is output from the output terminal of the second inverter 115 (refer to Figure 9 ), the second switch transistor 135 is turned on based on the row strobe signal 100a and the first level signal 114a, the third switch transistor 145 is turned off based on the row strobe signal 100a and the first level signal 114a, and the first current source 164 pulls up the voltage at the input terminal of the comparator 105 to a first preset value at a first rate; if a second level signal 114b is output from the output terminal of the second inverter 115 (refer to Figure 9 ), the second switch transistor 135 is turned off based on the row strobe signal 100a and the second level signal 114b, the third switch transistor 145 is turned on based on the row strobe signal 100a and the second level signal 114b, and the second current source 184 pulls down the voltage at the input terminal of the comparator 105 to a second preset value at a second rate.

[0080] It can be understood that the comparator 105 can be configured to conduct when both the first switching transistor 125 and the second switching transistor 135 are conducting and the voltage at the input terminal of the comparator 105 rises to a first preset value, and after inverting the electrical signal received at the input terminal of the comparator 105, transmit it to the input terminal of the second inverter 115. The second inverter 115 inverts the electrical signal again and outputs a first level signal 114a; alternatively, when both the third switching transistor 145 and the fourth switching transistor 155 are conducting and the voltage at the input terminal of the comparator 105 drops to a second preset value, conduct, and after inverting the electrical signal received at the input terminal of the comparator 105, transmit it to the input terminal of the second inverter 115. The second inverter 115 inverts the electrical signal again and outputs a second level signal 114b. In this way, the output terminal of the second inverter 115 can periodically output the first level signal 114a and the second level signal 114b, thereby realizing the alternating conduction of the second switching transistor 135 and the third switching transistor 145, so that the output terminal of the ring oscillator circuit 104 outputs an initial pulse signal 100c, and an initial pulse signal 100c with an adjustable duty cycle can be formed by adjusting the first rate and the second rate.

[0081] It should be noted that, continuing to refer to Figure 10 , the ring oscillator circuit 104 may further include: a charge and discharge module 165. One end of the charge and discharge module 165 is electrically connected to the input terminal of the comparison circuit 114, and the other end of the charge and discharge module 165 is electrically connected to the ground terminal. Among them, if both the first switching transistor 125 and the second switching transistor 135 are conducting, the charge and discharge module 165 is in a charging state by being electrically connected to the working power supply through the conducting first switching transistor 125 and second switching transistor 135, so as to extend the time required for the voltage at the input terminal of the comparison circuit 114 to be pulled up to the first preset value; if both the third switching transistor 145 and the fourth switching transistor 155 are conducting, the charge and discharge module 165 is in a discharging state by being electrically connected to the ground terminal through the conducting third switching transistor 145 and fourth switching transistor 155, so as to extend the time required for the voltage at the input terminal of the comparison circuit 114 to be pulled down to the second preset value. By setting the charge and discharge module 165, it is beneficial to extend the cycle length of the initial pulse signal 100c, avoid overheating of the anti-fuse unit caused by too high a programming pulse frequency, ensure that the resistance of the anti-fuse unit is small after breakdown, and ensure the accuracy of the resistance measurement of the anti-fuse unit. It can be understood that the first rate and the second rate are also affected by the charge and discharge rate of the charge and discharge module 165.

[0082] In one example, the charge and discharge module 165 can be a capacitor with a variable capacitance value, and the first rate and the second rate can be adjusted by adjusting the capacitance value of the capacitor. It should be noted that, Figure 10Taking the charge and discharge module 165 with a variable capacitance value as an example, in practical applications, the charge and discharge module 165 can also be other electrical devices capable of realizing the charge and discharge function. The embodiments of the present disclosure do not limit the specific forms of the charge and discharge module 165.

[0083] In some embodiments, referring to Figure 11 , the ring oscillator circuit 104 (referring to Figure 10 ) may further include: a fourth inverter 107, the input end of the fourth inverter 107 receives the row strobe signal 100a, and the output end of the fourth inverter 107 is connected to the control end of the first switch 125.

[0084] Among them, if the level value of the first level signal 114a is lower than the level value of the second level signal 114b, the second switch 135 can be a PMOS transistor, and is turned on based on the low level, that is, the first level signal 114a, and the third switch can be an NMOS transistor, and is turned on based on the high level, that is, the second level signal 114b.

[0085] In addition, the first switch 125 and the fourth switch 155 are turned on based on the row strobe signal 100a. When the antifuse memory is in the programming stage, the row strobe signal 100a is at a high level. Referring to Figure 10 , if there is no inverter between the control end of the first switch 125 and the row strobe signal 100a, and between the fourth switch 155 and the row strobe signal 100a, the first switch 125 and the fourth switch 155 can be NMOS transistors, and are turned on based on the high level, that is, the row strobe signal 100a; referring to Figure 11 , if there is a fourth inverter 107 between the control end of the first switch 125 and the row strobe signal 100a, and there is no inverter between the fourth switch 155 and the row strobe signal 100a, the first switch 125 can be a PMOS transistor, and is turned on based on the low level, that is, the inverted signal of the row strobe signal 100a, and the fourth switch 155 can be an NMOS transistor, and is turned on based on the high level, that is, the row strobe signal 100a. In practical applications, if there are inverters between the control end of the first switch 125 and the row strobe signal 100a and between the fourth switch 155 and the row strobe signal 100a, the first switch 125 and the fourth switch 155 can both be PMOS transistors, and are turned on based on the low level, that is, the inverted signal of the row strobe signal 100a; if there is no inverter between the control end of the first switch 125 and the row strobe signal 100a, and there is an inverter between the fourth switch 155 and the row strobe signal 100a, the first switch 125 can be an NMOS transistor, and is turned on based on the high level, that is, the row strobe signal 100a, and the fourth switch 155 can be a PMOS transistor, and is turned on based on the low level, that is, the inverted signal of the row strobe signal 100a.

[0086] It should be noted that Figure 10 and Figure 11 take the series connection of the first switching transistor 125 and the second switching transistor 135 to implement the function of the first switching module 174 as an example. In practical applications, any circuit module that can be turned on in response to the row strobe signal 100a and the first level signal 114a can be used as the first switching module 174 in the embodiments of the present disclosure. That is, the embodiments of the present disclosure do not limit the specific form of the first switching module 174. In addition, Figure 10 and Figure 11 take the series connection of the third switching transistor 145 and the fourth switching transistor 155 to implement the function of the second switching module 194 as an example. In practical applications, any circuit module that can be turned on in response to the row strobe signal 100a and the second level signal 114b can be used as the second switching module 194 in the embodiments of the present disclosure. That is, the embodiments of the present disclosure do not limit the specific form of the second switching module 194.

[0087] In some embodiments, referring to Figure 11 , the signal generation unit 101 (refer to Figure 6 ) may further include: a buffer circuit 106, and the buffer circuit 106 is connected to the output terminal of the ring oscillator circuit 104 (refer to Figure 10 ).

[0088] Among them, the buffer circuit 106 may include an even number of third inverters 116 connected in series.

[0089] Since the third inverter 116 has advantages such as a large noise margin, an extremely high input resistance, an extremely low static power consumption, and insensitivity to noise and interference, and an even number of third inverters 116 connected in series will not invert the initial pulse signal 100c finally transmitted to the input terminal of the level converter 102 (refer to Figure 7 ), it is beneficial to reduce the interference suffered by the initial pulse signal 100c during the transmission from the output terminal of the ring oscillator circuit 104 to the input terminal of the level converter 102, so as to further ensure that the initial pulse signal 100c transmitted to the input terminal of the level converter 102 is not distorted, so as to ensure the accuracy of the programming pulse signal 100b formed based on the initial pulse signal 100c subsequently, which is beneficial to improving the success rate when reading the antifuse memory, so as to improve the programming effect of the antifuse memory.

[0090] In summary, during the entire programming process of the antifuse memory, the programming pulse signal 100b generated based on the row strobe signal 100a helps to avoid the overheating problem after the antifuse memory is broken down. On the one hand, it helps to reduce the probability of damage to the antifuse memory, thereby improving the yield of the antifuse memory; on the other hand, it helps to reduce the resistance of the antifuse memory in the low-resistance state after being broken down, thus facilitating the improvement of the success rate when reading the antifuse memory, so as to improve the accuracy of reading data from the antifuse memory.

[0091] Another embodiment of the present disclosure provides a control method for an antifuse memory, which is used to control the antifuse memory provided in the foregoing embodiment. The following will be combined with Figure 2 and Figure 4 to describe in detail the control method for the antifuse memory provided in another embodiment of the present disclosure. Corresponding parts to the foregoing embodiment will not be elaborated herein.

[0092] Referring to Figure 2 , the control method of the antifuse memory includes: generating a programming pulse signal 100b in response to the row strobe signal 100a; performing programming in response to the programming pulse signal 100b. In this way, during the entire programming process of the antifuse memory, the level value of the programming voltage formed based on the programming pulse signal 100b changes periodically, avoiding the overheating problem after the antifuse memory is broken down, thus facilitating the improvement of the accuracy of reading data from the antifuse memory and the yield of the antifuse memory.

[0093] In some embodiments, referring to Figure 4 , the step of generating the programming pulse signal 100b in response to the row strobe signal 100a may include: simultaneously generating the programming pulse signal 100b in response to the row strobe signal 100a and the reference pulse signal 100d, and the duty cycle of the reference pulse signal 100d is adjustable. Since the duty cycle of the reference pulse signal 100d is adjustable, the duty cycle of the programming pulse signal 100b can also be adjusted by adjusting the duty cycle of the reference pulse signal 100d.

[0094] In other embodiments, the step of generating the programming pulse signal 100b in response to the row strobe signal 100a may include: generating a programming pulse signal 100b with an adjustable duty cycle in response to the row strobe signal 100a.

[0095] Among them, forming the programming pulse signal 100b based on the row strobe signal 100a can be implemented by the ring oscillator circuit 104. The specific implementation method is the same as that of the foregoing embodiment and will not be elaborated herein.

[0096] In the above embodiments, the duty cycle of the programming pulse signal 100b is adjustable, which is beneficial to enabling anti-fuse memory cells with different electrical properties to be programmed based on the programming pulse signal 100b, thereby facilitating improving the accuracy of reading data from the anti-fuse memory and the yield of the anti-fuse memory.

[0097] In summary, the anti-fuse memory generates the programming pulse signal 100b in response to the row strobe signal 100a and performs programming in response to the programming pulse signal 100b, which is beneficial to avoiding overheating problems after the anti-fuse memory is broken down. On the one hand, it is beneficial to reducing the probability of damage to the anti-fuse memory to improve the yield of the anti-fuse memory; on the other hand, it is beneficial to reducing the resistance of the anti-fuse memory in the low-resistance state after being broken down, thereby facilitating improving the success rate of reading the anti-fuse memory to improve the accuracy of reading data from the anti-fuse memory.

[0098] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. An anti-fuse memory, characterized in that, Comprising: The antifuse memory is configured to generate a programming pulse signal based on a row strobe signal. A word line of the antifuse memory array receives the row strobe signal, and the antifuse memory array is programmed in response to the programming pulse signal. The antifuse memory is further configured to generate the programming pulse signal with an adjustable duty cycle based on the row strobe signal. Further comprising: a pulse signal generation module, which receives the row strobe signal and generates the programming pulse signal. The pulse signal generation module includes: A signal generation unit, which outputs an initial pulse signal in response to the row strobe signal. A level converter, which is used to perform level conversion on the initial pulse signal to generate and output the programming pulse signal, and the level value of the programming pulse signal is greater than the level value of the initial pulse signal.

2. The antifuse memory according to claim 1, wherein The antifuse memory is further configured to generate the programming pulse signal based on the row strobe signal and a reference pulse signal.

3. The antifuse memory according to claim 2, wherein, The reference pulse signal is an internal clock signal.

4. The antifuse memory according to claim 2, wherein, The antifuse memory includes: a reference pulse signal generation module, which is configured to output the reference pulse signal with an adjustable duty cycle.

5. The antifuse memory according to claim 1, characterized in that, The signal generation unit simultaneously responds to the row strobe signal and the reference pulse signal to output the initial pulse signal.

6. The antifuse memory according to claim 5, characterized in that, The duty cycle of the reference pulse signal is adjustable.

7. The antifuse memory according to claim 1, wherein, The signal generation unit includes: a ring oscillator circuit, and the row strobe signal is an enable signal of the ring oscillator circuit, and an output end of the ring oscillator circuit outputs the initial pulse signal.

8. The antifuse memory according to claim 7, wherein The ring oscillator circuit is configured to output the initial pulse signal with an adjustable duty cycle.

9. The antifuse memory according to claim 8, wherein, The ring oscillator circuit includes: A comparison circuit, and an output end of the comparison circuit outputs the initial pulse signal. A pull-up module, which is connected between a working power supply and an input end of the comparison circuit, is turned on in response to the row strobe signal and a first level signal output by the comparison circuit, and pulls up the voltage of the input end of the comparison circuit at a first rate, and the first rate is adjustable. A pull-down module, which is connected between a ground terminal and the input end of the comparison circuit, is turned on in response to the row strobe signal and a second level signal output by the comparison circuit, and pulls down the voltage of the input end of the comparison circuit at a second rate, and the second rate is adjustable. The level values of the first level signal and the second level signal are different.

10. The antifuse memory according to claim 9, characterized in that, The pull-up module includes a first current source and a first switch module. The first switch module is connected between the first current source and the input end of the comparison circuit, and the first switch module is turned on in response to the row strobe signal and the first level signal. The pull-down module includes a second current source and a second switch module. The second switch module is connected between the second current source and the input end of the comparison circuit, and the second switch module is turned on in response to the row strobe signal and the second level signal, and the current magnitude of the first current source and / or the second current source is adjustable.

11. The antifuse memory according to claim 10, characterized in that, The comparison circuit includes a comparator and a second inverter connected in series with the comparator, and the output end of the second inverter outputs the initial pulse signal; The first switch module includes a first switch transistor and a second switch transistor connected in series. The first current source is connected between the first switch transistor and the working power supply. The control end of the second switch transistor is connected to the output end of the second inverter, and the first switch transistor is turned on in response to the row strobe signal; The second switch module includes a third switch transistor and a fourth switch transistor connected in series. The second current source is connected between the fourth switch transistor and the ground terminal. The control end of the third switch transistor is connected to the output end of the second inverter, and the fourth switch transistor is turned on in response to the row strobe signal.

12. The antifuse memory according to claim 10, characterized in that, The antifuse memory further includes: a current adjustment module configured to adjust the current magnitude of the first current source and / or the second current source.

13. A control method for an anti-fuse memory, characterized in that, Comprising: Generating a programming pulse signal in response to a row strobe signal; Performing programming in response to the programming pulse signal; The generating the programming pulse signal in response to the row strobe signal includes: generating the programming pulse signal with an adjustable duty cycle in response to the row strobe signal; The generating the programming pulse signal in response to the row strobe signal further includes: outputting an initial pulse signal in response to the row strobe signal; performing a level conversion on the initial pulse signal to generate and output the programming pulse signal, and the voltage value of the programming pulse signal is greater than the voltage value of the initial pulse signal.

14. The control method according to claim 13, wherein, The generating the programming pulse signal in response to the row strobe signal includes: generating the programming pulse signal in response to the row strobe signal and a reference pulse signal simultaneously, and the duty cycle of the reference pulse signal is adjustable.

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