Memory access method, device, memory, equipment and storage medium

Abstract

The present disclosure provides a memory access method, apparatus, memory, device, and storage medium, relating to the field of memory technology. The method includes: obtaining location information of failed bits in multiple arrays, using a patching algorithm to allocate a backup circuit to a target array in the multiple arrays based on the location information of the failed bits, obtaining a predicted patching result for the target array, performing a validity check on the target array based on the predicted patching result, obtaining information indicating whether a bit of a target partial address bit of the target array is predicted to be valid or invalid, and then determining a predicted partial address bit from multiple address bits based on the information of the target partial address bit of the target array, so as to access the memory using a partial access mode based on the predicted partial address bit. This method can quickly determine the portion to be accessed using the partial mode, effectively improving the yield of memory products.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory access method, apparatus, memory, storage device, and computer-readable storage medium. Background Art

[0002] Due to the limitations of the process technology and design of early DRAM production lines, product yields were typically low. Even when a wafer was used for DRAM production, repairing the DRAM product to recover some of its failed bits was possible. However, many DRAM products could not recover all of their failed bits, preventing the number of good chips from reaching the required product yield standard. This resulted in too few good chips per wafer, making mass production impossible.

[0003] The related art uses a partial mode to access the memory, accessing only a portion of the bits in the entire memory and shutting down the rest. However, when using the partial mode access, it is impossible to quickly determine which part of the bits in the memory are accessed, resulting in a low yield of the memory product.

[0004] As described above, how to quickly determine the effective portion of the memory to improve the yield of the memory product has become an urgent problem to be solved.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a memory access method, apparatus, device and readable storage medium, which can quickly determine the valid part of the memory to access the memory using a partial mode, thereby improving the yield of the memory product.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a memory access method is provided, comprising: the memory comprising a plurality of arrays, each of the plurality of arrays comprising a plurality of address bits, the plurality of arrays comprising a failed bit, each of the plurality of address bits comprising at least two partial address bits, the method comprising: obtaining position information of the failed bits in the plurality of arrays; employing a patching algorithm to allocate a spare circuit to a target array in the plurality of arrays according to the position information of the failed bit, and obtaining a predicted patching result of the target array; performing a validity check on the target array according to the predicted patching result of the target array, and obtaining information of a target partial address bit of the target array, wherein the partial address bits of the plurality of address bits of the target array include the target partial address bit; determining a predicted partial address bit from the plurality of address bits according to the information of the target partial address bit of the target array, so as to access the memory in a partial access mode according to the predicted partial address bit, wherein the bit prediction of the predicted partial address bit of the respective arrays is valid.

[0009] According to some embodiments of the present disclosure, the method further includes: obtaining a validity detection range, the validity detection range including at least one address bit to be detected among the multiple address bits; performing a validity detection on the target array according to the predicted patch result of the target array, including: judging whether the bits of some address bits of the address bits to be detected of the target array are the bits predicted to be successfully patched based on the validity detection range and the predicted patch result of the target array; if the bits of some address bits of the address bits to be detected of the target array are the bits predicted to be successfully patched, determining that the some address bits of the address bits to be detected of the target array are the target some address bits of the target array.

[0010] According to some embodiments of the present disclosure, a patching algorithm is used to allocate a spare circuit to a target array among the multiple arrays based on the position information of the failed bits, including: obtaining the position information of the failed bits in the target array from the position information of the failed bits in the multiple arrays; obtaining information about the spare circuit of the target array; and using the position information of the failed bits in the target array and the information about the spare circuit of the target array as input information, and using the patching algorithm to allocate the spare circuit to the target array.

[0011] According to some embodiments of the present disclosure, a patching algorithm is used to allocate a spare circuit to a target array among the multiple arrays based on the position information of the failed bits, and the method further includes: obtaining a patching rule corresponding to the memory; taking the position information of the failed bits in the target array and the information of the spare circuit of the target array as input information, and using the patching algorithm to allocate the spare circuit to the target array, including: taking the position information of the failed bits in the target array, the information of the spare circuit of the target array, and the patching rule corresponding to the memory as input information, and using the patching algorithm to allocate the spare circuit to the target array.

[0012] According to some embodiments of the present disclosure, the target array includes multiple global domains, and the global domain includes multiple subdomains; the spare circuits include global spare circuits and subdomain spare circuits, and the information of the spare circuits of the target array includes the number of global spare circuits and the number of subdomain spare circuits of the target array; a patching algorithm is used to assign spare circuits to the target array in the multiple arrays according to the position information of the failed bits, and a predicted patching result of the target array is obtained, including: taking the position information of the failed bits in the target array and the number of global spare circuits and the number of subdomain spare circuits of the target array as input information, and using the patching algorithm to assign the global spare circuits and the subdomain spare circuits to the target array, and obtaining a predicted patching result of each of the global domains of the target array, wherein the predicted patching result of the global domain is a prediction that the global spare circuits and subdomain spare circuits assigned to the global domain are completely covered and patched, or a prediction that the global spare circuits and subdomain spare circuits not assigned to the global domain are completely covered and patched.

[0013] According to some embodiments of the present disclosure, a validity check is performed on the target array based on a predicted patch result of the target array to obtain information about a target portion of address bits of the target array, including: if, for each of the global domains of the target array, the predicted patch result is that the global domain spare circuit and the subdomain spare circuit allocated to the global domain are predicted to completely cover the patch, then the validity check result of the target array is obtained as the target array is predicted to be valid, and the target array prediction valid indicates that the bit prediction of a portion of the multiple address bits of the target array is valid.

[0014] According to some embodiments of the present disclosure, a validity check is performed on the target array based on a predicted patch result of the target array to obtain information about a target partial address bit of the target array, including: obtaining the address bits to be detected of the target array; if the predicted patch result of the global domain where the partial address bits of the address bits to be detected of the target array are located is that the global domain spare circuits and sub-domain spare circuits assigned to the global domain are predicted to be completely covered and patched, then the partial address bits of the address bits to be detected of the target array are obtained as the target partial address bits.

[0015] According to some embodiments of the present disclosure, a validity check is performed on the target array based on a predicted patch result of the target array to obtain information about a target portion of address bits of the target array, including: if, for each of the global domains of the target array, the predicted patch result is that the global domain spare circuit and the subdomain spare circuit that are not assigned to the global domain are completely covered and patched, then the validity check result of the target array is obtained as invalid target array prediction, where the invalid target array prediction indicates that bit predictions for some of the multiple address bits of the target array are invalid.

[0016] According to some embodiments of the present disclosure, the method further includes: obtaining a validity detection range, the validity detection range including at least one address bit to be detected among the multiple address bits; the target array includes each array among the multiple arrays; based on the information of the target partial address bits of the target array, determining the predicted partial address bits from the multiple address bits, including: based on the information of the target partial address bits of the each array, judging whether the bits of the partial address bits of the address bits to be detected of the each array are predicted to be valid; if the bits of the partial address bits of the address bits to be detected of the each array are predicted to be valid, determining that the partial address bits of the address bits to be detected are the predicted partial address bits.

[0017] According to some embodiments of the present disclosure, based on information of the target partial address bits of the target array, the predicted partial address bits are determined from the multiple address bits, and the method further includes: if the multiple arrays include an array in which the bit prediction of the partial address bits of the address bits to be detected is invalid, then the partial address bits of the address bits to be detected are not determined to be the predicted partial address bits.

[0018] According to some embodiments of the present disclosure, each address bit of the plurality of address bits includes two partial address bits, and for each array of the plurality of arrays, the two partial address bits of each address bit of the array have the same bit capacity.

[0019] According to another aspect of the present disclosure, a memory is provided, comprising a plurality of arrays, each of the plurality of arrays comprising a plurality of address bits, the plurality of arrays comprising a failed bit, each of the plurality of address bits comprising at least two partial address bits, and any of the above methods being used when accessing the memory.

[0020] According to another aspect of the present disclosure, a memory access device is provided, wherein the memory includes multiple arrays, each of the multiple arrays includes multiple address bits, the multiple arrays include failed bits, and each of the multiple address bits includes at least two partial address bits. The device includes: an acquisition module for acquiring position information of the failed bits in the multiple arrays; a patching module for allocating a spare circuit to a target array in the multiple arrays based on the position information of the failed bits using a patching algorithm, thereby obtaining a predicted patching result for the target array; an array detection module for performing validity detection on the target array based on the predicted patching result of the target array, thereby obtaining information about target partial address bits of the target array, wherein some of the multiple address bits of the target array include the target partial address bits, and the information about the target partial address bits of the target array is used to indicate whether a bit prediction of the target partial address bits of the target array is valid or invalid; and a memory prediction module for determining a predicted partial address bit from the multiple address bits based on the target partial address bit information, thereby accessing the memory in a partial access mode based on the predicted partial address bit, wherein the bit prediction of the predicted partial address bits of each array is valid.

[0021] According to some embodiments of the present disclosure, the array detection module is further used to: obtain a validity detection range, the validity detection range including at least one address bit to be detected among the multiple address bits; determine whether the bits of some address bits of the address bits to be detected of the target array are the bits predicted to be successfully repaired based on the validity detection range and the predicted repair result of the target array; if the bits of some address bits of the address bits to be detected of the target array are the bits predicted to be successfully repaired, then determine that the some address bits of the address bits to be detected of the target array are the target some address bits of the target array.

[0022] According to some embodiments of the present disclosure, the patching module is further configured to: obtain position information of failed bits in the target array from position information of failed bits in the multiple arrays; obtain information about a spare circuit of the target array; and use the position information of failed bits in the target array and the information about the spare circuit of the target array as input information to allocate the spare circuit to the target array using the patching algorithm.

[0023] According to some embodiments of the present disclosure, the patching module is further used to: obtain a patching rule corresponding to the memory; use the position information of the failed bit in the target array, the information of the spare circuit of the target array, and the patching rule corresponding to the memory as input information, and use the patching algorithm to allocate the spare circuit to the target array.

[0024] According to some embodiments of the present disclosure, the target array includes multiple global domains, and the global domains include multiple subdomains; the spare circuits include global spare circuits and subdomain spare circuits, and the information of the spare circuits of the target array includes the number of global spare circuits and the number of subdomain spare circuits of the target array; the patching module is also used to: take the position information of the failed bits in the target array and the number of global spare circuits and the number of subdomain spare circuits of the target array as input information, use the patching algorithm to assign the global spare circuits and the subdomain spare circuits to the target array, and obtain predicted patching results for each of the global domains of the target array, wherein the predicted patching results of the global domains are to predict that the global spare circuits and subdomain spare circuits assigned to the global domains are fully covered and patched, or to predict that the global spare circuits and subdomain spare circuits that are not assigned to the global domains are fully covered and patched.

[0025] According to some embodiments of the present disclosure, the array detection module is further configured to: if, for each of the global domains of the target array, a predicted repair result is that the global domain spare circuits and sub-domain spare circuits allocated to the global domain are predicted to be completely covered and repaired, then obtain a validity detection result of the target array as the target array is predicted to be valid, where the target array is predicted to be valid indicating that bits of some of the multiple address bits of the target array are predicted to be valid.

[0026] According to some embodiments of the present disclosure, the array detection module is further configured to: obtain the address bits to be detected of the target array; if a predicted repair result of the global domain where the partial address bits of the address bits to be detected of the target array are located is that the global domain spare circuits and sub-domain spare circuits allocated to the global domain are predicted to be completely covered and repaired, then the partial address bits of the address bits to be detected of the target array are obtained as the target partial address bits.

[0027] According to some embodiments of the present disclosure, the array detection module is further configured to: if, for each of the global domains of the target array, a predicted repair result is that the global spare circuits and sub-domain spare circuits that are not assigned to the global domain are completely covered and repaired, then a validity detection result of the target array is obtained as invalid target array prediction, where the invalid target array prediction indicates that bit predictions for some of the multiple address bits of the target array are invalid.

[0028] According to some embodiments of the present disclosure, the target array includes each array of the multiple arrays; the memory prediction module is further used to: obtain a validity detection range, the validity detection range includes at least one address bit to be detected among the multiple address bits; based on information of the target partial address bits of the respective arrays, determine whether the bits of the partial address bits of the address bits to be detected of the respective arrays are predicted to be valid; if the bits of the partial address bits of the address bits to be detected of the respective arrays are predicted to be valid, then determine that the partial address bits of the address bits to be detected are the predicted partial address bits.

[0029] According to some embodiments of the present disclosure, the memory prediction module is further configured to: if the plurality of arrays include an array in which bit predictions of some address bits of the address bits to be detected are invalid, then determine that the some address bits of the address bits to be detected are not the predicted some address bits.

[0030] According to some embodiments of the present disclosure, each address bit of the plurality of address bits includes two partial address bits, and for each array of the plurality of arrays, the two partial address bits of each address bit of the array have the same bit capacity.

[0031] According to another aspect of the present disclosure, a storage device is provided, comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor implements any of the above methods when executing the executable instructions.

[0032] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored. When the executable instructions are executed by a processor, any of the above methods is implemented.

[0033] The memory access method provided by the embodiments of the present disclosure obtains the position information of failed bits in multiple arrays, uses a patching algorithm to allocate a spare circuit to a target array in the multiple arrays according to the position information of the failed bits, obtains a predicted patching result of the target array, performs a validity check on the target array according to the predicted patching result of the target array, obtains information indicating whether the bit of the target partial address bit of the target array is predicted to be valid or invalid, and then determines the predicted partial address bit from multiple address bits according to the information of the target partial address bit of the target array, so as to access the memory in a partial access mode according to the predicted partial address bit, thereby quickly determining the portion to be accessed using the partial mode, and effectively improving the yield of the memory product.

[0034] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0036] Figure 1 A schematic diagram showing a system structure in an embodiment of the present disclosure.

[0037] Figure 2 The figure is a schematic diagram showing the structure of a memory according to an exemplary embodiment.

[0038] Figure 3 A flowchart of a memory access method in an embodiment of the present disclosure is shown.

[0039] Figure 4 Shown Figure 3 FIG. 5 is a schematic diagram of the processing process of step S304 in one embodiment.

[0040] Figure 5 is based on Figure 3 and Figure 4 A schematic diagram of an array repair method is shown.

[0041] Figure 6 Shown Figure 3 FIG. 5 is a schematic diagram of the processing process of step S306 in one embodiment.

[0042] Figure 7 according to Figure 4 Shown Figure 3 FIG. 5 is a schematic diagram of the processing process of step S306 in another embodiment.

[0043] Figure 8 is based on Figures 3 to 7 A schematic diagram of an array repair method is shown.

[0044] Figure 9 Shown Figure 3 FIG. 5 is a schematic diagram of the processing process of step S308 in one embodiment.

[0045] Figure 10 is based on Figures 3 to 9 A schematic diagram of an array repair method is shown.

[0046] Figure 11 is based on Figures 3 to 10 A flowchart of a method for predicting a partial memory access pattern is shown.

[0047] Figure 12 A block diagram of a memory access device according to an embodiment of the present disclosure is shown.

[0048] Figure 13 A schematic structural diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these examples are provided so that this disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures indicate identical or similar parts, and thus repeated descriptions thereof will be omitted.

[0050] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0051] Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. The symbol " / " generally indicates an "or" relationship between the preceding and following objects.

[0052] In this disclosure, unless otherwise specified or limited, terms such as "connected" should be interpreted broadly. For example, they can mean electrically connected or capable of mutual communication; they can be directly connected or indirectly connected through an intermediary. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0053] As mentioned above, the related art uses a partial mode to access the memory, accessing only a portion of the bits in the entire memory and shutting down the rest. For example, half of each bank can be selected as the access content, and the other half will not be accessed. For example, an 8GB partial mode can be executed on a 16GB chip, which means that the chip can be turned into a working qualified chip while sacrificing the 8GB capacity of the chip.

[0054] In this regard, the present disclosure provides a memory access method, which performs validity detection on a target array based on a predicted patch result of the target array, obtains information indicating whether a bit element of a target partial address bit of the target array is predicted to be valid or invalid, and then determines a predicted partial address bit from a plurality of address bits based on the information of the target partial address bit of the target array, so as to access a memory in a partial access mode based on the predicted partial address bit, thereby quickly determining a portion to be accessed using the partial mode, and effectively improving the yield of the memory product.

[0055] Figure 1 An exemplary system architecture 10 is shown to which the memory access method or memory access apparatus of the present disclosure may be applied.

[0056] like Figure 1 As shown, system architecture 10 may include terminal device 102, network 104, and server 106. Terminal device 102 may be any electronic device with a display screen and input and output support, including but not limited to smartphones, tablet computers, laptop computers, desktop computers, wearable devices, virtual reality devices, smart homes, and the like. Network 104 is a medium for providing a communication link between terminal device 102 and server 106. Network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables. Server 106 may be a server or server cluster that provides various services, such as a backend processing server, a database server, and the like.

[0057] A user can use terminal device 102 to interact with server 106 via network 104 to receive or send data, etc. For example, a user can download location information of failed bits in multiple arrays of multiple memories from server 106 via network 104 to terminal device 102, which can then be used as input information for patching software running on terminal device 102. For another example, a user can operate on terminal device 102 to have array testing software running on terminal device 102 transmit predicted patch results for a target array to server 106 via network 104, allowing server 106 to perform a validity test on the target array based on the predicted patch results.

[0058] It should be understood that Figure 1 The number of terminal devices, networks and servers in the embodiment is merely illustrative. Any number of terminal devices, networks and servers may be provided as required.

[0059] Figure 2 FIG. 1 is a schematic diagram showing the structure of a memory according to an exemplary embodiment. Figure 2 The method provided by the embodiment of the present disclosure can be used when the memory is used. Figure 2As shown, the memory may include multiple arrays, each of which may serve as a target array, for example Figure 2 The memory includes 16 arrays including target array 0, target array 1, target array 2, ..., target array 6, target array 7, ..., target array 15.

[0060] For each array in the plurality of arrays, each array may include a plurality of address bits Xn, where n may be an integer greater than or equal to 0. Each address bit in the plurality of address bits may include at least two partial address bits, such as an address bit Xn may include a word line (Word Line) of a first partial address bit Xn=0 and a word line (Word Line) of a first partial address bit Xn=1, wherein the word line of the array is perpendicular to the direction of the bit line (Bit Line). Figure 2 As shown, taking the target array 15 as an example, the target array 15 may include 16 address bits, such as X0, X1, ..., X14, and X15. Each address bit may include two partial address bits. For example, the X0 address bit includes X0=0 and X0=1, the X14 address bit includes X14=0 and X14=1, and the X15 address bit includes X15=0 and X15=1, etc., where 0 and 1 may be flag bits. An X-direction decoder 208 may be provided between the bits of the partial address bits with a flag bit of 0 and the bits of the partial address bits with a flag bit of 1.

[0061] In some embodiments, for each array in the plurality of arrays, the bit capacity of the two partial address bits of each address bit of the array is the same.

[0062] In some embodiments, the X address bit may be set as a basis for selecting the partial access mode. For example, setting the address bit X15=0 indicates that when accessing the memory, the X15 address bit only accesses the portion where X15=0.

[0063] Multiple arrays may include failed bits. In some embodiments, each target array may include failed bits that need to be repaired by a repair algorithm.

[0064] The memory may further include a sense amplifier / Y-direction decoder 202 , a fuse control / row control circuit 204 , and a peripheral device 206 for implementing operations such as read / write access to the memory.

[0065] Figure 3 FIG. 1 is a flow chart showing a memory access method according to an exemplary embodiment. Figure 3 The method shown can be applied, for example, to access Figure 2 The memory shown can be Figure 1It is implemented by the terminal device and / or server of the system.

[0066] refer to Figure 3 , the method 30 provided in the embodiment of the present disclosure may include the following steps.

[0067] In step S302 , location information of failed bits in a plurality of arrays is obtained.

[0068] In some embodiments, the location information of failed bits of all memory chips generated by a wafer tester may be obtained, and the location information of failed bits of each array of each memory may be further obtained.

[0069] In step S304 , a repair algorithm is used to allocate spare circuits to a target array among the multiple arrays according to the location information of the failed bits, so as to obtain a predicted repair result of the target array.

[0070] In some embodiments, the modular repair algorithm unit can be used to input the location information of the failed bit of the target array into the repair algorithm unit, and then output the predicted repair result of the target array. For specific implementation, please refer to Figure 4 and Figure 5 .

[0071] In step S306 , the target array is tested for validity according to the predicted patching result of the target array to obtain information of a target partial address bit of the target array, where a partial address bit of the plurality of address bits of the target array includes the target partial address bit.

[0072] In some embodiments, the information of the target partial address bits of the target array is used to indicate whether the bit prediction of the target partial address bits of the target array is valid or invalid.

[0073] In some embodiments, a target array validity detection algorithm can be used to perform validity detection on an array basis, and each target array (e.g., Figure 8 Validity detection is performed by the method of detecting whether the address bit can be repaired. The specific implementation method can be referred to Figures 6 to 8 .

[0074] In step S308, predicted partial address bits are determined from a plurality of address bits according to information of the target partial address bits of the target array, so as to access the memory in a partial access mode according to the predicted partial address bits, wherein the bit prediction of the predicted partial address bits of each array is valid.

[0075] In some embodiments, for example, it is possible to determine whether the bits of the partial address bits in the validity detection range are predicted to be valid according to the information of the target partial address bits of the target array according to the defined validity detection range, so as to determine the predicted partial address bits from the multiple address bits. For specific implementations, please refer to Figures 9 and 10 .

[0076] In some embodiments, each array of the memory can be used as a target array, and each array is processed in turn according to step S306 and step S308 to obtain the predicted partial address bits, so as to obtain all the predicted partial address bits of the memory. For a specific implementation, please refer to Figure 11 .

[0077] According to the memory access method provided by the embodiment of the present disclosure, position information of failed bits in multiple arrays is obtained, a repair algorithm is used to allocate spare circuits to a target array in the multiple arrays according to the position information of the failed bits, a predicted repair result of the target array is obtained, and the target array is tested for validity according to the predicted repair result of the target array, and information indicating whether the bit of the target partial address bit of the target array is predicted to be valid or invalid is obtained. Then, based on the information of the target partial address bit of the target array, the predicted partial address bit is determined from the multiple address bits, so that the memory is accessed in a partial access mode according to the predicted partial address bit, thereby quickly determining the portion to be accessed using the partial mode, and effectively improving the yield of the memory product.

[0078] The memory access method provided by the embodiments of the present disclosure can quickly determine whether a currently unpatchable memory chip can be upgraded to a qualified chip by adopting partial mode access, thereby effectively improving product yield; and can predict the potential partial mode configuration of the current product, thereby effectively reducing R&D costs.

[0079] Figure 4 Shown Figure 3 FIG. 1 is a schematic diagram of the processing process of step S304 in one embodiment. Figure 4 As shown, in the embodiment of the present disclosure, the above step S304 may further include the following steps. Figure 4 The method steps shown can be Figure 5 The patching algorithm unit 502 is executed.

[0080] In step S402 , the position information of the failed bits in the target array is obtained from the position information of the failed bits in the plurality of arrays.

[0081] Step S404: Acquire information about the backup circuit of the target array.

[0082] In some embodiments, the target array may include multiple global domains, which may include multiple subdomains; the spare circuits may include global domain spare circuits and subdomain spare circuits, and the spare circuit information of the target array may include the number of global domain spare circuits and the number of subdomain spare circuits of the target array. Figure 5For example, the number of global spare circuits and the number of sub-domain spare circuits of the target array may be input into the patching algorithm unit 502 as product patching parameters 5004 .

[0083] In some embodiments, patching rules corresponding to the memory may be obtained, such as common patching and cross-region patching rules, and may also be input into the patching algorithm unit 502 as product patching parameters 5004 .

[0084] In step S406 , the location information of the failed bit in the target array and the information of the spare circuit of the target array are used as input information, and a repair algorithm is used to allocate a spare circuit for the target array.

[0085] In some embodiments, the position information of failed bits in the target array, the information of the backup circuits of the target array, and the patching rules corresponding to the memory can be used as input information, and a patching algorithm can be used to assign backup circuits to the target array. The patching algorithm is an algorithm that can effectively assign backup circuits so that they completely cover the failed bit positions. For example, the position information of failed bits in the target array and the number of global backup circuits and the number of sub-domain backup circuits of the target array can be used as input information, and a patching algorithm can be used to assign global backup circuits and sub-domain backup circuits to the target array to obtain predicted patching results for each global domain of the target array, wherein the predicted patching result of the global domain is that the global backup circuits and sub-domain backup circuits assigned to the global domain are completely covered and patched, that is, the failed bits in the global domain can be successfully and completely covered and patched by the limited backup circuits; or the global backup circuits and sub-domain backup circuits that are not assigned to the global domain are completely covered and patched, which is a failed global domain. The target array to which the failed global domain belongs can also be designated as a failed array.

[0086] Figure 5 is based on Figure 3 and Figure 4 The schematic diagram of an array patching method is shown in FIG. Figure 5 As shown, the patching algorithm unit 502 may include an input parameter module 5022 and an allocation algorithm module 5024. Because the allocation process of the entire area and sub-area of ​​any array does not affect other areas, each array may enter the allocation algorithm module 5024 for spare circuit allocation processing in turn.

[0087] The input parameter module 5022 can be used to obtain product repair parameters 5004. The product repair parameters 5004 can include Figure 4The number of global spare circuits and sub-domain spare circuits of the target array, as well as the patching rules corresponding to the memory in which the target array resides, can be determined by the allocation algorithm module 5024. The allocation algorithm module 5024 can be used to obtain the failed bit position 5002 and then use the patching algorithm to allocate the global spare circuits and sub-domain spare circuits to the target array, thereby obtaining predicted patching results for each global domain of the target array.

[0088] Figure 6 Shown Figure 3 FIG. 1 is a schematic diagram of the processing process of step S306 in one embodiment. Figure 6 As shown, in the embodiment of the present disclosure, the above step S306 may further include the following steps.

[0089] Step S602: Acquire a validity detection range, where the validity detection range includes at least one address bit to be detected among the plurality of address bits.

[0090] In some embodiments, for example, a specific detection position can be input by a user, with reference to Figure 2 The detection position may be, for example, X15, and the validity detection range is the address bit to be detected X15, which includes part of the address bit, for example, two partial address bits to be detected, X15=0 and X15=1.

[0091] In other embodiments, for example, the user may input a location detection range of the feasibility of a portion of the access pattern to be predicted, referring to Figure 2 The detection range may be, for example, multiple address bits in X0-X15, such as X0, X14, X15, or X3-X10, etc.

[0092] Step S604 : determining whether bits of some of the to-be-detected address bits of the target array are bits predicted to be successfully repaired based on the validity detection range and the predicted repair result of the target array.

[0093] In some embodiments, whether the address bits to be detected belong to the valid full domain of the predicted patching result of the target array can be used to determine whether the bits of the address bits to be detected of the target array are the bits predicted to be successfully patched. For a specific implementation, please refer to Figure 7 .

[0094] In step S606 , if the bits of the partial address bits of the target array to be detected are bits predicted to be successfully patched, the partial address bits of the target array to be detected are determined as target partial address bits of the target array.

[0095] In some embodiments, if the bits of the partial address bits of the target array's address bits to be detected are not bits predicted to be successfully patched, the partial address bits of the target array's address bits to be detected are not determined to be the target partial address bits of the target array, and the determination of the next address bit to be detected in the validity detection range is continued.

[0096] Figure 7 according to Figure 4 Shown Figure 3 FIG. 1 is a schematic diagram of the processing process of step S306 in another embodiment. Figure 7 As shown, in the embodiment of the present disclosure, the above step S306 may further include the following steps.

[0097] In step S702, if the predicted repair result for each global region of the target array is that the allocated global spare circuits and sub-region spare circuits of the global region are completely covered and repaired, then the target array validity check result is obtained as the target array is predicted to be valid. The target array is predicted to be valid, indicating that some of the multiple address bits of the target array are predicted to be valid.

[0098] In some embodiments, if the entire target array is repairable, res=0 may be added to the result file, which may be Figure 8 The validity check result obtained in step S806 may be, for example, [0], which indicates that the bit prediction of some address bits of each address bit of the target array is valid (ie, patchable and accessible).

[0099] Step S7042: Obtain the address bits to be detected of the target array.

[0100] In step S7044, if the predicted patching result of the global region where the partial address bits of the target array's address bits to be detected are located is that the global spare circuits and sub-region spare circuits allocated to the global region are completely covered and patched, then the partial address bits of the target array's address bits to be detected are obtained as target partial address bits.

[0101] In some embodiments, if not the entire target array is repairable, it is possible to determine whether the entire domain where the partial address bits of the address bits to be detected are located is valid (i.e., repairable) based on the predicted repair result. If valid, it is determined that the partial address bits of the address bits to be detected are the target partial address bits that can be repaired. For example, if X15=0 is determined to be repairable, res=150 can be added to the result file, otherwise not added; if X15=1 is repairable, res=151 can be added to the result file, otherwise not added. For another example, if X14=0 is determined to be repairable, res=140 is added to the result file, otherwise not added; if X14=1 is determined to be repairable, res=141 is added to the result file, otherwise not added. The result file can be Figure 8 The type of validity detection results obtained in step S806 shown may be, for example,

[150] ,

[140] , or

[141] .

[0102] In step S706, if the predicted patching result for each global region of the target array is that the global spare circuits and sub-region spare circuits that are not assigned to the global region are completely patched, then the target array validity check result is obtained as invalid target array prediction. Invalid target array prediction indicates that the bit predictions of some of the multiple address bits of the target array are invalid.

[0103] In some embodiments, if the entire target array is unrepairable, res=-1 may be added to the result file, which may be Figure 8 One type of validity check result obtained in step S806 may be, for example, [-1], which indicates that the bit prediction of some address bits of the target array is invalid (ie, cannot be repaired or accessed).

[0104] Figure 8 is based on Figures 3 to 7 The schematic diagram of an array detection method is shown in FIG. Figure 8 As shown, for each target array, after obtaining the position 8002 of the target array failure bit to be detected, the validity detection range is first defined (S802). The specific implementation method can refer to step S602. Then, the failure information is updated (S804). By traversing the validity detection range, the spare circuit and failure bit used in the previous repair are restored during each detection to truly detect the repairability of the current detection. When the entire array is repairable, no update is required. Then, the spare circuit is allocated by the repair algorithm unit 502 to obtain the predicted repair result of the target array. The specific implementation method can refer to Figure 4 and Figure 5 ; Then classify the validity test results of the target array according to the predicted patch results. The validity test result file obtained can contain the following contents: [0], [-1] and [Xn+0 / 1]. For specific implementation methods, please refer to Figure 7 .

[0105] Figure 9 Shown Figure 3 The processing diagram of step S308 in one embodiment is shown in FIG. Figure 9 In the embodiment, each of the plurality of arrays of the memory is a target array that has undergone validity detection. Figure 9 As shown, in the embodiment of the present disclosure, the above step S308 may further include the following steps.

[0106] Step S902 : obtaining a validity detection range, where the validity detection range includes at least one address bit to be detected among the plurality of address bits.

[0107] In some embodiments, obtaining the validity detection range may refer to step S602 , where the address bits to be detected in the validity detection range are candidate address bits of the predicted partial address bits of each array of the memory.

[0108] Step S904 : judging whether the bits of the partial address bits to be detected of each array are predicted to be valid according to the information of the target partial address bits of each array.

[0109] In step S9062 , if the bit prediction of the partial address bits of the address bits to be detected in each array is valid, the partial address bits of the address bits to be detected are determined to be the predicted partial address bits.

[0110] In step S9064 , if the plurality of arrays include an array in which the bit prediction of the partial address bits of the address bits to be detected is invalid, the partial address bits of the address bits to be detected are not determined to be the predicted partial address bits.

[0111] In some embodiments, reference Figure 2 , taking the address to be detected as X15, we can loop through each bank as follows Figure 8 The result file obtained by the array detection algorithm shown is referenced Figure 7 If 150 exists in the result file of the mth (m is a positive integer) array bank (m), it is determined that the partial enabling of X15=0 is feasible (that is, the bit prediction of X15=0 of bank (m) is valid), and res_bank(m)=1 is obtained; if 0 exists in the result file of bank (m), it is determined that the partial enabling of X15=0 is feasible, and res_bank(m)=1 is obtained; otherwise, the partial enabling of X15=0 of bank (m) is not feasible, and res_bank(m)=0 is obtained.

[0112] Then, the result res of each bank in the memory can be ANDed. If the result of the ANDed operation is equal to 1, it means that the X15=0 partial enabling of the memory is feasible, and the partial address bits of the address bits to be detected are determined to be the predicted partial address bits; if the result of the ANDed operation is equal to 0, it means that the X15=0 partial enabling of the memory is not feasible, and the partial address bits of the address bits to be detected are determined to be the predicted partial address bits.

[0113] Figure 10 is based on Figures 3 to 9 The schematic diagram of an array patching method is shown in FIG. Figure 10 As shown, first input memory failure bit position information 10002, and each array of the memory is obtained through the target array validity detection algorithm 10004. Figure 8 The test result obtained in step S806 is then Figure 9 The multi-array decision is made (S1002), and then the prediction result of the memory is output (S1004).

[0114] The prediction result of the memory can obtain the judgment result (S10042) and the prediction result (S10044). The judgment result (S10042) can determine whether the specific detection position selected by the user (for example, X15=0) is partially enabled according to the input detection range. For details, please refer to Figure 9 If it is feasible, the judgment result output is "X15=0 partial enabling success"; if it is not feasible, the judgment result output is "X15=0 partial enabling failure".

[0115] The prediction result (S10044) can be sequentially traversed through the prediction range (e.g. X0-X14), and each bank is judged in turn.<X0=0> The validity test result res_bank(m) is ANDed and the validity of the memory is obtained.<X0=0> Partially enable feasibility; judge each bank in turn<X0=1> The validity test result res_bank(m) is ANDed to get the memory<X0=1> Partially enable feasibility; judge each bank in turn<X1=0> The validity test result res_bank(m) is ANDed to get the memory<X1=0> Partially enable feasibility; judge each bank in turn<X1=1> The validity test result res_bank(m) is ANDed to get the memory<X1=1> Partial enable feasibility; and so on to X14, outputting the partial enable configuration prediction of the memory, for example, it can be: X15=0, X13=1, X2=1, that is, these partial address bits are the predicted partial address bits of the memory.

[0116] Figure 11 is based on Figures 3 to 10 FIG. 1 is a flow chart of a method for predicting a partial memory access pattern. Figure 11 The memory portion access pattern prediction process shown may include the following steps.

[0117] Step S1102: The process starts.

[0118] Step S1104: Read all memories in sequence, for example, read current memory chip 0.

[0119] Step S1106. Read all arrays of the current memory in sequence, and use the target array validity detection algorithm 10004 (refer to Figure 8) Obtain validity test results for each array based on the input failed bit position 11002, repair parameters 11004, and test range 11006. For example, the current array bank 0 of the current memory chip 0 may be read and bank 0 may be run through the target array validity test algorithm 10004 to obtain a validity test result for bank 0.

[0120] Step S1108. Determine whether all the current memories are invalid (unrepairable) based on the validity test results of each array of the current memory. If so, return to step S1104 and read the next memory, for example, the memory chip 1 next to the memory chip 0. If not, use the memory prediction algorithm 1102 (refer to Figure 10 ).

[0121] Step S1110: Output memory prediction results, which may include judgment result 11082 and prediction result 11084. Prediction result 11084 may be, for example: chip 0 partially enabled configuration prediction: X15=0, X13=1, X2=1; chip 1 partially enabled configuration prediction: X15=0, X12=1, X4=0.

[0122] Step S1112: Determine whether all memories have been read. If not, return to step S1104 and proceed to the next memory. If so, terminate the process (S11104). For example, if the current memory is chip 0, determine whether chip 1 exists. If so, the read is not complete, return to step S1104 and proceed to the next memory. If so, terminate the process (S11104).

[0123] The method provided by the disclosed embodiments modularizes the backup circuit algorithm, combining it with the array validity detection algorithm and the memory prediction algorithm to form a complete set of chip partial enablement configuration decision and prediction algorithms. This helps users quickly determine whether the currently selected specific test location can be configured as a partial mode, thereby enabling unqualified chips to be qualified through the partial mode. By inputting a test range, potential partial mode configurations for the current product are predicted. The partial enablement results of the current product line can provide a reference for the design of partial modes for the next generation of products.

[0124] In the case of poor yield, the method provided by the embodiments of the present disclosure can help quickly determine partial mode configurations and, through these modes, convert unrepairable chips into qualified chips, significantly improving product yield. Furthermore, DRAM factories can maximize chip utilization while significantly reducing production costs.

[0125] Figure 12FIG. 1 is a block diagram of a memory access device according to an exemplary embodiment. Figure 12 The device shown can be used, for example, to access Figure 2 The memory shown can be Figure 1 It is implemented by the terminal device and / or server of the system.

[0126] refer to Figure 12 The apparatus 120 provided by the embodiment of the present disclosure may include an acquisition module 1202 , a repair module 1204 , an array detection module 1206 and a memory prediction module 1208 .

[0127] The acquisition module 1202 may be configured to acquire location information of failed bits in a plurality of arrays.

[0128] The patching module 1204 may be configured to allocate spare circuits to a target array among the plurality of arrays according to the location information of the failed bits using a patching algorithm, and obtain a predicted patching result for the target array.

[0129] The patching module 1204 may also be configured to: obtain the location information of a failed bit in a target array from the location information of failed bits in multiple arrays; obtain information about a spare circuit in the target array; and allocate a spare circuit to the target array using a patching algorithm using the location information of the failed bit in the target array and the information about the spare circuit in the target array as input information.

[0130] The patching module 1204 can also be used to: obtain patching rules corresponding to the memory; use the location information of the failed bit in the target array, the information of the spare circuit of the target array and the patching rules corresponding to the memory as input information, and use the patching algorithm to allocate spare circuits for the target array.

[0131] The patching module 1204 may also be configured to: take the location information of failed bits in the target array and the number of global spare circuits and sub-domain spare circuits in the target array as input information, employ a patching algorithm to assign global spare circuits and sub-domain spare circuits to the target array, and obtain predicted patching results for each global domain of the target array, wherein the predicted patching results for the global domain include a prediction that the assigned global spare circuits and sub-domain spare circuits in the global domain are fully covered and patched, or a prediction that the unassigned global spare circuits and sub-domain spare circuits in the global domain are fully covered and patched.

[0132] The array detection module 1206 may be configured to perform validity detection on the target array based on the predicted patch result of the target array, and obtain information about target partial address bits of the target array, where some of the multiple address bits of the target array include the target partial address bits. The information about the target partial address bits of the target array is used to indicate whether the bit prediction of the target partial address bits of the target array is valid or invalid.

[0133] The array detection module 1206 may further be configured to: obtain a validity detection range, the validity detection range including at least one address bit to be detected from the plurality of address bits; determine, based on the validity detection range and according to the predicted patch result of the target array, whether bits of a portion of the address bits to be detected of the target array are bits predicted to be successfully patched; and if bits of the portion of the address bits to be detected of the target array are bits predicted to be successfully patched, determine that the portion of the address bits to be detected of the target array are target portion of the address bits of the target array.

[0134] The array detection module 1206 may also be configured to obtain a target array validity detection result as "target array predicted valid" if, for each global region of the target array, the predicted repair result indicates that the global spare circuits and sub-region spare circuits allocated to the global region are completely patched. The target array predicted valid indicates that bits of some of the multiple address bits of the target array are predicted valid.

[0135] The array detection module 1206 may further be configured to: obtain address bits to be detected of the target array; if the predicted patch result of the global region where the partial address bits of the address bits to be detected of the target array are located is that the global spare circuits and sub-region spare circuits allocated to the global region are completely covered and patched, then the partial address bits of the address bits to be detected of the target array are the target partial address bits.

[0136] The array detection module 1206 may also be configured to: if, for each global region of the target array, the predicted repair result is that the global spare circuits and sub-region spare circuits that are not assigned to the global region are completely covered and repaired, then obtain a target array validity detection result of "target array prediction invalid," where the target array prediction invalid indicates that the bit predictions for some of the multiple address bits of the target array are invalid.

[0137] The memory prediction module 1208 may be configured to determine predicted partial address bits from a plurality of address bits based on information of target partial address bits of a target array, so as to access a memory in a partial access mode based on the predicted partial address bits, wherein bit predictions of the predicted partial address bits of each array are valid.

[0138] The memory prediction module 1208 may also be configured to: obtain a validity detection range, the validity detection range including at least one address bit to be detected from a plurality of address bits; determine, based on information about target partial address bits of each array, whether bits of the partial address bits of the address bits to be detected of each array are predicted to be valid; and if bits of the partial address bits of the address bits to be detected of each array are predicted to be valid, determine that the partial address bits of the address bits to be detected are predicted partial address bits.

[0139] The memory prediction module 1208 may also be configured to determine that the partial address bits of the address bits to be detected are the predicted partial address bits if the plurality of arrays include an array whose bit prediction of the partial address bits of the address bits to be detected is invalid.

[0140] The specific implementation of each module in the device provided by the embodiment of the present disclosure can refer to the content of the above method and will not be repeated here.

[0141] Figure 13 FIG. 1 shows a schematic diagram of the structure of a storage device in an embodiment of the present disclosure. It should be noted that: Figure 13 The device shown is only an example of a computer system and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0142] like Figure 13 As shown, the device 1300 includes a central processing unit (CPU) 1301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1302 or a program loaded from a storage portion 1308 into a random access memory (RAM) 1303. Various programs and data required for the operation of the device 1300 are also stored in the RAM 1303. The CPU 1301, the ROM 1302, and the RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0143] The following components are connected to the I / O interface 1305: an input section 1306 including a keyboard, a mouse, and the like; an output section 1307 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 1308 including a hard disk; and a communication section 1309 including a network interface card such as a LAN card or a modem. The communication section 1309 performs communication processing via a network such as the Internet. A drive 1310 is also connected to the I / O interface 1305 as needed. Removable media 1311, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 1310 as needed, so that computer programs read therefrom can be installed into the storage section 1308 as needed.

[0144] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1309, and / or installed from a removable medium 1311. When the computer program is executed by the central processing unit (CPU) 1301, the above-mentioned functions defined in the system of the present disclosure are performed.

[0145] It should be noted that the computer-readable medium described in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical fiber cable, RF, or any suitable combination thereof.

[0146] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0147] The modules described in the embodiments of this disclosure may be implemented in software or hardware. The modules described may also be located within a processor. For example, they may be described as: an acquisition module, a repair module, an array detection module, and a memory prediction module. In some cases, the names of these modules do not limit the modules themselves. For example, the acquisition module may also be described as a "module for acquiring failed bit location information."

[0148] As another aspect, the present disclosure further provides a computer-readable medium, which may be included in the device described in the above embodiments; or may exist independently and not be incorporated into the device. The computer-readable medium carries one or more programs, and when the one or more programs are executed by the device, the device includes:

[0149] Obtaining position information of failed bits in a plurality of arrays; using a patching algorithm to allocate a spare circuit to a target array in the plurality of arrays according to the position information of the failed bits, and obtaining a predicted patching result of the target array; performing validity detection on the target array according to the predicted patching result of the target array, and obtaining information of a target partial address bit of the target array, wherein a partial address bit of a plurality of address bits of the target array includes the target partial address bit, and the information of the target partial address bit of the target array is used to indicate whether a bit prediction of the target partial address bit of the target array is valid or invalid; determining a predicted partial address bit from a plurality of address bits according to the information of the target partial address bit of the target array, so as to access a memory in a partial access mode according to the predicted partial address bit, wherein the bit prediction of the predicted partial address bit of each array is valid.

[0150] While the exemplary embodiments of the present disclosure have been specifically illustrated and described above, it should be understood that the present disclosure is not limited to the detailed structures, configurations, or implementations described herein; rather, the present disclosure is intended to encompass various modifications and equivalent configurations within the spirit and scope of the appended claims.

Claims

1. A memory access method, characterized in that: The memory includes a plurality of arrays, each of the plurality of arrays includes a plurality of address bits, the plurality of arrays includes a failed bit, each of the plurality of address bits includes at least two partial address bits, and the method includes: Obtaining position information of failed bits in the plurality of arrays; Using a repair algorithm to allocate a spare circuit to a target array among the plurality of arrays according to the position information of the failed bit, and obtaining a predicted repair result of the target array; Performing validity detection on the target array according to the predicted patching result of the target array to obtain information of a target partial address bit of the target array, where a partial address bit of a plurality of address bits of the target array includes the target partial address bit; According to information of the target partial address bits of the target array, predicted partial address bits are determined from the plurality of address bits to access the memory in a partial access mode according to the predicted partial address bits, wherein bit predictions of the predicted partial address bits of the respective arrays are valid.

2. The method according to claim 1, characterized in that Also includes: Acquire a validity detection range, where the validity detection range includes at least one address bit to be detected among the plurality of address bits; Performing validity detection on the target array according to the predicted repair result of the target array includes: Determining whether bits of some of the address bits to be detected of the target array are the bits predicted to be successfully repaired based on the validity detection range and the predicted repair result of the target array; If the bits of the partial address bits of the target array's address bits to be detected are the bits predicted to be successfully patched, the partial address bits of the target array's address bits to be detected are determined to be the target partial address bits of the target array.

3. The method according to claim 1, characterized in that Using a patching algorithm to allocate a spare circuit to a target array among the plurality of arrays according to the position information of the failed bit, comprising: Obtaining position information of the failed bit in the target array from the position information of the failed bits in the plurality of arrays; Acquiring information about a backup circuit of the target array; The position information of the failed bit in the target array and the information of the spare circuit of the target array are used as input information, and the spare circuit is allocated to the target array using the repair algorithm.

4. The method according to claim 3, characterized in that Using a repair algorithm to allocate a spare circuit to a target array among the plurality of arrays according to the position information of the failed bit, further comprising: Obtaining a patch rule corresponding to the memory; Taking the position information of the failed bit in the target array and the information of the spare circuit of the target array as input information, and using the patching algorithm to allocate the spare circuit to the target array, the method includes: The position information of the failed bit in the target array, the information of the spare circuit of the target array and the patching rule corresponding to the memory are used as input information, and the patching algorithm is used to allocate the spare circuit to the target array.

5. The method according to claim 3, characterized in that The target array includes a plurality of full domains, and the full domain includes a plurality of subdomains; The spare circuits include global spare circuits and sub-domain spare circuits, and the spare circuit information of the target array includes the number of global spare circuits and the number of sub-domain spare circuits of the target array; Using a repair algorithm to allocate a spare circuit to a target array among the plurality of arrays according to the position information of the failed bit to obtain a predicted repair result of the target array, including: The position information of the failed bits in the target array and the number of the global spare circuits and the number of the sub-domain spare circuits of the target array are used as input information, and the global spare circuits and the sub-domain spare circuits are assigned to the target array using the patching algorithm to obtain predicted patching results for each of the global domains of the target array, wherein the predicted patching results for the global domains are predicted to be fully covered and patched by the global spare circuits and the sub-domain spare circuits assigned to the global domains, or predicted to be fully covered and patched by the global spare circuits and the sub-domain spare circuits not assigned to the global domains.

6. The method according to claim 5, characterized in that Performing validity detection on the target array according to the predicted patch result of the target array to obtain information of a target portion of address bits of the target array includes: If, for each of the global domains of the target array, the predicted repair result is that the global domain spare circuits and sub-domain spare circuits assigned to the global domain are completely covered and repaired, then the validity detection result of the target array is obtained as the target array is predicted to be valid, and the target array is predicted to be valid, indicating that the bits of some of the multiple address bits of the target array are predicted to be valid.

7. The method according to claim 5, characterized in that Performing validity detection on the target array according to the predicted patch result of the target array to obtain information of a target portion of address bits of the target array includes: Obtaining the address bits to be detected of the target array; If the predicted repair result of the global domain where the partial address bits of the address bits to be detected of the target array are located is that the global domain spare circuits and sub-domain spare circuits assigned to the global domain are predicted to be completely covered and repaired, then the partial address bits of the address bits to be detected of the target array are obtained as the target partial address bits.

8. The method according to claim 5, characterized in that Performing validity detection on the target array according to the predicted patch result of the target array to obtain information of a target portion of address bits of the target array includes: If, for each of the global domains of the target array, the predicted repair result is that the global domain spare circuits and sub-domain spare circuits that are not assigned to the global domain are completely covered and repaired, then the validity check result of the target array is that the target array prediction is invalid, and the invalid target array prediction indicates that the bit predictions of some of the multiple address bits of the target array are invalid.

9. The method according to claim 1, characterized in that Also includes: Acquire a validity detection range, where the validity detection range includes at least one address bit to be detected among the plurality of address bits; The target array includes each array in the plurality of arrays; Determining predicted partial address bits from the plurality of address bits according to information of the target partial address bits of the target array includes: determining whether bits of a portion of the address bits to be detected of each array are predicted to be valid based on information of the target portion of the address bits of each array; If the bit prediction of the partial address bits of the address bits to be detected in each array is valid, the partial address bits of the address bits to be detected are determined to be the predicted partial address bits.

10. The method according to claim 9, characterized in that Determining predicted partial address bits from the plurality of address bits based on information of the target partial address bits of the target array, further comprising: If the plurality of arrays include an array in which the bit prediction of a portion of the address bits to be detected is invalid, the portion of the address bits to be detected is not determined to be the predicted portion of the address bits.

11. The method according to claim 1, wherein Each address bit of the plurality of address bits includes two partial address bits, and for each array of the plurality of arrays, the two partial address bits of each address bit of the array have the same bit capacity.

12. A memory, characterized in that: The method comprises a plurality of arrays, each of the plurality of arrays comprises a plurality of address bits, the plurality of arrays comprises a failed bit, each of the plurality of address bits comprises at least two partial address bits, and the method according to any one of claims 1 to 11 is used when accessing the memory.

13. A memory access device, characterized in that: The memory comprises a plurality of arrays, each of the plurality of arrays comprising a plurality of address bits, the plurality of arrays comprising a fail bit, each of the plurality of address bits comprising at least two partial address bits, the apparatus comprising: an acquisition module, configured to acquire position information of failed bits in the plurality of arrays; a patching module, configured to allocate a spare circuit to a target array among the plurality of arrays according to the position information of the failed bit using a patching algorithm, and obtain a predicted patching result of the target array; an array detection module, configured to perform validity detection on the target array according to the predicted patching result of the target array, and obtain information of a target partial address bit of the target array, where a portion of the plurality of address bits of the target array includes the target partial address bit, and the information of the target partial address bit of the target array is used to indicate whether a bit prediction of the target partial address bit of the target array is valid or invalid; A memory prediction module is configured to determine predicted partial address bits from the plurality of address bits based on information of target partial address bits of the target array, so as to access the memory in a partial access mode based on the predicted partial address bits, wherein bit predictions of the predicted partial address bits of each array are valid.

14. A storage device comprising: A memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor implements the method according to any one of claims 1 to 11 when executing the executable instructions.

15. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that: When the executable instructions are executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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