Corrective reads of memory devices with reduced latency

Abstract

This application relates to corrective reads of memory devices with reduced latency. The memory system can identify read errors based on access to the memory device and can select fine-tuning settings for performing corrective read operations based on data retention conditions associated with the accessed memory device. Such data retention conditions can be associated with data retention duration or cross-temperature conditions, and other criteria or combinations thereof. In some embodiments, the memory system can select from a subset of possible fine-tuning settings that can be associated with relevant process corners. For example, the memory system can select between a first fine-tuning setting associated with a relatively large cross-temperature and a relatively short data retention duration, and a second fine-tuning setting associated with a relatively small cross-temperature and a relatively long data retention duration.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 645,683, filed December 22, 2021, entitled "Corrective Read of a Memory Device with Reduced Latency," which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to corrective reads of memory devices with reduced latency. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: identify a read error based at least in part on receiving first information associated with a first read operation of the memory device from the memory device; select a fine-tuning setting from a plurality of fine-tuning settings based at least in part on identifying data retention conditions associated with the first information; transmit an instruction to the memory device to initiate a second read operation of the memory device according to the selected fine-tuning setting; and perform a decoding operation based at least in part on receiving second information associated with the second read operation of the memory device from the memory device.

[0007] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: identify a read error based at least in part on receiving first information associated with a first read operation of the memory device from the memory device; select a fine-tuning setting from a plurality of fine-tuning settings based at least in part on identifying data retention conditions associated with the first information; transmit an instruction to the memory device, according to the selected fine-tuning setting, to initiate a second read operation of the memory device; and perform a decoding operation based at least in part on receiving second information associated with the second read operation of the memory device from the memory device.

[0008] A method at a controller is described. The method may include: identifying a read error based at least in part on receiving first information associated with a first read operation of the memory device from the memory device; selecting a fine-tuning setting from a plurality of fine-tuning settings based at least in part on identifying data retention conditions associated with the first information; transmitting an instruction to the memory device to initiate a second read operation of the memory device according to the selected fine-tuning setting; and performing a decoding operation based at least in part on receiving second information associated with the second read operation of the memory device from the memory device. Attached Figure Description

[0009] Figure 1 Examples of systems that support corrective reads of memory devices with reduced latency, based on the examples disclosed herein, are shown.

[0010] Figure 2 Examples of methods for supporting corrective reads of memory devices with reduced latency, based on the examples disclosed herein, are shown.

[0011] Figure 3 Examples of process flows and associated signaling supporting corrective reads of memory devices with reduced latency, based on the examples disclosed herein, are shown.

[0012] Figure 4 A block diagram is shown of a memory system that supports corrective reads of a memory device with reduced latency, according to an example disclosed herein.

[0013] Figure 5 The flowcharts shown below illustrate one or more methods for supporting corrective reads of memory devices with reduced latency, based on examples disclosed herein. Detailed Implementation

[0014] In some implementations, the memory system may be subjected to a relatively wide range of operating conditions, such as a relatively wide range of potential operating temperatures, relatively large potential temperature differences between access operations (e.g., between write and read operations), relatively large differences in potential data retention durations, and so on. For example, in some automotive applications, the memory system may be designed to operate across a temperature range of -40 degrees Celsius to 110 degrees Celsius, and may also be designed to support full cross-temperature conditions, which may involve supporting memory cells being written to at one extreme of this temperature range (e.g., -40 degrees Celsius) and read from at another extreme of this temperature range (e.g., 110 degrees Celsius). In some instances, supporting a range of operating conditions may involve a different set of fine-tuning settings for operating the memory device, such as different read parameters, some of which may be selected from said set based on (or in response to) different criteria. While a set of different fine-tuning settings can be extended to support an acceptable read margin for a relatively wide range of operating conditions or combinations of operating conditions, in some cases, such as corrective read operations (e.g., in response to a detected read error), iteration with a relatively large set of fine-tuning settings can be associated with increased latency, power consumption, processing load, or other adverse operations.

[0015] Based on the examples disclosed herein, memory systems can be configured to support various techniques for improving system efficiency when performing corrective read operations in response to detected read errors (e.g., according to enhanced corrective reads). For example, a memory system can identify read errors based on (or in response to) access to a memory device, and in response to an identified read error, can select one or more fine-tuning settings for performing the corrective read operation, at least in part, based on data retention conditions associated with the accessed memory device (e.g., associated with the information accessed at the memory device, associated with the physical address accessed at the memory device). In various examples, such data retention conditions can be associated with data retention duration or temperature or cross-temperature conditions, and other criteria or combinations thereof.

[0016] In some implementations, the memory system can select from a subset of possible fine-tuning settings that may be associated with performing corrective read operations at one or more relevant process corners. For example, the memory system may choose between a first fine-tuning setting associated with a relatively large cross temperature and a relatively short data retention duration, and a second fine-tuning setting associated with a relatively small cross temperature and a relatively long data retention duration. The ability of the memory system to select between different fine-tuning settings facilitates a proper balance between read margin reliability and latency associated with performing corrective read operations. For example, if a first corrective read operation associated with one of the first or second fine-tuning settings fails, the memory system may attempt a second corrective read operation associated with the other of the first or second fine-tuning settings. If the second corrective read operation fails, the memory system can infer a relatively high probability of a defect or other relatively serious error and can proceed with other error handling operations without further attempts at corrective read operations. Therefore, by selecting from a subset of possible fine-tuning parameters that represent appropriate angles of possible operating conditions or combinations thereof, the memory system can perform corrective read evaluations relatively quickly, which can reduce latency, power consumption, or processor load associated with error handling operations.

[0017] The features of this disclosure are firstly in reference to Figure 1 The features of this disclosure are described in the context of the system. Figure 2 and 3 The process flow is described in the context of this disclosure. These and other features of this disclosure are further supported by references. Figure 4 and 5 Device diagrams and flowcharts relating to corrective reads of memory devices with reduced latency are shown and described in the context of the device diagrams and flowcharts.

[0018] Figure 1 An example of a system 100 supporting corrective reads of a memory device with reduced latency, according to the examples disclosed herein, is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130—and other such operations—collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0028] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions described herein as belonging to memory system controller 115. Generally, one or more functions described herein as belonging to memory system controller 115 may actually be performed in some cases by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 that is at least partially managed by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in the supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations can be performed. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d located respectively in planes 165-a, 165-b, 165-c, and 165-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 may have one or more restrictions, such as parallel operations being performed on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0036] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. For example, in some cases, such copying and remapping may be performed to account for latency or attrition, rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0037] In some cases, the L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data due to a more recent or updated version of the data being stored in a different page 175 of memory device 130. Invalid data may have previously been programmed to an invalid page 175, but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has never been written to or has been erased.

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0039] System 100 may include any number of non-transitory computer-readable media that support corrective reads of memory devices with reduced latency. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, if such instructions are executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), they may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0040] In some cases, memory system 110 may use memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0041] In some implementations, system 100 (e.g., host system 105, memory system 110) may be subjected to a relatively wide range of operating conditions, such as a relatively wide range of potential operating temperatures, relatively large potential temperature differences between access operations (e.g., relatively large crossover temperatures, a relatively large difference between write operations and read operations on memory device 130), relatively large differences in potential data retention durations (e.g., the duration between write operations and read operations on memory cells of memory device 130), and so on. For example, in some automotive applications, memory system 110 may be designed to operate across a temperature range of -40 degrees Celsius to 110 degrees Celsius and may also be designed to support full crossover temperature conditions, which may involve supporting memory cells of memory device 130 being written to at one extreme of this temperature range and read at the other extreme of this temperature range.

[0042] In some instances, supporting a range of operating conditions may involve a set of different fine-tuning settings, such as different parameters for performing read operations at memory device 130, wherein the fine-tuning settings may be selected from the set based on (or in response to) different criteria (e.g., based on detected or inferred operating conditions) to support different read operations. In some such instances, such criteria may be associated with a specification stack. For example, a set of different fine-tuning settings may be associated with a number of elements or parameters, such as temperature or cross-temperature and data retention duration (e.g., high-temperature data retention duration, which may be associated with the cumulative duration between write and read operations at or above a threshold temperature). In some instances, using a single (e.g., uniform) setting for different operating conditions may be undesirable because such a technique may benefit read performance at certain process corners at the expense of read performance at other process corners. Therefore, in some instances, fine-tuning settings associated with different read temperatures may be implemented at memory device 130 to improve read performance at different temperature or cross-temperature corners, and fine-tuning settings associated with different data retention durations may be implemented at memory device 130 to improve read performance at different data retention corners. In some implementations, the cross-temperature section and the data holding section can be relatively independent, and the fine-tuning settings for these sections can be controlled separately.

[0043] In some instances, memory system 110 may be configured to support corrective read operations, which can refer to various techniques for performing one or more read operations on those same memory cells after an error is identified associated with a previous read operation on a memory cell (e.g., the physical address of the memory cell) of memory device 130. In some embodiments, such techniques may be configured to supplement other read error handling operations performed at memory device 130, which may utilize processing or other capabilities outside of memory device 130 (e.g., of memory system controller 115). For example, memory device 130 (e.g., local controller 135) may perform read operations and may identify errors based on various error detection or error correction capabilities of memory device 130. In some instances, memory device 130 may be unable to resolve such errors and may indicate the error to memory system controller 115. In response, the memory system controller 115 may initiate one or more corrective read operations (e.g., via signaling to the memory device 130), which may include the memory system controller 115 selecting and indicating fine-tuning settings for the memory device 130 to use when performing corrective read operations.

[0044] While a set of different fine-tuning settings implemented by memory device 130 can be extended to support acceptable read margins for a relatively wide range of operating conditions or combinations of operating conditions, in some cases, such as corrective read operations (e.g., in response to a detected read error), iteration with a relatively large set of fine-tuning settings can be associated with increased latency, power consumption, processing load, or other adverse operations. According to the examples disclosed herein, memory system 110 can be configured to support various techniques for improving system efficiency when performing corrective read operations in response to read errors associated with read operations on memory device 130 (e.g., according to an enhanced corrective read). For example, the number of fine-tuning settings for corrective read operations can be limited (e.g., limited to a subset of fine-tuning parameters implemented at memory device 130), and memory system 110 (e.g., memory system controller 115) can be configured to select a fine-tuning setting from said subset based on (or in response to) observed or inferred system conditions. For example, memory system 110 (e.g., memory system controller 115) may identify read errors based on (or in response to) access to memory device 130 (e.g., based on signaling from memory device 130), and may, in response to an identified read error, select fine-tuning settings for performing a corrective read operation on memory device 130, at least in part, based on data retention conditions associated with the accessed memory device 130 (e.g., associated with the information accessed at memory device 130, associated with the physical address accessed at memory device 130). In various instances, such data retention conditions may be associated with data retention duration (e.g., high-temperature data retention duration) or temperature or cross-temperature conditions, and other criteria or combinations thereof.

[0045] In some implementations, memory system 110 (e.g., memory system controller 115) can be selected from a subset of possible fine-tuning settings that may be associated with performing a corrective read operation at a relevant process corner. For example, memory system 110 may select between a first fine-tuning setting associated with a relatively large cross temperature and a relatively short data retention duration, and a second fine-tuning setting associated with a relatively small cross temperature and a relatively long data retention duration, which can support an appropriate balance between read margin reliability and latency associated with performing a corrective read operation. For example, if a first corrective read operation at memory device 130 performed according to one of the first or second fine-tuning settings is unsuccessful, then memory system 110 may attempt a second corrective read operation at memory device 130 according to the other of the first or second fine-tuning settings. If the second corrective read operation fails, the memory system 110 (e.g., the memory system controller 115) can infer a relatively high probability of a defect or other relatively serious error at the memory device 130 and can proceed with other error handling operations (e.g., via the memory system controller 115, via the memory device 130) without further corrective read attempts. Therefore, by selecting from a subset of possible fine-tuning parameters that can represent or otherwise cover appropriate angles of possible operating conditions or combinations thereof, the memory system 110 can complete the corrective read evaluation relatively quickly, which reduces latency, power consumption, or processor load associated with error handling operations.

[0046] Figure 2 An example of a method 200 supporting corrective reads of memory devices with reduced latency, according to the examples disclosed herein, is shown. Operation of method 200 may be performed by a memory system 110, such as a memory system controller 115 coupled to one or more memory devices 130.

[0047] In some instances, method 200 may include operations performed in response to an earlier step of a read error handling (REH) operation (e.g., performed after, or initiated based on, the earlier step). For example, memory device 130 (e.g., local controller 135) may perform a read operation (e.g., in response to a read command from host system 105, or in the absence of a read command from host system 105, such as a read operation supporting memory management operations within memory system 110), and memory device 130 may identify an error in a portion of die 160 being read (e.g., physical address, page 175). In response to the identified error, memory device 130 may attempt to perform various read error handling operations. For example, memory device 130 may perform one or more "read retry" operations, including rereading the same portion of die 160 using different predefined read levels (e.g., different read voltages). In some instances, memory device 130 may perform a "read calibration" operation associated with a finer-grained read level search, whereby a finer-grained calibration can be performed around a suitable read level once it is identified. In some instances, sequential read calibration may be performed at memory device 130, providing coverage that is greater than that of a single calibration. If such read error handling operations fail to resolve an identified read error (e.g., preventing memory device 130 from performing a resolution operation), then method 200 may proceed to the operation at 205.

[0048] At 205, method 200 may include selecting and applying a first fine-tuning setting (e.g., one or more fine-tuning settings) for a corrective read operation. In some instances, such techniques may be performed by memory system controller 115 in response to information received from memory device 130 (e.g., read information, error information). For example, memory system controller 115 may be configured to select from a subset of fine-tuning settings implemented at memory device 130 or other more fundamental read parameters that may be associated with different specification angles. Memory system controller 115 may dynamically (e.g., during operation) select the first fine-tuning setting, which can reduce error handling latency by identifying fine-tuning settings applicable to relevant (e.g., current) operating conditions for the corrective read operation. In some instances, such selection may be based on (or in response to) detected or inferred operating conditions (e.g., conditions corresponding to portions of memory device 130 accessed in previous read operations), such as data retention conditions associated with memory device 130.

[0049] In some implementations, the memory system controller 115 may be configured to perform selection among multiple fine-tuning settings for corrective read operations, providing an appropriate balance between error handling reliability and latency. In some instances, one fine-tuning setting may be associated with a relatively high crossover temperature angle and a relatively short data hold duration angle, while another fine-tuning setting may be associated with a relatively low crossover temperature angle and a relatively long data hold duration angle. Other fine-tuning settings different from the two discussed herein are also envisioned. In some instances, the fine-tuning setting may be relatively more sensitive to the data hold duration portion than the temperature or crossover temperature portion; therefore, the selection between fine-tuning settings may be primarily (e.g., in weighted selection) based on, and in some cases only on, detections or inferences associated with the data hold duration (e.g., associated with the portion of memory device 130 being read). In some instances, such selection may be performed without involving the detection or inference of operating temperature, since the fine-tuning setting may be less sensitive to temperature than the data hold duration.

[0050] In some instances, the selection of 205 can be based on supporting information provided by memory device 130, which memory system controller 115 can use to infer conditions of memory device 130 (e.g., data retention conditions). For example, some memory devices 130 (e.g., memory devices 130 implementing a NAND architecture) can utilize the threshold voltage (Vt) characteristics of transistors to store or detect a given logic state. In some instances, the Vt characteristic can shift over time, which can be associated with the data retention duration of memory device 130 (e.g., the time between when a memory cell is written and when a memory cell is read, the cumulative duration between write and read operations where a portion of die 160 is above a threshold temperature). For example, a relatively long retention duration, or a relatively long duration of retaining information at high temperatures, can be associated with a relatively large Vt offset (e.g., compared to nominal or write conditions).

[0051] In some instances, memory device 130 may detect or infer Vt offset information associated with a portion of die 160, such as during early read processing operations (e.g., before operation 205, during read retry or read calibration operations). For example, once a trough is detected during an early read error processing operation, the Vt offset of the word line of die 160 can be estimated. In some instances, the Vt offset may correspond to the difference between the Vt level associated with the default read level and the Vt level associated with one or more read retries or read calibrations performed by memory device 130. Memory device 130 may provide Vt offset information (e.g., before or as part of operation 205) to memory system controller 115, which can be used by memory system controller 115 as a proxy for data retention duration to support selection between fine-tuning settings. For example, at 205, if the indicated Vt offset is less than a threshold, indicating a relatively short hold duration, then the memory system controller 115 can select a fine-tuning setting associated with a relatively high crossover temperature angle and a relatively short data hold duration angle. Conversely, if the indicated Vt offset is greater than the threshold, indicating a relatively long hold duration, then the memory system controller 115 can select a fine-tuning setting associated with a relatively low crossover temperature angle and a relatively long data hold duration angle. In an example of the former, out of a set of 10 candidate fine-tunings, 5 can be associated with the data hold duration and 5 with the temperature. Depending on the selection at 205, the memory system controller 115 can be configured to adjust the fine-tuning associated with the data hold duration to cover shorter hold durations and adjust the fine-tuning associated with the temperature to cover larger crossover temperatures. In some instances, such selections can increase the likelihood of successful subsequent corrective read operations.

[0052] In some instances, at 210, method 200 may include performing Automatic Recovery Calibration (ARC). The operation at 210 may include a calibration operation at memory device 130, which may be initiated by signaling from memory system controller 115. For example, when initiated by memory system controller 115, memory device 130 may perform a read calibration operation, during which memory device 130 may identify the characteristics of the distribution of read voltage levels and corresponding voltage thresholds (e.g., between logic states) of one or more memory levels associated with memory cells (e.g., according to SLC configuration or MLC configuration, and other configurations). Memory device 130 may utilize information from ARC, such as information related to read voltage levels or voltage thresholds, to determine the applicable read voltage level for the corresponding memory level, and the associated offset relative to a baseline read voltage level. In some instances, once an appropriate read level is identified, a finer-grained calibration may be performed around said level. In some instances, the ARC at 210 may be performed using a preferred calibration offset identified during an earlier read operation performed by memory device 130 (e.g., before the operation at 205). For example, ARC of 210 can be performed using a minimum checker weight read offset associated with an early step in read error handling performed by memory device 130.

[0053] At 215, method 200 may include performing a corrective read operation with a first fine-tuning setting (e.g., selected at 205), which may be associated with the same portion of die 160 as the initial read (e.g., the same physical address associated with the read error handling operation prior to 205). The corrective read operation may be initiated by memory system controller 115, which may include various signaling (e.g., read command, read trigger) directed to memory device 130. Such signaling may include an indication of the first fine-tuning setting selected at 205, which may include an explicit indication of one or more parameters, or may include an identifier of one or more fine-tuning parameters stored at memory device 130, and other instances. In some embodiments, such operation may include performing a 2-bit corrective read. In various instances, the corrective read operation at 215 may include memory device 130 transmitting relevant information (e.g., read information, error information) to memory system controller 115 for subsequent operations, or subsequent operations may be performed at memory device 130, or various combinations thereof.

[0054] At 220, method 200 may include performing a decoding operation, which may refer to various operations that decode or otherwise verify information associated with a corrective read operation (e.g., information associated with a portion of die 160 may be retrieved). In various instances, the decoding at 220 may involve one or more hard-bit decoding operations, one or more soft-bit decoding operations (e.g., one or more unit soft bit read (SBSBR) operations), or various combinations thereof. For example, the decoding at 220 may include a first hard-bit decoding (e.g., 1-bit hard decoding (1H)), which may be followed by a combination of hard-bit and soft-bit decoding (e.g., 1H2S decoding in the event that the 1-bit hard decoding is unsuccessful). In various instances, the decoding may be performed by memory device 130 or memory system controller 115. If performed at memory device 130, then memory device 130 may transmit signaling to memory system controller 115 to indicate whether the decoding at 220 was successful.

[0055] At 225, method 200 may include determining whether decoding at 220 was successful, which may be performed by memory system controller 115. If decoding at 220 is successful, indicating a successful corrective read operation, then method 200 may terminate, which may be associated with exiting read error handling operations associated with memory device 130. If decoding at 225 is unsuccessful, then the method may proceed to 230.

[0056] At 230, method 200 may include selecting and applying a second fine-tuning setting to perform a second corrective read operation. In some instances, such a technique may be performed by memory system controller 115. In cases where the selection at 205 is made between two fine-tuning settings (e.g., based on or in response to a comparison of Vt offset with a threshold), the selection at 205 may be associated with selecting one of the two fine-tuning settings, and the selection at 230 may be associated with selecting the other of the two fine-tuning settings. In some instances, operation 230 may be associated with disabling corrective reads.

[0057] In some instances, at 235, method 200 may include performing a second ARC. The operation at 235 may include a calibration operation at memory device 130, which may be initiated by signaling from memory system controller 115. For example, when initiated by memory system controller 115, memory device 130 may perform a read calibration operation, whereby a finer-grained calibration can be performed around a suitable read level once that level is identified. In some instances, the calibration at 235 may be performed using a preferred calibration offset identified during an earlier read operation performed by memory device 130 (e.g., before the operation at 205 or during the operation at 210 or 215). For example, the ARC at 235 may be performed using a minimum checksum weighted read offset associated with an early step in read error handling performed by memory device 130 or a corrective read operation at 215, or a combination thereof.

[0058] At 240, method 200 may include performing a corrective read operation with a second fine-tuning setting (e.g., selected at 230), which may be associated with the same portion of die 160 as the initially read (e.g., the same physical address associated with the read error handling operation prior to 205). The corrective read operation may be initiated by memory system controller 115, which may include various signaling to memory device 130, including indications of the second fine-tuning setting. In some embodiments, such an operation may include performing a 2-bit corrective read. In various instances, the corrective read operation at 240 may include memory device 130 transmitting relevant information to memory system controller 115 for subsequent operations, or subsequent operations may be performed at memory device 130, or various combinations thereof.

[0059] At 245, method 200 may include performing a decoding operation to attempt to decode or otherwise verify information associated with the second corrective read operation. In various instances, decoding may be performed by memory device 130 or memory system controller 115. If performed at memory device 130, then memory device 130 may transmit signaling to memory system controller 115 to indicate whether decoding at 245 was successful.

[0060] At 250, method 200 may include determining whether decoding of 245 was successful, which may be performed by memory system controller 115. If decoding of 245 is successful, indicating a successful corrective read operation, then method 200 may terminate, which may be associated with exiting read error handling operations associated with memory device 130. If decoding of 245 is unsuccessful, then method 200 may also terminate, which may be associated with performing subsequent read error handling operations. In some instances, such operations may include performing other corrective read operations, but at a finer granularity, and may include recovering lost data using redundant information. In some instances, such operations may include defect management operations (e.g., where unsuccessful decoding of 245 indicates a physical defect), such as refreshing, restoring, or retrieving associated portions of die 160.

[0061] Figure 3 An example of a process flow 300 supporting corrective reads of a memory device with reduced latency, according to the examples disclosed herein, is shown. Operation of process flow 300 may be performed by one or more components of memory system 110-c, such as memory system controller 115-c and memory device 130-c, which may be referenced... Figure 1 and 2 An instance of the corresponding component described.

[0062] At 310, process flow 300 may include, for example, performing a read operation via memory device 130-c (e.g., local controller 135). In some instances, the read operation at 310 may be performed in response to a read command issued by host system 105 (not shown), or as part of a memory management operation of memory system controller 115-c. In some such instances, the read operation at 310 may be initiated based on or in response to a signal (e.g., a read initiation signaling) transmitted by memory system controller 115-c and received by memory device 130-c. In some other instances, the read operation at 310 may be initiated autonomously by the memory management operation of memory device 130-c (e.g., without an initiation signal from memory system controller 115-c).

[0063] At 320, process flow 300 may include initiating a read error handling operation. For example, memory device 130-c (e.g., local controller 135) may identify a read error associated with the read operation at 310 and may initiate a read error handling operation at 320 (e.g., at memory device 130-c). In some instances, read error handling by memory device 130-c may succeed, which may avoid one or more aspects of subsequent error handling (e.g., avoiding corrective read operations, exiting or terminating process flow 300). In some other instances, read error handling by memory device 130-c may fail, which may be associated with continuing subsequent operations of process flow 300.

[0064] At 330 (e.g., in response to an unsuccessful read error handling operation at 320), process flow 300 may include, for example, the transfer of read information via memory device 130-c, which may be received by memory system controller 115-c. In some instances, the read information at 330 may be associated with the read operation at 310 and may include erroneous read information that cannot be decoded or corrected by memory device 130-c. In various instances, the read information at 330 may include one or more levels of error correction application, or may be unmodified since the read operation at 310 or the read error handling at 320. In some instances, the read information at 330 may be the output associated with one or more read retry operations or read calibration operations associated with the read error handling operation at 330.

[0065] In some instances, at 340, process flow 300 may include transmitting error information associated with read error handling at 320. In some instances, the error information at 340 may include an indication that read information at 330 was not successfully decoded or otherwise verified. In some instances, the error information at 340 may include error identification information, such as the number of errors, the characteristics or category of the errors, or an indication of one or more parameters of the read operation at 310 or the read error handling at 320 (e.g., an indication of one or more operating conditions, such as temperature, cross temperature, or voltage, and others). In some instances, the error information at 340 may include an indication of Vt offset, which can be used to infer the data retention conditions of memory device 130-c associated with the read operation at 310 (e.g., to infer the data retention duration associated with a physical address of memory device 130-c, such as page 175 of memory device 130-c).

[0066] At 350 (e.g., in response to receiving a read message from 330 or an error message from 340, or both, or otherwise in response to identifying a read error associated with the read operation at 310), process flow 300 may include performing one or more corrective read operations. The corrective read operations at 350 may include one or more operations initiated or otherwise managed by the memory system controller 115-c, and may include operations that are more advanced, more functional, or more processor-intensive than the read error handling operation at 320 (e.g., to utilize the processing or other capabilities of the memory system controller 115-c).

[0067] In some instances, at 351, a fine-tuning setting for corrective read operations can be selected, for example, via memory system controller 115-c. This may include selections based on (or in response to) data hold conditions associated with read information from 330 or error information from 340. For example, the selection at 351 may be based on (or in response to) data hold duration or temperature (e.g., read temperature, crossover temperature) or a combination thereof, which in some instances may be signaled in read information from 330 or error information from 340. In some instances, the selection at 351 may be based on Vt offset information signaled via memory device 130-c, which may be associated with an inference of the data hold duration corresponding to the read information from 330. In some instances, the selection at 351 may be associated with a choice between two fine-tuning settings, wherein a first fine-tuning setting may be associated with a relatively short data hold duration and a second fine-tuning setting may be associated with a relatively long data hold duration. In some instances, the selection at 351 may be based on an inference of the data hold duration and may also be associated with assumptions about temperature or crossover temperature (e.g., to assess worst-case or boundary process angles). For example, the first fine-tuning setting may also be associated with a relatively high temperature or cross temperature, and the second fine-tuning setting may also be associated with a relatively low temperature or cross temperature.

[0068] In some instances, at 352, a corrective read operation can be initiated, for example, via the memory system controller 115-c, which may be associated with an initiation signaling that can be received by the memory device 130-c. In various instances, the initiation at 352 may include implicit or explicit indications of one or more read parameters associated with the selection at 351 to perform the corrective read operation.

[0069] In some instances, at 353, a corrective read operation can be performed, for example, by memory device 130-c (e.g., local controller 135) based on a fine-tuning setting selected at 315, as initiated by memory system controller 115-c. In some instances, at 354, memory device 130-c can transmit corrective read information (e.g., read information associated with the corrective read operation at 353), which can be received by memory system controller 115-c.

[0070] In some instances, at 355, a component such as memory system controller 115-c may attempt to decode the corrective read information of 354. If decoding at 355 is successful, process flow 300 may terminate, and memory system 110-c may continue normal operation (e.g., processing the decoded read information, which may include transmitting the read information to requesting host system 105 or otherwise processing the read information to support memory management or other operations). In some instances, if decoding at 355 is unsuccessful, the corrective read operation of 350 may be repeated. For example, to support selection between two tuning settings, operations from 351 to 355 may be repeated for a second tuning setting (e.g., based on a tuning setting not selected during the first iteration of 351). In some other instances (e.g., if the corrective read operation is performed only for a single selected tuning setting, or if the previous corrective read operation has been repeated a configured number of times), process flow 300 may terminate the corrective read operation of 350 and continue with operation 360.

[0071] At 360, process flow 300 may include performing defect management operations. In some instances, the defect management operations at 360 may include memory device 130-c performing other corrective read operations, but at a finer granularity, and may include recovering lost data using redundancy information (e.g., from memory device 130-c, or from another memory device 130). In some instances, such operations may include defect management operations (e.g., where unsuccessful decoding of one or more iterations at 355 may indicate a physical defect), such as refreshing, restoring, or retrieving associated portions of die 160, which may be performed by memory system controller 115-c, memory device 130-c, or both.

[0072] Figure 4 A block diagram 400 illustrates a memory system 420 supporting corrective reads of a memory device with reduced latency, according to an example disclosed herein. The memory system 420 may be a reference... Figures 1 to 3Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of components for performing various aspects of corrective reads of a memory device with reduced latency as described herein. For example, memory system 420 may include an error identification component 425, a fine-tuning setting selection component 430, a read operation initiation component 435, a decoding component 440, a physical address parameter receiving component 445, a hold condition identification component 450, a defect management component 455, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses). In some embodiments, the error identification component 425, the fine-tuning setting selection component 430, the read operation initiation component 435, the decoding component 440, the physical address parameter receiving component 445, the hold condition identification component 450, and the defect management component 455 may be compatible with reference to... Figure 1 The components of a memory system controller 115 coupled to one or more memory devices 130 as described.

[0073] Error identification component 425 may be configured or otherwise support components for identifying read errors based at least in part on receiving first information associated with a first read operation of the memory device from the memory device. In some instances, fine-tuning setting selection component 430 may be configured or otherwise support components for selecting a fine-tuning setting from a plurality of fine-tuning settings based at least in part on identifying data retention conditions associated with the first information. In some instances, read operation initiation component 435 may be configured or otherwise support components for transmitting an instruction to the memory device to initiate a second read operation of the memory device according to the selected fine-tuning setting. In some instances, decoding component 440 may be configured or otherwise support components for performing a decoding operation based at least in part on receiving second information associated with a second read operation of the memory device from the memory device.

[0074] In some instances, the physical address parameter receiving component 445 may be configured or otherwise supported for receiving an indication of a threshold voltage offset associated with the physical address of the memory device for the first read operation. In some instances, the hold condition identification component 450 may be configured or otherwise supported for identifying data hold conditions based at least in part on the threshold voltage offset.

[0075] In some instances, to select a fine-tuning setting, the fine-tuning setting selection component 430 may be configured or otherwise support selection between a first fine-tuning setting associated with a first data retention duration and a second fine-tuning setting associated with a second data retention duration greater than the first data retention duration. In some instances, the first fine-tuning setting may be associated with a first temperature difference between one or more write operations and one or more read operations, and the second fine-tuning setting may be associated with a second temperature difference less than the first temperature difference between one or more write operations and one or more read operations.

[0076] In some instances, the instruction to initiate a second read operation may be associated with a selection of either a first or second fine-tuning setting. In some such instances, the read operation initiation component 435 may be configured or otherwise support components for transmitting an instruction to the memory device to initiate a third read operation of the memory device, based at least in part on the failure of a decoding operation, according to another of the first or second fine-tuning setting. In some such instances, the decoding component 440 may be configured or otherwise support components for performing a second decoding operation, based at least in part on receiving third information associated with a third read operation of the memory device from the memory device.

[0077] In some instances, the defect management component 455 may be configured or otherwise support components that perform defect management operations, at least in part, based on the failure of a second decoding operation. In some instances, performing a decoding operation may include performing hard-bit decoding, soft-bit decoding, or any combination thereof.

[0078] Figure 5 A flowchart illustrating an example disclosed herein demonstrates a method 500 for supporting corrective reads of a memory device with reduced latency. Operation of method 500 can be implemented by the memory system or its components described herein. For example, operation of method 500 can be provided by reference to... Figures 1 to 4 The described memory system executes the method. Aspects of method 500 may be implemented by a controller and other components. Alternatively, aspects of method 500 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to or otherwise included in memory system 110, or instructions stored in local memory 120). For example, these instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operation of method 500. Alternatively, memory system 110 may use dedicated hardware to execute aspects of the described functionality.

[0079] At 505, the method may include identifying a read error based at least in part on receiving first information associated with a first read operation on the memory device. Operation 505 may be performed according to the examples disclosed herein. In some instances, aspects of operation 505 may be derived from references... Figure 4 The described error identification component 425 is executed.

[0080] At 510, the method may include selecting a fine-tuning setting from a plurality of fine-tuning settings, at least in part based on identifying data retention conditions associated with the first information. Operation 510 may be performed according to the examples disclosed herein. In some instances, aspects of operation 510 may be derived from references... Figure 4 The fine-tuning settings selection component 430 described is executed.

[0081] At 515, the method may include transmitting an instruction to the memory device to initiate a second read operation of the memory device according to selected fine-tuning settings. Operation 515 may be performed according to the examples disclosed herein. In some examples, aspects of operation 515 may be derived from references... Figure 4 The described read operation is initiated by component 435.

[0082] At 520, the method may include performing a decoding operation based at least in part on receiving second information associated with a second read operation of the memory device from the memory device. Operation 520 may be performed according to the examples disclosed herein. In some examples, aspects of operation 520 may be derived from references... Figure 4 The described decoding component 440 is executed.

[0083] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0084] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: identifying a read error based at least in part on receiving first information associated with a first read operation of the memory device from the memory device; selecting a fine-tuning setting from a plurality of fine-tuning settings based at least in part on identifying a data retention condition associated with the first information; transmitting an instruction to the memory device, according to the selected fine-tuning setting, to initiate a second read operation of the memory device; and performing a decoding operation based at least in part on receiving second information associated with the second read operation of the memory device from the memory device.

[0085] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1 further includes an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: receiving an indication of a threshold voltage offset associated with a physical address of the memory device for the first read operation, and identifying the data retention condition based at least in part on the threshold voltage offset.

[0086] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein selecting the fine-tuning setting includes operations, features, circuit systems, logic, components, or instructions or any combination thereof for selecting between a first fine-tuning setting associated with a first data retention duration and a second fine-tuning setting associated with a second data retention duration greater than the first data retention duration.

[0087] Aspect 4: The method, device, or non-transitory computer-readable medium according to aspect 3, wherein the first fine-tuning setting is associated with a first temperature difference between one or more write operations and one or more read operations, and the second fine-tuning setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference.

[0088] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 3 to 4, wherein the instruction to initiate the second read operation is associated with a selection of the first fine-tuning setting or the second fine-tuning setting, and wherein the method, apparatus, or non-transitory computer-readable medium further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: transmitting an instruction to the memory device to initiate a third read operation of the memory device, at least in part based on the failure of the decoding operation, according to the other of the first fine-tuning setting or the second fine-tuning setting, and performing the second decoding operation, at least in part based on receiving third information associated with the third read operation of the memory device from the memory device.

[0089] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to aspect 5 further includes an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for performing a defect management operation at least in part based on the failure of the second decoding operation.

[0090] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 6, wherein performing the decoding operation comprises operations, features, circuit systems, logic, components, or instructions or any combination thereof for performing the decoding operation comprises performing hard-bit decoding, soft-bit decoding, or any combination thereof.

[0091] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0092] This document describes a device. An overview of various aspects of the device described herein is provided below:

[0093] Aspect 8: An apparatus comprising: a memory device; and a controller coupled to the memory device and configured to cause the device to: identify a read error based at least in part on receiving first information associated with a first read operation of the memory device from the memory device; select a fine-tuning setting from a plurality of fine-tuning settings based at least in part on identifying a data retention condition associated with the first information; transmit an instruction to the memory device, according to the selected fine-tuning setting, to initiate a second read operation of the memory device; and perform a decoding operation based at least in part on receiving second information associated with the second read operation of the memory device from the memory device.

[0094] Aspect 9: The device according to aspect 8, wherein the controller is further configured to cause the device to: receive an indication of a threshold voltage offset associated with a physical address of the memory device for the first read operation; and identify the data retention condition based at least in part on the threshold voltage offset.

[0095] Aspect 10: The device according to any one of aspects 8 to 9, wherein, in order to select the fine-tuning setting, the controller is configured to cause the device to: select between a first fine-tuning setting associated with a first data holding duration and a second fine-tuning setting associated with a second data holding duration greater than the first data holding duration.

[0096] Aspect 11: The device according to aspect 10, wherein the first fine-tuning setting is associated with a first temperature difference between one or more write operations and one or more read operations, and the second fine-tuning setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference.

[0097] Aspect 12: The device according to any one of aspects 10 to 11, wherein the instruction to initiate the second read operation is associated with a selector of the first fine-tuning setting or the second fine-tuning setting, and wherein the controller is further configured to cause the device to: transmit an instruction to initiate a third read operation of the memory device, based at least in part on the failure of the decoding operation, according to the other of the first fine-tuning setting or the second fine-tuning setting; and perform the second decoding operation, based at least in part on receiving third information associated with the third read operation of the memory device from the memory device.

[0098] Aspect 13: The device according to aspect 12, wherein the controller is further configured to cause the device to perform a defect management operation at least in part based on the failure of the second decoding operation.

[0099] Aspect 14: The device according to any one of aspects 8 to 13, wherein, in order to perform the decoding operation, the controller is configured to cause the device to perform hard-bit decoding, soft-bit decoding, or any combination thereof.

[0100] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0101] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0102] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If, for example, one component of a controller couples other components together, then that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0103] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0104] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, these terms are used interchangeably if they describe the connection between conditional actions, conditional processes, or process parts.

[0105] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0106] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other condition or action.

[0107] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0108] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0109] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0110] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0111] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0112] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0113] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0114] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to: A read error is identified, at least in part, based on first information received from the memory device in association with a first read operation of the memory device; At least in part, based on identifying data retention conditions associated with the first information, a fine-tuning setting is selected from a plurality of fine-tuning settings, wherein the data retention conditions are associated with data retention duration, temperature, cross temperature conditions, or any combination thereof; Based on the selected fine-tuning settings, an instruction to initiate a second read operation of the memory device is transmitted to the memory device; and The decoding operation is performed at least in part based on receiving second information associated with the second read operation of the memory device from the memory device.

2. The device of claim 1, wherein the controller is further configured to cause the device to: Receive an indication of a threshold voltage offset associated with the physical address of the memory device used for the first read operation; and The data holding conditions are identified, at least in part, based on the threshold voltage offset.

3. The device of claim 1, wherein, in order to select the fine-tuning setting, the controller is configured to cause the device to: Choose between a first fine-tuning setting associated with a first data retention duration and a second fine-tuning setting associated with a second data retention duration greater than the first data retention duration.

4. The device of claim 3, wherein the first fine-tuning setting is associated with a first temperature difference between one or more write operations and one or more read operations, and the second fine-tuning setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference.

5. The device of claim 3, wherein the instruction to initiate the second read operation is associated with a selector of the first fine-tuning setting or the second fine-tuning setting, and wherein the controller is further configured to cause the device to: Based at least in part on the failure of the decoding operation, an instruction to initiate a third read operation of the memory device is transmitted to the memory device according to either the first fine-tuning setting or the second fine-tuning setting; and The second decoding operation is performed at least in part based on receiving third information associated with the third read operation of the memory device from the memory device.

6. The device of claim 5, wherein the controller is further configured to cause the device to: Defect management operations are performed, at least in part, based on the failure of the second decoding operation.

7. The device of claim 1, wherein, in order to perform the decoding operation, the controller is configured to cause the device to perform hard-bit decoding, soft-bit decoding, or any combination thereof.

8. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: A read error is identified, at least in part, based on first information received from the memory device in association with a first read operation of the memory device. At least in part, based on identifying data retention conditions associated with the first information, a fine-tuning setting is selected from a plurality of fine-tuning settings, wherein the data retention conditions are associated with data retention duration, temperature, cross temperature conditions, or any combination thereof; Based on the selected fine-tuning settings, an instruction to initiate a second read operation of the memory device is transmitted to the memory device; and The decoding operation is performed at least in part based on receiving second information associated with the second read operation of the memory device from the memory device.

9. The non-transitory computer-readable medium of claim 8, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Receive an indication of a threshold voltage offset associated with the physical address of the memory device used for the first read operation; and The data holding conditions are identified, at least in part, based on the threshold voltage offset.

10. The non-transitory computer-readable medium of claim 8, wherein, in order to select the fine-tuning setting, the instruction, when executed by the processor of the electronic device, causes the electronic device to select between a first fine-tuning setting associated with a first data retention duration and a second fine-tuning setting associated with a second data retention duration greater than the first data retention duration.

11. The non-transitory computer-readable medium of claim 10, wherein the first fine-tuning setting is associated with a first temperature difference between one or more write operations and one or more read operations, and the second fine-tuning setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference.

12. The non-transitory computer-readable medium of claim 10, wherein the instruction to initiate the second read operation is associated with a selector of the first or second fine-tuning setting, and wherein the instruction, when executed by the processor of the electronic device, further causes the electronic device to: Based at least in part on the failure of the decoding operation, an instruction to initiate a third read operation of the memory device is transmitted to the memory device according to either the first fine-tuning setting or the second fine-tuning setting; and The second decoding operation is performed at least in part based on receiving third information associated with the third read operation of the memory device from the memory device.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform a defect management operation at least in part based on the failure of the second decoding operation.

14. The non-transitory computer-readable medium of claim 8, wherein, in order to perform the decoding operation, the instructions, when executed by the processor of the electronic device, cause the electronic device to perform hard-bit decoding, soft-bit decoding, or any combination thereof.

15. A method at a controller, the method comprising: A read error is identified, at least in part, based on first information received from the memory device in association with a first read operation of the memory device. At least in part, based on identifying data retention conditions associated with the first information, a fine-tuning setting is selected from a plurality of fine-tuning settings, wherein the data retention conditions are associated with data retention duration, temperature, cross temperature conditions, or any combination thereof; Based on the selected fine-tuning settings, an instruction to initiate a second read operation of the memory device is transmitted to the memory device; and The decoding operation is performed at least in part based on receiving second information associated with the second read operation of the memory device from the memory device.

16. The method of claim 15, further comprising: Receive an indication of a threshold voltage offset associated with the physical address of the memory device used for the first read operation; as well as The data holding conditions are identified, at least in part, based on the threshold voltage offset.

17. The method of claim 15, wherein selecting the fine-tuning setting comprises: Choose between a first fine-tuning setting associated with a first data retention duration and a second fine-tuning setting associated with a second data retention duration greater than the first data retention duration.

18. The method of claim 17, wherein the first fine-tuning setting is associated with a first temperature difference between one or more write operations and one or more read operations, and the second fine-tuning setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference.

19. The method of claim 17, wherein the instruction to initiate the second read operation is associated with a selector of the first fine-tuning setting or the second fine-tuning setting, the method further comprising: At least in part based on the failure of the decoding operation, an instruction to initiate a third read operation of the memory device is transmitted to the memory device according to either the first fine-tuning setting or the second fine-tuning setting; as well as The second decoding operation is performed at least in part based on receiving third information associated with the third read operation of the memory device from the memory device.

20. The method of claim 19, further comprising: Defect management operations are performed, at least in part, based on the failure of the second decoding operation.

21. The method of claim 15, wherein performing the decoding operation comprises performing hard-bit decoding, soft-bit decoding, or any combination thereof.

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