Method for manufacturing a packaging substrate

Abstract

The application provides a manufacturing method of a packaging substrate, which comprises the following steps: obtaining a pattern compensation value through trial production, modifying existing process parameters according to the obtained pattern compensation value, and manufacturing mass production packaging substrates based on the same electroplating production line, etching production line and plate placing rules as in the trial production. The improved process design of the application firstly carries out sample production before formal production, and during the sample production process, different exposure compensation values are selected for different patterns, the line width, pitch and copper thickness are measured, the copper thickness contour distribution data (distribution map) established after electroplating is matched, the etching topographic map is found out, the line width compensation value is revised according to the relationship between the electroplated copper thickness, the line width compensation value and the etching uniformity and the actual measurement results, and finally the etching is carried out according to the revised line width compensation value, which can greatly improve the consistency of the fine line manufacturing of the whole plate surface of the packaging substrate, reduce the scrap rate, and thus improve the economic benefits.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a packaging substrate. Background Technology

[0002] As electronic products become increasingly lighter, thinner, shorter, and smaller, the pattern density of packaging substrates is increasing, and the linewidth spacing and interconnect diameters are shrinking, posing greater challenges to the manufacturing capabilities of packaging substrates. In the fabrication of fine circuitry, traditional subtractive etching methods are widely used due to their low cost and minimal equipment investment. However, the production of fine circuitry is limited by several factors: First, the subtractive method suffers from a pooling effect, causing lateral etching (also known as side etching) during the etching process, resulting in low precision in fine circuitry. Second, during electroplating, issues such as the distribution of electric field lines and the effectiveness of the etching solution lead to poor uniformity, resulting in inconsistent copper thickness during etching. Third, the uniformity of etched lines in the subtractive method is affected by nozzle pressure and differences in the exchange rate of the etching solution between the upper and lower surfaces, leading to varying etching capabilities at different locations. These three main reasons limit the precision of subtractive etching in producing fine circuitry. Therefore, addressing these issues and improving the precision of subtractive etching for fine circuitry is an urgent problem to solve.

[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing a packaging substrate, which solves the problems of difficulty in manufacturing fine lines when using the subtractive method to manufacture the circuits of the packaging substrate, due to poor side etching, electroplating uniformity, and nozzle pressure causing different etching capabilities at different locations.

[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a packaging substrate. The method includes first obtaining pattern compensation values ​​through pilot production, then modifying existing process parameters based on the obtained pattern compensation values, and mass-producing the packaging substrate using the same electroplating production line, etching production line, and board placement rules as during pilot production. The step of obtaining the pattern compensation values ​​through pilot production includes the following steps:

[0006] S1: Prepare the test substrate and electroplate copper on the test substrate to form the required target copper thickness;

[0007] S2: Divide the test substrate into multiple grids and measure the copper thickness at multiple points in different grids to obtain the copper thickness distribution value;

[0008] S3: Form a resist layer on the test substrate and expose it. During the exposure process, different compensations are applied to different exposure patterns. The compensation value is selected from any one of 0, n and n+N×m, where n is the line width, m is the minimum exposure adjustment value, and N is an integer greater than or equal to 1.

[0009] S4: Develop the exposed resist layer;

[0010] S5: Etch the circuit and remove the residual resist layer, and use an additional 2oz thick copper plate for simultaneous etching during the etching process.

[0011] S6: Measure the linewidth distribution value of each etched line;

[0012] S7: Match the copper thickness distribution value obtained in step S2 with the copper plate etching uniformity distribution value in step S5, and compare it with the line width distribution value of the etched circuit to obtain the relationship between the line width distribution value and the copper plating thickness uniformity and etching uniformity of the test substrate, and obtain the pattern compensation value based on the actual measurement results.

[0013] Optionally, the process of preparing the test substrate includes:

[0014] 1) Create the core board pattern;

[0015] 2) A dielectric layer, a first copper foil layer, and a second copper foil layer are formed on the core board and then laminated.

[0016] 3) Fabricate interconnect holes;

[0017] 4) Clean the core board;

[0018] 5) Deposit a copper layer on the surface of the core board.

[0019] Optionally, the roughness of the first copper foil layer and the second copper foil layer is less than 2 μm.

[0020] Optionally, the method for cleaning the core board includes chemical cleaning; the thickness of the copper oxide layer deposited on the surface of the core board is 0.5μm-1μm.

[0021] Optionally, the copper foil used in the core board includes electrolytic copper foil and / or rolled copper foil.

[0022] The organic materials used in the optional core board include glass fiber cloth coated with resin copper clad laminate, and the resin includes several of epoxy resin, high temperature resistant epoxy resin, polyimide resin, bismaleimide modified triazine resin, polysulfone resin and polyphenylene ether resin.

[0023] Optionally, in step S1, electroplating may be performed using a vertical continuous electroplating line or a horizontal electroplating line.

[0024] Optionally, the resist layer in step S3 is a dry film layer.

[0025] Optionally, in step S2, both the upper and lower surfaces of the test substrate are divided into a×b grids, where a and b are both integers greater than 1.

[0026] Optionally, there are no fewer than 3 measurement points in each grid. Based on the measurement data, a copper thickness contour map of each electroplating line is established, and the board placement rules of each electroplating line are recorded and matched with the subsequent etching line database.

[0027] Optionally, the board placement rules for the etching lines include: the substrate surface has anti-reverse holes, the placement direction of each substrate is consistent, the distance between the board edge and the equipment edge is consistent, and the distance between boards is consistent.

[0028] Optionally, step S3 further includes a step of pretreating the test substrate with a roughening solution before forming a dry film layer on the test substrate.

[0029] Optionally, during the development process in step S4, the development point is 30%-50%.

[0030] Optionally, the etching in step S5 is performed in a vacuum etching apparatus or a vacuum two-fluid etching apparatus.

[0031] As described above, the method for manufacturing a packaging substrate provided by the present invention has the following beneficial effects: The improved process design of the present invention allows for sample production before formal production. During the sample production process, different exposure compensation values ​​are selected for different patterns, and the line width, spacing, and copper thickness are measured. These measurements are then matched with the copper thickness contour distribution data (distribution map) established after electroplating to find the etching topography map. Based on the relationship between the compensation values ​​of electroplated copper thickness and line width and the etching uniformity, as well as the actual measurement results, the line width compensation value is revised. Finally, etching is performed based on the revised line width compensation value. This can greatly improve the consistency of fine circuit fabrication on the entire surface of the packaging substrate, reduce the scrap rate, and thus increase economic benefits. Attached Figure Description

[0032] Figure 1 The diagram shown illustrates the board routing direction and sampling method of etching line #1 in an embodiment of the present invention.

[0033] Figure 2 The diagram shown is a contour plot of the W / W μm linewidth distribution of a 20 μm thick copper plate in an embodiment of the present invention.

[0034] Figure 3 The diagram shown is a contour map of the etching uniformity of etching line #1 in an embodiment of the present invention.

[0035] Figure 4 The diagram shown is a contour map illustrating the electroplating uniformity of electroplating line #1 in an embodiment of the present invention.

[0036] Figure 5 and Figure 6 The images shown are comparison diagrams of the graphic design before and after optimized exposure compensation under the No. 1 electroplating line and the No. 1 etching line in the embodiments of the present invention.

[0037] Figure 7 The image shown is a comparison of the yield of Set6 before and after optimized exposure compensation in an embodiment of the present invention. Detailed Implementation

[0038] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0039] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0040] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0042] This invention provides a method for manufacturing a packaging substrate. The method includes first obtaining pattern compensation values ​​through pilot production, then modifying existing process parameters based on the obtained pattern compensation values, and finally manufacturing mass-production packaging substrates based on the same electroplating production line, etching production line, and board placement rules as during pilot production. That is, pilot production and subsequent formal production are carried out on the same electroplating and etching production lines, and the board placement rules in each process are completely consistent. The step of obtaining pattern compensation values ​​through pilot production includes the following steps:

[0043] S1: Prepare the test substrate and electroplate copper on the test substrate to form the required target copper thickness;

[0044] S2: Divide the test substrate into multiple grids and measure the copper thickness at multiple points in different grids to obtain the copper thickness distribution value;

[0045] S3: Form a resist layer on the test substrate and expose it. During the exposure process, different compensations are applied to different exposure patterns. The compensation value is selected from any one of 0, n and n+N×m, where n is the line width of the electroplated line, m is the minimum exposure adjustment value, which is related to the exposure equipment used. For example, in this embodiment, the minimum exposure adjustment value is 2.5μm, and N is an integer greater than or equal to 1.

[0046] S4: Develop the exposed resist layer;

[0047] S5: Etch the circuit and remove the residual dry film. During the etching process, an additional 2oz thick copper plate is used for synchronous etching.

[0048] S6: Measure the linewidth distribution value of each etched line;

[0049] S7: Match the copper thickness distribution value obtained in step S2 with the copper plate etching uniformity distribution value in step S5, and compare it with the line width distribution value of the etched line to obtain the relationship between the line width distribution value and the copper plating thickness uniformity and etching uniformity of the test substrate, and obtain the pattern compensation value based on the actual measurement results.

[0050] It should be noted that there is no strict distinction between the above steps. For example, the electroplating in step S1 and the measurement in step S2 can be considered as the same step, as long as the corresponding operations are performed.

[0051] The improved process design of this invention involves sample production before formal production (mass production). During sample production, different exposure compensation values ​​are selected for different patterns, and the line width, spacing, and copper thickness are measured. These measurements are then matched with the copper thickness contour distribution data (distribution map) established after electroplating to find the etching topography map. Based on the relationship between the compensation values ​​of electroplated copper thickness and line width and the etching uniformity, as well as the actual measurement results, the line width compensation values ​​are revised. Finally, etching is performed based on the revised line width compensation values. This can greatly improve the consistency of fine circuit fabrication on the entire surface of the packaging substrate, reduce the scrap rate, and thus increase economic benefits.

[0052] The present invention will now be further described with reference to specific embodiments. In this application, the process of preparing the test substrate can begin with the fabrication of the core board, or it can begin with providing a substrate whose core board pattern has already been fabricated; the specific process is not limited, but the important thing is that the trial production and mass production processes are completely consistent. To fully demonstrate the fabrication process of the packaging substrate, this embodiment will begin with the fabrication process of the core board.

[0053] First, the core board pattern is fabricated. The copper foil used in the core board can be electrolytic copper foil, rolled copper foil, or a combination of both types, but usually only one is selected. The organic material used in the core board is preferably glass fiber cloth coated with resin copper clad laminate, but it is not limited to this. The resin can be several of the following: epoxy resin, high-temperature resistant epoxy resin, polyimide resin (PI), bismaleimide modified triazine resin (BT), polysulfone resin, and polyphenylene ether resin (PPO).

[0054] Next, a dielectric layer, a first copper foil layer, and a second copper foil layer are formed on the core board and then laminated. The dielectric layer can be, but is not limited to, a photosensitive epoxy resin layer, and can be formed by coating or lamination. Preferably, the roughness Rz of the first copper foil layer and the second copper foil layer is less than 2 μm. Lower roughness ensures that defects such as the shedding of circuit layers will not occur during subsequent etching.

[0055] Then, interconnect holes are fabricated on the core board; these are referred to here as interconnect holes. Interconnect holes can be through holes, blind holes, or a combination of both. Interconnect holes can be fabricated using laser drilling or mechanical drilling methods.

[0056] After drilling, drilling smudges will remain on the test substrate, requiring desmudge removal. In this embodiment, chemical desmudge removal is preferred. This is because removing drilling smudges chemically increases the surface roughness of the substrate, allowing for better adhesion between the substrate and the copper plating layer.

[0057] Next, chemical copper plating is performed as a seed layer for the circuit, for example, depositing a 0.5μm to 2μm copper plating layer on the substrate surface.

[0058] After chemical copper plating, electroplating is performed. Vertical continuous plating lines or horizontal plating lines are preferred during the electroplating process to reduce the difference in copper thickness within the same substrate and between substrates, which helps in the fabrication of fine circuitry. Each plating line is plated to the target copper thickness. The test substrate's surface is then arranged according to the subsequent graphic design delivery units (Units). For example, the upper and lower surfaces of the test substrate are divided into a×b grids (where a and b are integers greater than 1). Copper thickness is measured using a copper thickness gauge, collecting at least 3 data points per grid to obtain the copper thickness distribution value. In this embodiment, a copper thickness contour map is created based on the obtained values, and subsequent data are also mapped accordingly. Creating contour maps makes the data more intuitive and simplifies subsequent data comparison; for example, a fitting method can be used for data comparison. In a specific example, since the subsequent graphic design consists of 12 Units per surface, the test substrate is divided into 2×6 grids, corresponding to the Units. Three data points are measured for each Unit, and the test results are as follows: Figure 4 As shown. At this point, the copper thickness contour map of each electroplating line should be collected, and the board placement rules of each electroplating line should be recorded, and then matched with the subsequent etching line database.

[0059] Typically, the electroplating process in a factory will simultaneously control the average copper thickness, the uniformity of copper thickness variation, and the process capability of each batch of boards. Only test boards that pass the control process will proceed to the next step.

[0060] After electroplating, a resist layer is formed on the substrate surface; in this embodiment, a dry film is used. The dry film fully meets the precision requirements of this embodiment. Furthermore, compared to photoresist coating, using a dry film method helps improve production efficiency and reduce production costs. In a preferred example, the substrate is pretreated before applying the dry film, for example, using a roughening solution. Applying the dry film to the electroplated surface afterward enhances the adhesion between the dry film and the substrate.

[0061] The next step is exposure. The exposure method can be selected as needed, such as based on the exposure linewidth and / or the material of the resist layer. Maskless exposure can be chosen provided the exposure linewidth is met. After exposure, the exposed area of ​​the dry film is modified and becomes insoluble in the developer. Therefore, in subsequent etching processes, the exposed area resists etching, protecting the copper traces underneath. Theoretically, the width of the exposed dry film should be the same as the width of the unetched area underneath. However, in actual processes, because the etchant seeps into the bottom of the exposed area, some of the traces at the bottom of the exposed area are also etched away, resulting in an image smaller than the target linewidth. Therefore, to obtain the target linewidth, compensation is added during exposure to increase the exposure size. The added compensation value is crucial for obtaining the accurate target linewidth. In this embodiment, different levels of compensation are applied to different exposure patterns during exposure. Specifically, the compensation values ​​for different exposure patterns are: 0, n, n+m, n+2m, n+3m, n+4m, n+5m…, where n is the line width of the electroplating line, and m is the minimum exposure adjustment unit, the specific value of which is related to the exposure equipment. For example, in one example, m is 2.5μm, and there are 5 exposure patterns. The exposure compensation values ​​for these 5 patterns are 0 (i.e., exposure according to the baseline value), n, n+2.5, n+2×2.5, and n+3×2.5, respectively. By applying different levels of compensation to different exposure patterns, the optimal compensation value is found.

[0062] After exposure, development is performed. A preferred development method is horizontal spray development, where the developer is maintained at a constant temperature, and the test substrate moves forward under the drive of a roller. Preferably, in this embodiment, the development point is controlled between 30% and 50%.

[0063] Next, the etching process is performed. The contour map of the linewidth for each etched line is collected, and the placement rules for each etched line are recorded, corresponding to the copper thickness contour map of the aforementioned electroplating lines. For ultra-fine circuit fabrication, vacuum etching equipment or vacuum two-fluid etching equipment is preferred to reduce lateral etching problems caused by the pooling effect on the surface of the packaging substrate. Simultaneously, placement rules for each etched line are specified, such as the substrate surface must have anti-reverse vias, each board must be placed in the same direction, the distance between the board edge and the equipment edge must be consistent, and the distance between boards must be consistent, ensuring the uniformity of each etched line is stable and reliable.

[0064] In addition, in this embodiment, a 2oz thick copper plate is also used for etching while etching the test substrate to obtain the etching uniformity results of the etched lines. These results are then compared one-to-one with the linewidth distribution map and the electroplating uniformity distribution map. The test results are as follows: Figure 3 As shown.

[0065] After etching is completed, the residual dry film is removed. For example, organic or inorganic film remover can be used to remove the dry film on the circuit. In this embodiment, an inorganic film remover is used.

[0066] Next, linewidth and spacing are measured, and linewidth data for each etched line is collected to obtain a contour map. The copper thickness contour map established after electroplating in the previous steps is matched with the etching uniformity map of the thick copper plate after etching, and compared with the etched linewidth distribution topography map to find the relationship between the linewidth distribution and the uniformity of the electroplated copper thickness and etching uniformity of the test substrate. Based on the measured results, the linewidth compensation values ​​are revised. The optimized compensation values ​​for the corresponding electroplated and etched lines are collected and recorded for use in the subsequent mass production of fine circuitry on the board.

[0067] The difference between the compensation modification method in this embodiment and the existing method of uniformly modifying the compensation of each Unit is that this invention modifies the compensation value of a Unit at a specific location, rather than modifying the same graphic design data for the compensation of every Unit. For example, as Figure 5 In the graphic design, there are a total of 12 Units. The compensation values ​​of all Units on the left side of Set6 remain unchanged. Only the compensation values ​​of the two Units at the bottom of Set6 are modified for etching uniformity.

[0068] In this embodiment, the board routing direction and sampling method of etching line #1 are as follows: Figure 1 As shown. The tracing direction refers to the direction of movement of the substrate in the equipment. For example, the substrate is placed in the roller of the equipment and immersed in the etching solution. As the roller moves, the substrate moves forward. Figure 1 Each small box in each Set represents a sampling location. It is specified that eight locations are selected for testing in Set1, Set3, and Set6 respectively, with three data points measured at each sampling location. The measurement results of the W / Wμm linewidth distribution of a 20μm thick copper plate are represented by a contour map as shown below. Figure 2 As shown, it is evident that the linewidth at position Set6 is too low, deviating significantly from the target value of Wμm. Therefore, it is necessary to analyze the reason for the small linewidth at position Set6. The analysis process includes: examining the etching uniformity using a thick copper plate on the same etching production line, and drawing an etching topography map. The results are as follows. Figure 3 As shown, it is quite obvious that the etching amount at position Set6 is too large, compared to... Figure 2 The results were consistent. Further examination of the electroplating uniformity in the preceding process (plating line #1) yielded the following results: Figure 4 As shown, the copper thickness after electroplating is relatively uniform in Set1, Set3, and Set6. Figure 3 By comparison, we can conclude that Figure 2 The reason why the line width of Set6 is relatively small is mainly due to the etching uniformity.

[0069] Therefore, when the etching uniformity of the etched lines cannot be adjusted, the relationship between the compensation values ​​of the electroplated copper thickness and line width and the etching uniformity can be found. Based on the measured results, the line width compensation value can be revised, with a focus on optimizing the exposure compensation of Set6 throughout the board to improve the yield of fine lines. The figures before and after the compensation adjustment are shown below. Figure 5 and Figure 6 As shown, since Set6 has a large etching amount, appropriate compensation can be added to Set6 separately.

[0070] After obtaining the optimized compensation value through the aforementioned steps, the existing process parameters are corrected. Based on the corrected process parameters, the same procedures as when manufacturing the test substrate are followed (i.e., electroplating, exposure, development, and etching are performed sequentially after the substrate is provided; however, measurement of each substrate is not required after each step, but sampling inspection can be used to correct the previous optimized compensation value). Mass production of the fine circuitry of the production board is carried out using the same electroplating production line, etching production line, and board placement rules as during pilot production. It should be noted that the above pilot production process usually only needs to be performed once, but it can be performed more than twice if necessary. Each pilot production run can use one or more test substrates. The key is to ensure that all pilot production runs are conducted under completely identical conditions to the formal mass production. The average compensation value obtained from all test substrates can be used as the final optimized compensation value.

[0071] It is important to emphasize again that the method of this invention presupposes a fixed electroplating production line, etching production line, and board placement rules. For example, if a production board is to be manufactured using electroplating line #1 and etching line #3, and the board placement rules for etching and electroplating are specified, then the optimized compensation value obtained from the test board produced by electroplating line #1 and etching line #3 in the first step should be selected for the production board. Different etching lines, electroplating lines, and board placement rules will all affect the uniformity of copper thickness to some extent. Fixing the electroplating production line, etching production line, and board placement rules ensures that the optimized compensation value is applied in a targeted manner. In this embodiment, the optimized compensation value of the test board produced using electroplating line #1 and etching line #1 ( Figure 6 After that, the open / short circuit yield rate of the circuit was tested, and the test results were as follows: Figure 7 As shown, the yield of Set6 increased from 40.91% to 95.45%, with a significant improvement in the yield of fine lines, which greatly reduces scrap costs for the factory.

[0072] In summary, the improved process design of this invention allows for sample production before formal production. During sample production, different exposure compensation values ​​are selected for different patterns, and linewidth, spacing, and copper thickness are measured. These measurements are then matched with the copper thickness contour distribution data (distribution map) established after electroplating to identify the etching topography. Based on the relationship between the compensation values ​​for electroplated copper thickness and linewidth and etching uniformity, as well as the measured results, the linewidth compensation values ​​are revised. Finally, etching is performed based on the revised linewidth compensation values. This significantly improves the consistency of fine circuit fabrication across the entire packaging substrate, reduces scrap rates, and thus increases economic benefits. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a packaging substrate, characterized in that, The manufacturing method includes first obtaining pattern compensation values ​​through pilot production, then correcting existing process parameters based on the obtained pattern compensation values, and manufacturing mass-production packaging substrates based on the same electroplating production line, etching production line, and board placement rules as during pilot production. The process of obtaining pattern compensation values ​​through pilot production includes the following steps: S1: Prepare the test substrate and electroplate copper on the test substrate to form the required target copper thickness; S2: Divide the test substrate into multiple grids and measure the copper thickness at multiple points in different grids to obtain the copper thickness distribution value; S3: Form a resist layer on the test substrate and expose it. During the exposure process, different compensations are applied to different exposure patterns. The compensation value is selected from any one of 0, n and n+N×m, where n is the line width, m is the minimum exposure adjustment value, and N is an integer greater than or equal to 1. S4: Develop the exposed resist layer; S5: Etch the circuit and remove the residual resist layer, and use an additional 2oz thick copper plate for simultaneous etching during the etching process. S6: Measure the linewidth distribution value of each etched line; S7: Match the copper thickness distribution value obtained in step S2 with the copper plate etching uniformity distribution value in step S5, and compare it with the line width distribution value of the etched line. Match the obtained electroplated copper thickness distribution value, etching uniformity distribution value and the line width distribution value of the etched line according to the board placement rules of the test substrate to obtain the relationship between the line width distribution value and the electroplated copper thickness uniformity and etching uniformity of the test substrate. Determine the graphic compensation value at the corresponding position according to the difference between the line width compensation value and the target line width. In step S2, the upper and lower surfaces of the test substrate are divided into a×b grids, where a and b are both integers greater than 1; there are no less than 3 measurement points in each grid, and a copper thickness contour map of each electroplating line is established based on the measurement data, and the board placement rules of each electroplating line are recorded to correspond with the etching data results generated by the subsequent etching process. The board placement rules for etching lines include: the substrate surface has anti-reverse holes, the placement direction of each substrate is consistent, the distance between the board edge and the equipment edge is consistent, and the distance between boards is consistent.

2. The manufacturing method according to claim 1, characterized in that, The process of preparing the test substrate includes: 1) Create the core board pattern; 2) A dielectric layer, a first copper foil layer, and a second copper foil layer are formed on the core board and then laminated. 3) Fabricate interconnect holes; 4) Clean the core board; 5) Deposit a copper layer on the surface of the core board.

3. The manufacturing method according to claim 2, characterized in that, The roughness of the first and second copper foil layers is less than 2 μm; the methods for cleaning the core board include chemical cleaning; the thickness of the copper oxide layer deposited on the core board surface is 0.5 μm-1 μm.

4. The manufacturing method according to claim 2, characterized in that, The copper foil used in the core board includes electrolytic copper foil and / or rolled copper foil; the organic materials used in the core board include glass fiber cloth coated with resin copper clad laminate, and the resin includes several of epoxy resin, high temperature resistant epoxy resin, polyimide resin, bismaleimide modified triazine resin, polysulfone resin and polyphenylene ether resin.

5. The manufacturing method according to claim 1, characterized in that, In step S1, electroplating uses a vertical continuous electroplating line or a horizontal electroplating line, and in step S3, the resist layer used is a dry film layer.

6. The manufacturing method according to claim 1, characterized in that, In step S3, before forming the resist layer on the test substrate, a pretreatment step of using a roughening solution to treat the test substrate is also included.

7. The manufacturing method according to claim 1, characterized in that, During the development process in step S4, the development point is 30%-50%.

8. The manufacturing method according to claim 1, characterized in that, The etching in step S5 is performed in a vacuum etching apparatus or a vacuum two-fluid etching apparatus.

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