Semiconductor manufacturing apparatus component

Abstract

Provided is a semiconductor manufacturing device component that can suppress discharge between a wafer and a conductive substrate. The semiconductor manufacturing device component (10) includes a ceramic plate (20), a metal joining layer (40) and a cooling plate (30) (conductive substrate) provided on the lower surface of the ceramic plate (20), a first hole (24) that penetrates the ceramic plate (20) in the vertical direction, and a through hole (42) and a gas hole (34) (second hole) that penetrate the conductive component in the vertical direction and communicate with the first hole (24). The upper surface of a porous plug (50) is exposed at the upper opening of the first hole (24), and the lower surface is below the upper surface of the conductive substrate. The upper surface of an insulating tube (60) is positioned lower than the wafer placement surface (21), and the lower surface is positioned lower than the lower surface of the porous plug (50). An integrated component (As) is obtained by integrating the porous plug (50) and the insulating tube (60), and the outer peripheral surface is fixed to the first hole (24) and the second hole by an adhesive layer (70) from the upper surface of the first hole (24) to the inside of the second hole.

Description

TECHNICAL FIELD

[0001] The present application relates to a member for a semiconductor manufacturing apparatus. BACKGROUND

[0002] In the past, as a member for a semiconductor manufacturing apparatus, a member for a semiconductor manufacturing apparatus having an electrostatic chuck having a wafer mounting surface on an upper surface is known. For example, with respect to the electrostatic chuck of Patent Literature 1, it is disclosed that the electrostatic chuck has a ceramic plate that adsorbs and holds a wafer, a through hole formed in the ceramic plate, a porous plug disposed in the through hole, and a conductive cooling plate bonded to a lower surface of the ceramic plate. A lower surface of the porous plug coincides with a lower surface of the ceramic plate. In a case where a wafer mounted on the wafer mounting surface is processed by plasma, high-frequency power is applied between the cooling plate and a flat plate electrode disposed on an upper portion of the wafer, so that plasma is generated on the upper portion of the wafer. At the same time, in order to increase heat conduction of the wafer and the ceramic plate, helium as a heat conduction gas is supplied to a back surface of the wafer via the porous plug. If the porous plug is not present, electrons generated by ionization of the helium accelerate and collide with other helium, so that arc discharge occurs. However, if the porous plug is present, the electrons collide with the porous plug before colliding with the other helium, so that the arc discharge is suppressed.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2019-29384 SUMMARY

[0006] However, as the process is made higher in power, a potential difference generated between the wafer and the cooling plate increases, and in the above-described electrostatic chuck, since the porous plug itself has a low withstand voltage, spark discharge occurs in the porous plug, and the wafer is sometimes deteriorated.

[0007] The present application has been made to solve the above-described problems, and a main object thereof is to provide a member for a semiconductor manufacturing apparatus having a porous plug, which can suppress arc discharge and spark discharge between a wafer and a conductive base material.

[0008] The member for a semiconductor manufacturing apparatus of the present application has:

[0009] a ceramic plate having a wafer mounting surface on an upper surface;

[0010] a conductive base material disposed on a lower surface of the ceramic plate;

[0011] a first hole that penetrates the ceramic plate in a vertical direction;

[0012] a second hole that penetrates the electrically conductive substrate in the up-down direction and communicates with the first hole;

[0013] a porous plug whose upper surface is exposed at the upper opening of the first hole and whose lower surface is located below the upper surface of the electrically conductive substrate;

[0014] an insulating tube whose upper surface is located lower than the wafer mounting surface and whose lower surface is located lower than the lower surface of the porous plug; and

[0015] an integrated member that is obtained by integrating the porous plug and the insulating tube, the outer peripheral surface of which is fixed to the first hole and the second hole by the adhesive layer from the upper surface of the first hole to the inside of the second hole.

[0016] In the semiconductor manufacturing apparatus member, the lower surface of the porous plug is located below (preferably, lower than) the upper surface of the electrically conductive substrate. In the case where the lower surface of the porous plug is located higher than the upper surface of the electrically conductive substrate, arc discharge occurs between the lower surface of the porous plug and the electrically conductive substrate, in contrast to which, in the case where the lower surface of the porous plug is located below the upper surface of the electrically conductive substrate, the arc discharge can be suppressed. In addition, the lower surface of the insulating tube is located lower than the lower surface of the porous plug. Therefore, the distance from the wafer to the electrically conductive substrate is longer than in the case where the insulating tube is not present, and spark discharge in the porous plug can be suppressed. Thus, the semiconductor manufacturing apparatus member provided with the porous plug can suppress arc discharge and spark discharge between the wafer and the electrically conductive substrate.

[0017] Note that, in the present specification, up-down, left-right, front-rear, and the like are sometimes used to describe the present application, but up-down, left-right, front-rear are merely relative positional relationships. Thus, in the case where the orientation of the semiconductor manufacturing apparatus member is changed, up-down can become left-right, or left-right can become up-down, and such cases are also included in the technical scope of the present application.

[0018] In the semiconductor manufacturing apparatus member of the present application, the width of the adhesive layer can be wider outside the radius in the inside of the second hole than in the inside of the first hole. Thus, in the case where the adhesive layer is formed with an adhesive, the generation of bubbles in the adhesive in the inside of the second hole can be suppressed, and the adhesive can be filled.

[0019] In the semiconductor manufacturing apparatus component of the present application, the inner peripheral surface of the second hole can have a diameter-increasing portion in which the diameter increases from the lower portion toward the upper portion, and the adhesive layer can be present between the diameter-increasing portion and the insulating tube. Even in this case, it is easy to prevent the adhesive inside the second hole from generating bubbles when the adhesive layer is formed with an adhesive.

[0020] In the semiconductor manufacturing apparatus component of the present application, the insulating tube can have a bottomed hole in the upper portion of the tube, and the porous plug can be held in a state of being inserted into the bottomed hole. According to this, it is not necessary to perform complicated shape processing on the relatively fragile porous plug.

[0021] In the semiconductor manufacturing apparatus component of the present application, the wafer placement surface can have a plurality of small protrusions that support the wafer, and the upper surface of the porous plug can be positioned lower than the upper surfaces of the small protrusions. According to this, the wafer is not lifted by the upper surface of the porous plug. In this case, the upper surface of the porous plug can be positioned at the same height as a reference surface of the wafer placement surface on which the small protrusions are not provided, or can be positioned at a position lower than the reference surface by 0.2 mm or less. According to this, since the height of the space between the back surface of the wafer and the upper surface of the porous plug is suppressed to a low level, it is possible to prevent arcing from occurring in the space. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a longitudinal sectional view of the semiconductor manufacturing apparatus component 10.

[0023] Figure 2 is a plan view of the ceramic plate 20.

[0024] Figure 3 is a partial enlarged view of Figure 1 .

[0025] Figure 4 is a manufacturing process diagram of the integrated component As.

[0026] Figure 5 is a manufacturing process diagram of the semiconductor manufacturing apparatus component 10.

[0027] Figure 6 is a partial enlarged view showing the adhesive layer 170 and its periphery.

[0028] Figure 7 is a partial enlarged view showing a modification of the porous plug 50.

[0029] Figure 8 is a partial enlarged view showing a modification of the porous plug 50.

[0030] Figure 9is a partial enlarged view showing the porous plug 250 and its periphery.

[0031] Figure 10 is a partial enlarged view showing the porous plug 350 and its periphery.

[0032] Explanation of symbols

[0033] 10 semiconductor manufacturing apparatus component, 20 ceramic plate, 21 wafer mounting surface, 21a seal band, 21b circular small protrusion, 21c reference surface, 22 electrode, 24 first hole, 24a hole upper portion, 24b hole lower portion, 30 cooling plate, 32 coolant flow path, 34 gas hole, 34a gas hole periphery, 40 metal joining layer, 40a upper surface, 42 through hole, 50 porous plug, 50a upper surface, 50b lower surface, 52 holding layer, 60 insulating tube, 60a upper surface, 60b lower surface, 62 gas passage, 64 bottomed hole, 90 metal joining material, 92 spare hole, 94 joined body, 170 adhesive layer, 220 ceramic plate, 224 first hole, 230 cooling plate, 234 gas hole, 240 metal joining layer, 242 through hole, 250 porous plug, 252 bottomed hole, 260 insulating tube, 270 adhesive layer, 350 porous plug. DETAILED DESCRIPTION

[0034] Next, the preferred embodiment of the present application will be described using the drawings. Figure 1 is a longitudinal sectional view of the semiconductor manufacturing apparatus component 10, Figure 2 is a plan view of the ceramic plate 20, Figure 3 is Figure 1 a partial enlarged view of

[0035] The semiconductor manufacturing apparatus component 10 is provided with a ceramic plate 20, a cooling plate 30, a metal joining layer 40, a porous plug 50, and an insulating tube 60.

[0036] The ceramic plate 20 is a ceramic-made circular plate (for example, 300 mm in diameter, 5 mm in thickness) of an alumina sintered body, an aluminum nitride sintered body, or the like. The upper surface of the ceramic plate 20 is a wafer mounting surface 21. The ceramic plate 20 has an electrode 22 built therein. As shown in Figure 2As shown, a seal band 21a is formed along the outer edge of the wafer mounting surface 21 of the ceramic plate 20, and a plurality of circular small projections 21b are formed on the entire surface. The seal band 21a and the circular small projections 21b are the same height, and the height is, for example, several μm to several tens of μm. The electrode 22 is a planar mesh electrode that functions as an electrostatic electrode and is capable of applying a direct current voltage. When a direct current voltage is applied to the electrode 22, the wafer W is adsorbed and fixed to the wafer mounting surface 21 (specifically, the upper surfaces of the seal band 21a and the circular small projections 21b) by electrostatic adsorption force, and when the application of the direct current voltage is released, the wafer W is released from the adsorption and fixation to the wafer mounting surface 21. Note that the portion of the wafer mounting surface 21 on which the seal band 21a and the circular small projections 21b are not provided is referred to as a reference surface 21c.

[0037] A first hole 24 is provided in the ceramic plate 20. The first hole 24 is a through hole that penetrates the ceramic plate 20 and the electrode 22 in the up-down direction. As shown, Figure 3 The first hole 24 is a stepped hole, and the hole upper portion 24a is thin, and the hole lower portion 24b is thick. That is, the first hole 24 is a hole in which the thin-diameter cylindrical hole upper portion 24a and the thick-diameter cylindrical hole lower portion 24b are connected. The first hole 24 is provided at a plurality of positions (for example, a plurality of positions provided at equal intervals in the circumferential direction) of the ceramic plate 20.

[0038] The cooling plate 30 is a circular plate (a circular plate having a diameter equal to or greater than the diameter of the ceramic plate 20) having a high thermal conductivity. Inside the cooling plate 30, a coolant flow path 32 through which a coolant circulates, and a gas hole 34 through which gas is supplied to the porous plug 50 are formed. The coolant flow path 32 is formed in one stroke from the inlet to the outlet on the entire surface of the cooling plate 30 in plan view. The gas hole 34 is a cylindrical hole that is provided coaxially with and in communication with the first hole 24. The diameter of the gas hole 34 is greater than the diameter of the hole lower portion 24b of the first hole 24. The material of the cooling plate 30 can be, for example, a metal material, a metal matrix composite (MMC), or the like. As the metal material, Al, Ti, Mo, or an alloy thereof, or the like can be given. As the MMC, a material containing Si, SiC, and Ti (also referred to as SiSiCTi), a material obtained by impregnating Al and / or Si in a SiC porous body, or the like can be given. As the material of the cooling plate 30, a material having a thermal expansion coefficient close to that of the material of the ceramic plate 20 is preferably selected. The cooling plate 30 also functions as an RF electrode. Specifically, an upper electrode (not shown) is disposed above the wafer mounting surface 21, and if high-frequency power is applied between the parallel-plate electrodes composed of the upper electrode and the cooling plate 30 built in the ceramic plate 20, plasma is generated.

[0039] The metal joining layer 40 joins the lower surface of the ceramic plate 20 and the upper surface of the cooling plate 30. The metal joining layer 40 is formed by, for example, TCB (Thermal compression bonding). TCB refers to a known method in which a metal joining material is sandwiched between two components to be joined, and the two components are press joined in a state in which the temperature is heated to a temperature below the solidus temperature of the metal joining material. The metal joining layer 40 is provided with a through-hole 42 that penetrates in the up-and-down direction in a manner that communicates with the first hole 24 of the ceramic plate 20 and the gas hole 34 of the cooling plate 30. The diameter of the through-hole 42 is the same as the diameter of the gas hole 34. The metal joining layer 40 and the cooling plate 30 of the present embodiment correspond to the electrically conductive substrate of the present application, and the through-hole 42 and the gas hole 34 of the present embodiment correspond to the second hole of the present application.

[0040] The porous plug 50 is a porous cylindrical component that allows gas to flow in the up-and-down direction. The porous plug 50 is formed of an electrically insulating material such as alumina. The upper surface 50a of the porous plug 50 is exposed at the upper opening of the first hole 24 and is the same plane as the reference surface 21c. Note that the term "same" includes not only the case in which they are completely the same, but also the case in which they are substantially the same (for example, the case in which they fall within the range of tolerance) (hereinafter, the same). The lower surface 50b of the porous plug 50 is located below the upper surface 40a of the metal joining layer 40, and is located inside the through-hole 42 (further below than the upper surface 40a of the metal joining layer 40).

[0041] The insulating tube 60 is a cylindrical tube formed of a dense ceramic, and has a gas passage 62 inside. The insulating tube 60 is provided with a bottomed hole 64 at the upper portion thereof, the diameter of which is larger than the diameter of the gas passage 62. The upper surface 60a of the insulating tube 60 is located at a position further below than the wafer placement surface 21, and the lower surface 60b of the insulating tube 60 is located at a position further below than the lower surface 50b of the porous plug 50, and is located inside the gas hole 34 of the cooling plate 30. The integrated component As is configured by the insulating tube 60 and the porous plug 50 being integrated. The integrated component As is held by the holding layer 52 formed of an adhesive in a state in which the porous plug 50 is inserted into the bottomed hole 64 of the insulating tube 60. A gap is present between the bottom surface of the bottomed hole 64 and the lower surface 50b of the porous plug 50. By providing this gap, the height of the porous plug 50 is easily adjusted.

[0042] The integrated member As is inserted into the gas hole 34, the through hole 42, and the first hole 24. The outer peripheral surface of the integrated member As is fixed to the first hole 24, the through hole 42, and the gas hole 34 by the adhesive layer 70 formed by the upper opening edge of the first hole 24 of the ceramic plate 20 to the inside of the gas hole 34 of the cooling plate 30 and by the adhesive. The width of the adhesive layer 70 in the horizontal direction is narrower in the hole upper portion 24a of the first hole 24, wider in the through hole 42 and the gas hole 34, and intermediate in the hole lower portion 24b of the first hole 24. That is, the width of the adhesive layer 70 inside the through hole 42 and the gas hole 34 is wider on the outer side of the radius than the width of the adhesive layer 70 inside the first hole 24. Therefore, the adhesive layer 70 inside the gas hole 34 is less likely to generate a bubble. Hereinafter, this point will be described.

[0043] Next, an example of use of the semiconductor manufacturing apparatus member 10 configured as described above will be described. First, in a state where the semiconductor manufacturing apparatus member 10 is disposed in a chamber not shown, a wafer W is loaded on the wafer loading surface 21. Then, the chamber is depressurized by a vacuum pump, and adjusted to a predetermined degree of vacuum, a direct current voltage is applied to the electrode 22 of the ceramic plate 20 to generate an electrostatic adsorption force, and the wafer W is adsorbed and fixed to the wafer loading surface 21 (specifically, the upper surface of the sealing band 21a, the upper surface of the circular small protrusion 21b). Next, the chamber is made into a reaction gas atmosphere of a predetermined pressure (for example, several tens to several hundreds of Pa), and in this state, a high-frequency voltage is applied between an upper electrode not shown provided to the top portion of the chamber and the cooling plate 30 of the semiconductor manufacturing apparatus member 10 to generate plasma. The surface of the wafer W is processed by the generated plasma. The coolant circulates in the coolant flow path 32 of the cooling plate 30. A back surface gas is introduced from a gas cylinder not shown to the gas hole 34. As the back surface gas, a heat transfer gas (for example, helium or the like) is used. The back surface gas passes through the gas hole 34, the insulating tube 60, and the porous plug 50, and is supplied to and enclosed in the space between the back surface of the wafer W and the reference surface 21c of the wafer loading surface 21. Due to the presence of the back surface gas, heat transfer between the wafer W and the ceramic plate 20 can be efficiently performed.

[0044] Next, based on Figure 4 and Figure 5 , an example of manufacture of the semiconductor manufacturing apparatus member 10 will be described. Figure 4 is a manufacturing process diagram of the integrated member As, Figure 5 is a manufacturing process diagram of the semiconductor manufacturing apparatus member 10. First, the porous plug 50 and the insulating tube 60 ( Figure 4 (A)) are prepared, an adhesive is applied to the inner peripheral surface of the bottomed hole 64 of the insulating tube 60, the porous plug 50 is inserted into the bottomed hole 64 and adhered, and thus the integrated member As ( Figure 4(B)). The adhesive is cured to become the holding layer 52.

[0045] In addition, the ceramic plate 20, the cooling plate 30, and the metal joining material 90 are prepared (A). Figure 5 (A)). The ceramic plate 20 has the electrode 22 and the first hole 24. The cooling plate 30 has the refrigerant flow path 32 and the gas hole 34. The metal joining material 90 is a joining material in which a spare hole 92 is provided at a position corresponding to the through hole 42.

[0046] Then, the lower surface of the ceramic plate 20 and the upper surface of the cooling plate 30 are joined by TCB to obtain a joined body 94 (B). Figure 5 (B)). The TCB is performed as follows. First, the metal joining material 90 is sandwiched between the lower surface of the ceramic plate 20 and the upper surface of the cooling plate 30 to make a laminate. At this time, the first hole 24 of the ceramic plate 20, the spare hole 92 of the metal joining material 90, and the gas hole 34 of the cooling plate 30 are laminated in a coaxial manner. Then, the laminate is pressure-bonded at a temperature below the solidus temperature of the metal joining material 90 (for example, a temperature of 20°C or more below the solidus temperature and below the solidus temperature), and thereafter, returned to room temperature. Accordingly, the metal joining material 90 becomes the metal joining layer 40, and the spare hole 92 becomes the through hole 42, to obtain the joined body 94 in which the ceramic plate 20 and the cooling plate 30 are joined by the metal joining layer 40. As the metal joining material at this time, an Al-Mg-based joining material or an Al-Si-Mg-based joining material can be used. For example, in the case where the Al-Si-Mg-based joining material is used for the TCB, the laminate is pressure-bonded in a state of being heated in a vacuum atmosphere. The metal joining material 90 preferably uses a joining material having a thickness of about 100 μm.

[0047] Next, an adhesive is applied to the inner peripheral surface of the first hole 24 of the ceramic plate 20, the inner peripheral surface of the through hole 42 of the metal joining layer 40, and the inner peripheral surface of the gas hole 34 of the cooling plate 30. Then, the first hole 24, the through hole 42, and the gas hole 34 are vacuumed in a state in which the upper opening of the first hole 24 is closed, whereby the adhesive is degassed, and the integrated member As is inserted into the above holes 34, 42, and 24. Here, the gap between the inner peripheral surface of the through hole 42 and the outer peripheral surface of the integrated member As, and the gap between the inner peripheral surface of the gas hole 34 and the outer peripheral surface of the integrated member As are wider than the gap between the inner peripheral surface of the first hole 24 and the outer peripheral surface of the integrated member As. Therefore, the adhesive located at the through hole 42 or the gas hole 34 is easily degassed. It is designed that when the upper surface 60a of the insulating tube 60 of the integrated member As hits the step of the first hole 24, the upper surface 50a of the porous plug 50 comes into contact with the reference surface 21c of the wafer mounting surface 21 (refer to FIG. 2). The adhesive is degassed by this contact. The adhesive is degassed by this contact. The adhesive is degassed by this contact. Figure 3) are in the same plane. Thereafter, the adhesive cures to become the adhesive layer 70, and the semiconductor manufacturing apparatus component 10 is obtained Figure 5 (C).

[0048] In the semiconductor manufacturing apparatus component 10 described in detail above, the lower surface 50b of the porous plug 50 is located below the upper surface 40a of the metal joining layer 40. In the case where the lower surface 50b of the porous plug 50 is located at a position higher than the upper surface 40a of the metal joining layer 40, arc discharge occurs between the lower surface 50b of the porous plug 50 and the conductive base material (the metal joining layer 40 and the cooling plate 30). In contrast, in the case where the lower surface 50b of the porous plug 50 is located below the upper surface 40a of the metal joining layer 40, the arc discharge can be suppressed. In addition, the lower surface 60b of the insulating tube 60 is located at a position lower than the lower surface 50b of the porous plug 50. Therefore, compared with the case where the insulating tube is not present, the distance along the surface from the wafer W to the cooling plate 30 is longer, and the spark discharge in the porous plug 50 can be suppressed. Thus, the arc discharge and the spark discharge between the wafer W and the cooling plate 30 can be suppressed.

[0049] In addition, the width of the adhesive layer 70 is wider outside the radius in the inside of the through-hole 42 of the metal joining layer 40 and the inside of the gas hole 34 of the cooling plate 30, compared with the inside of the first hole 24. Therefore, when the adhesive layer 70 is formed with the adhesive, the generation of bubbles in the adhesive at the through-hole 42 and the gas hole 34 can be suppressed, and thus the adhesive can be filled. Thus, the porosity of the adhesive layer 70 at the through-hole 42 and the gas hole 34 can be made smaller.

[0050] Further, the insulating tube 60 has the bottomed hole 64 at the tube upper portion, and the porous plug 50 is adhesively fixed in a state of being inserted into the bottomed hole 64. Therefore, it is not necessary to perform shape processing on the relatively fragile porous plug 50.

[0051] Further, the upper surface 50a of the porous plug 50 is located at a position lower than the upper surface of the sealing tape 21a and the upper surface of the circular small protrusion 21b. Therefore, the wafer W is not lifted up by the upper surface 50a of the porous plug 50.

[0052] Further, the upper surface 50a of the porous plug 50 is at the same height as the reference surface 21c of the wafer mounting surface 21. Therefore, the height of the space between the lower surface of the wafer W and the upper surface 50a of the porous plug 50 is suppressed to a low level. Thus, the arc discharge in the space can be prevented.

[0053] Furthermore, the insulating tube 60 uses an insulating tube with a gas passage 62 diameter smaller than the diameter of the bottom hole 64. Therefore, compared to the case where the inner diameters of the gas passage 62 and the bottom hole 64 are the same, the gas heat transfer is reduced (the insulating tube 60 conducts heat more easily than helium, and the gas heat transfer is reduced due to the increased volume of the insulating tube 60), resulting in good heat uniformity of the wafer W. At the same time, since an insulating distance can be obtained between the gas passage 62 and the cooling plate 30, the insulation withstand voltage is increased.

[0054] It should be noted that the present invention is not limited to any of the above embodiments. Of course, as long as it falls within the technical scope of the present invention, it can be implemented in various ways.

[0055] In the above embodiments, it is possible to... Figure 6 The periphery 34a of the upper opening of the gas hole 34 of the cooling plate 30 is chamfered (C-shaped). The chamfered periphery 34a is an enlarged diameter portion that increases from bottom to top. An adhesive layer 170 exists between the periphery 34a and the insulating tube 60. The inner circumferential surface of the second hole (the through hole 42 of the metal bonding layer 40 and the gas hole 34 of the cooling plate 30) has a periphery 34a as an enlarged diameter portion. Even so, when the adhesive layer 170 is formed with adhesive, it is easy to prevent the formation of air bubbles in the adhesive inside the through hole 42 of the metal bonding layer 40 or the gas hole 34 of the cooling plate 30. The C-chamfer of the periphery 34a is preferably C0.1 or more. Furthermore, the distance d between the side surface of the insulating tube 60 and the side surface of the gas hole 34 is preferably 2 mm or more. Accordingly, the distance from the wafer W to the surface of the cooling plate 30 is sufficiently long. Furthermore, the distance L from the lower surface of the ceramic plate 20 to the lower surface of the adhesive layer 170 is preferably 1 mm or more, more preferably 3 mm or more. Accordingly, the distance along the surface from the wafer W to the cooling plate 30 is sufficiently long. Additionally, the space between the cooling plate 30 and the insulating tube 60 (heat insulation layer) can be sufficiently filled with the adhesive layer 170, which has better thermal conductivity than the space itself, thereby facilitating heat transfer from the insulating tube 60 to the cooling plate 30, thus improving the heat uniformity of the wafer W. Figure 6 In this case, a resin adhesive layer can be used instead of the metal bonding layer 40. The inner circumferential surface of the second hole (the gas hole 34 of the cooling plate 30) also has a periphery 34a as an enlarged diameter portion.

[0056] In the above embodiment, the upper surface 50a of the porous plug 50 is at the same height as the reference surface 21c of the wafer mounting surface 21, but is not particularly limited to this. For example, as Figure 7As shown, the difference Δh obtained by subtracting the height of the upper surface 50a of the porous plug 50 from the height of the reference surface 21c of the wafer mounting surface 21 can be in the range of 0.2 mm or less (preferably 0.1 mm or less). In other words, the upper surface 50a of the porous plug 50 can be positioned at a position that is 0.2 mm or less (preferably 0.1 mm or less) lower than the reference surface 21c of the wafer mounting surface 21. Even so, the height of the space between the lower surface of the wafer W and the upper surface 50a of the porous plug 50 can be suppressed to a relatively low level. Therefore, arc discharge can be prevented in this space.

[0057] In the above embodiment, the lower surface 50b of the porous plug 50 is located inside the through hole 42 of the metal bonding layer 40 (that is, below the upper surface 40a of the metal bonding layer 40), but it is not particularly limited to this. For example, it can be as follows: Figure 8 The lower surface 50b of the porous plug 50 is positioned inside the gas hole 34 of the cooling plate 30 (i.e., lower than the upper surface of the cooling plate 30). Even so, the same effect as in the above embodiment is obtained. This configuration is effective when a resin adhesive layer is used instead of the metal bonding layer 40. This is because: when the lower surface 50b of the porous plug 50 is configured to be located inside the through hole of the resin adhesive layer, although a potential difference is generated between the lower surface 50b of the porous plug 50 and the cooling plate 30, if like Figure 8 If it is constructed that way, the potential difference will disappear. Figure 8 In the case where a resin adhesive layer is used instead of a metal bonding layer 40, the cooling plate 30 is equivalent to the conductive substrate of the present invention, and the gas hole 34 is equivalent to the second hole.

[0058] In the above embodiment, although the porous plug 50 is inserted into the bottom hole 64 provided on the upper part of the insulating tube 60 for bonding and fixing, it is not particularly limited to this. For example, it can be as follows: Figure 9 As shown, a bottom hole 252 is provided on the lower surface of the porous plug 250. An insulating tube 260 with a diameter smaller than that of the porous plug 250 is inserted into the bottom hole 252 and bonded to it. In this case, the integrated component of the porous plug 250 and the insulating tube 260 is bonded to it by an adhesive layer 270 provided between the outer peripheral surface of the porous plug 250 and the inner peripheral surfaces of each hole (the first hole 224 of the ceramic plate 220, the through hole 242 of the metal bonding layer 240, and the gas hole 234 of the cooling plate 230). An adhesive layer 270 is also formed on the lower surface of the porous plug 250 (except for the bottom hole). It can be used... Figure 10 Stepped porous plug 350 to replace Figure 9 250 cylindrical porous plugs.

[0059] In the above-described embodiments, the electrostatic electrode is exemplified as the electrode 22 built in the ceramic plate 20, but is not particularly limited thereto. For example, a heater electrode (resistance heating element) can be built in the ceramic plate 20 instead of the electrode 22, or a heater electrode (resistance heating element) can be built in the ceramic plate 20 in addition to the electrode 22.

Claims

1. A component for a semiconductor manufacturing apparatus, wherein, The semiconductor manufacturing apparatus component includes: a ceramic plate having a wafer placement surface on an upper surface; a conductive substrate provided on a lower surface of the ceramic plate; a first hole penetrating the ceramic plate in a vertical direction; a second hole penetrating the conductive substrate in the vertical direction and communicating with the first hole; a porous plug having an upper surface exposed at an upper opening of the first hole and a lower surface below the upper surface of the conductive substrate; an insulating tube having an upper surface at a position lower than the wafer placement surface and a lower surface at a position lower than the lower surface of the porous plug; and an integrated component obtained by integrating the porous plug and the insulating tube, an outer peripheral surface of which is fixed to the first hole and the second hole by an adhesive layer from the upper surface of the first hole to the inside of the second hole, the insulating tube has a bottomed hole at a tube upper portion, the porous plug is held in a state of being inserted into the bottomed hole, and a gap is present between a bottom surface of the bottomed hole and the lower surface of the porous plug.

2. The semiconductor manufacturing apparatus component according to claim 1, wherein the width of the adhesive layer is wider outside a radius than inside the first hole.

3. The semiconductor manufacturing apparatus component according to claim 1 or 2, wherein an inner peripheral surface of the second hole has an enlarged diameter portion in which a diameter increases from below to above, and the adhesive layer is present between the enlarged diameter portion and the insulating tube.

4. The semiconductor manufacturing apparatus component according to claim 1 or 2, wherein the wafer placement surface has a plurality of small protrusions that support a wafer, and the upper surface of the porous plug is at a position lower than an upper surface of the small protrusions.

5. The semiconductor manufacturing apparatus component according to claim 4, wherein the upper surface of the porous plug is at the same height as a reference surface of the wafer placement surface on which the small protrusions are not provided, or at a position within a range of 0.2 mm or less below the reference surface. ​

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