Method for manufacturing high-quality GaN HEMT power semiconductor epitaxial wafers
By introducing a three-dimensional nitride structure region into the GaN HEMT power semiconductor epitaxial wafer, the dislocation problem caused by the difference between lattice constant and thermal expansion coefficient is solved, achieving a high-quality epitaxial layer and excellent heat dissipation performance, thereby improving device reliability and lifespan.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WAVELORD CO LTD
- Filing Date
- 2025-12-19
- Publication Date
- 2026-06-23
AI Technical Summary
In the current technology for manufacturing GaN HEMT power semiconductor epitaxial wafers, the difference between the lattice constant and the coefficient of thermal expansion leads to a large number of through dislocations, which affects electron mobility and leakage current. In addition, conventional doping processes reduce crystal quality and heat dissipation performance.
Introducing three-dimensional nitride structure (3DNS) regions on the growth substrate, by forming nanoscale dot structures at key locations, blocks the propagation of crystal defects and improves crystal quality and heat dissipation efficiency without increasing thickness.
It effectively blocks dislocation propagation, improves electron mobility and leakage current, enhances device reliability and heat dissipation performance, reduces thermal resistance, and ensures stable operation under high temperature and high pressure environments.
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Abstract
Description
Technical Field
[0001] This invention relates to III-nitride-based epitaxial growth and wafer fabrication techniques for power semiconductor devices. More specifically, this invention relates to a method for fabricating high-quality GaN HEMT power semiconductor epitaxial wafers, which enables the control of crystal defects by introducing a three-dimensional nitride structure (3DNS) between the growth substrate and the channel region, thereby improving device reliability while reducing the overall thickness. Background Technology
[0002] Recently, gallium nitride (GaN)-based high electron mobility transistor (HEMT) epitaxial wafers have been widely used as power amplifiers in radio frequency (RF) communication modules, as well as core materials for high-speed switching converters and inverters. Typically, these GaN HEMT devices are fabricated by stacking nitride layers on silicon (Si) or silicon carbide (SiC) growth substrates with excellent thermal conductivity.
[0003] However, when GaN is grown on a silicon substrate, significant stress occurs during film formation due to the large differences in lattice constants (approximately 17%) and coefficients of thermal expansion (approximately 56%) between the two materials. This results in a large number of through-dislocations propagating along the growth direction. These crystal defects are transported to the upper channel region, leading to reduced electron mobility and increased leakage current in the device.
[0004] Conventionally, to suppress vertical leakage current, a high-resistivity layer is formed by artificially doping GaN buffer layers with impurities such as carbon (C) or iron (Fe). However, this doping process has the side effect of further degrading crystal quality, and the buffer layer must be grown to a thickness of several micrometers to ensure sufficient insulation performance. As the buffer layer becomes thicker, the path for heat generated during device operation to dissipate to the substrate becomes longer, thereby increasing thermal resistance, which directly leads to shortened device lifetime and reduced reliability.
[0005] Furthermore, the AlN nucleation layer used to prevent reflow etching caused by the reaction between silicon and gallium is itself insufficient to completely block upward propagation of dislocations. Therefore, there is an urgent need for a new level of dislocation control technology that can maximize heat dissipation characteristics through ultra-thin device structures without compromising crystal quality. Summary of the Invention
[0006] [Technical Issues]
[0007] The purpose of this invention is to effectively block the upward propagation of crystal defects generated from the growth substrate in order to form a high-quality epitaxial layer.
[0008] Another objective is to provide a method for manufacturing a high-reliability GaN HEMT power semiconductor wafer that can operate stably even in high-temperature and high-pressure environments by significantly reducing the overall thickness of the device to improve heat dissipation efficiency.
[0009] [Problem Solution]
[0010] To address the aforementioned problems, an embodiment of the present invention provides a method for manufacturing a high-quality GaN HEMT power semiconductor epitaxial wafer, comprising: forming a nucleation region on a growth substrate; and forming a three-dimensional nitride structure region (3DNS region), a stress relief region, a buffer zone, a channel region, and a barrier region on the nucleation region, wherein the 3DNS region is formed at one or more of the following locations: between the nucleation region and the stress relief region, between the various regions within the stress relief region, between the stress relief region and the buffer zone, between the buffer zone and the channel region, and between the barrier region and the pGaN region formed thereon, and wherein the 3DNS region is formed of a nitride material with a band gap smaller than that of the lower region.
[0011] In the method for manufacturing a high-quality GaN HEMT power semiconductor epitaxial wafer according to an embodiment of the present invention, the 3DNS region is formed of at least one material selected from the group consisting of GaN, AlGaN, InN, AlN, AlInN, InGaN, AlGaInN, MgN, and SiN.
[0012] In the method of the embodiments of the present invention, the thickness of the 3DNS region is 2 nm to 10 nm.
[0013] In the method of an embodiment of the present invention, the 3DNS region formed between the nucleation region and the stress relief region is formed of GaN, InGaN or AlGaN having a lower Al composition than the stress relief region, thereby blocking the propagation of crystal defects.
[0014] In the method of an embodiment of the present invention, the 3DNS region formed between the stress relief zone and the buffer zone is formed of GaN, MgN or SiN, thereby reorganizing the crystallinity and blocking vertical leakage current before the growth buffer zone.
[0015] In the method of an embodiment of the present invention, the 3DNS region formed between the buffer and the channel region is formed of InGaN or AlGaInN, thereby blocking the diffusion of dopants from the buffer.
[0016] In the method of an embodiment of the present invention, the stress relief region is characterized by having multiple AlGaN regions stacked together, or including an Al(Ga)N / AlGaN superlattice structure.
[0017] In the method of an embodiment of the present invention, before forming the channel region, the method further includes forming a back barrier region of an AlGaN or 2H-Al(Ga)N / 4H-SiC(N) superlattice structure.
[0018] In the method of an embodiment of the present invention, the formation of the 3DNS region includes the steps of: pre-flowing a group III element source to form a nanoscale precursor cluster without supplying a nitrogen (N) source; and supplying a nitrogen source to the precursor cluster to form a 3DNS region in which the precursor cluster recrystallizes into a single crystal.
[0019] In the method of an embodiment of the present invention, the 3DNS region has a composition ratio that varies along the lateral direction, and the variation period of the composition ratio is less than 100 nm.
[0020] [Beneficial Effects of the Invention]
[0021] According to the present invention, the 3DNS region effectively bends or annihilates penetrating dislocations generated from the bottom, thereby realizing the upper channel region in a substantially “dislocation-free” state, thereby significantly improving the electrical characteristics of the device.
[0022] Furthermore, the interfacial stress caused by the difference in lattice constant and thermal expansion coefficient between the nucleation region and the channel region was controlled, thereby suppressing wafer warping or crack formation.
[0023] Furthermore, due to improved crystal quality, conventional thick, high-resistivity doped buffer layers can be minimized or eliminated, allowing for ultra-thinning of the total epitaxial structure to below 700 nm. Additionally, by thinning the device structure, heat generated during device operation is directly transferred to the substrate, maximizing heat dissipation and improving device lifetime and reliability.
[0024] Furthermore, the yield and quality of the manufacturing process can be ensured by promoting the growth of high-quality active regions while preventing remelting etching. Attached Figure Description
[0025] Figure 1 This is a structural diagram of an epitaxial wafer stack according to the first embodiment of the present invention.
[0026] Figures 2 to 5 yes Figure 1 Examples of variations.
[0027] Figure 6 This is a TEM photograph showing the state in which the propagation of penetrating faults is blocked when a 3DNS zone is introduced.
[0028] Figure 7 This is a magnified TEM image showing the interface with nanoscale 3DNS regions formed. Detailed Implementation
[0029] In the following, embodiments of the high-quality GaN HEMT power semiconductor epitaxial wafer of the present invention and its manufacturing method by introducing a three-dimensional nitride structure will be described in detail with reference to the accompanying drawings.
[0030] The core of this invention is to introduce a 3DNS region 190, which is a nanoscale three-dimensional structure, at a key location inside the epitaxial layer, so as to simultaneously ensure the crystal quality and heat dissipation characteristics of the power semiconductor.
[0031] The overall process flow of this invention includes preparing a growth substrate and sequentially stacking AlN nucleation regions 120, stress relief regions 130, buffer zones 140, channel regions 160, and barrier regions 170 thereon, and includes forming 3DNS regions 190 through a special two-step growth method. The 3DNS regions 190 act as a physical barrier, which fundamentally blocks the vertical propagation of dislocations by intentionally accumulating precursor clusters at the defect tips of the lower layer, and also acts as a functional interface to reduce interlayer stress.
[0032] refer to Figure 1 The epitaxial wafer of this embodiment includes an AlN nucleation region 120, a stress relief region 130, a buffer zone 140, a channel region 160, and a blocking region 170 sequentially stacked on a growth substrate 110.
[0033] The growth substrate 110 is a substrate used for epitaxial growth and is made of silicon (Si). In particular, due to the similarity of the atomic arrangement to hexagonal nitride semiconductors, the crystal plane orientation of the silicon substrate 110 is preferably (111) plane. Furthermore, a high-resistivity or p-type silicon substrate is used to suppress vertical leakage current through the substrate. Alternatively, a growth substrate 110 made of silicon carbide (SiC) may also be used.
[0034] Nucleation region 120 is formed on growth substrate 110. It is mainly composed of aluminum nitride (AlN) and serves as a diffusion barrier layer to improve wetting between the silicon substrate and the overlying nitride layer and to prevent the substrate from being etched back during high-temperature growth.
[0035] Stress relief region 130 is formed on nucleation region 120. It is a layer used to control tensile stress caused by the difference in thermal expansion coefficients between silicon and GaN, and may include a stack of multiple AlGaN regions or an Al(Ga)N / AlGaN superlattice structure.
[0036] A buffer 140 is formed on the stress relief region 130. The buffer 140 is a layer that ensures high resistance to achieve breakdown voltage characteristics and enhances insulation properties by intentionally doping GaN with impurities such as carbon (C) or iron (Fe).
[0037] The back barrier region 150 may be disposed below the channel region 160. In particular, as a variant example of the present invention, the back barrier region 150 may have a superlattice structure in which 2H-Al(Ga)N material layers and 4H-SiC(N) material layers are stacked alternately, which maximizes the electron confinement effect while suppressing dislocation generation using lattice matching.
[0038] The channel region 160 is made of high-purity GaN and serves as an electron transport path, while the barrier region 170 thereon is made of AlGaN or the like to form a high-concentration two-dimensional electron gas (2DEG) through interfacial polarization. The pGaN layer 180 can be formed on the topmost layer to keep the device normally off.
[0039] In this embodiment, a 3DNS region 190 is introduced above the nucleation region 120 as a region where the composition ratio varies along the lateral direction. Discontinuous and non-uniform nanoscale point structures 191 are formed in the 3DNS region 190 to filter through dislocations propagating from the bottom. Its technical significance lies in: innovatively improving the crystal quality of the upper channel region by preferentially forming at defect points in the lower layer to block or bend the propagation path of dislocations.
[0040] The 3DNS region 190 is formed of a nitride material having a smaller band gap than the nitride layer located in the nucleation region 120, and it is the lower part of the corresponding region. The 3DNS region 190 is selected from GaN, AlGaN, InN, AlN, AlInN, InGaN, AlGaInN, MgN, and SiN. Specifically, in this embodiment, the 3DNS region 190 may be Al x In y Ga 1-x-y The active layer is composed of N and has a structural feature where the composition ratio of x and y varies along the lateral direction. When the underlying layer is AlN or AlGaN, 3DNS is formed from GaN or InGaN-like materials to form energy levels. This physical coupling relationship of the band gap provides the driving force for suppressing the growth of dislocation lines and inducing annihilation, enabling the growth of high-quality active layers.
[0041] Here, the stress dispersion effect can be further enhanced by nitriding the surface of the nucleation region before the formation of the 3DNS region, or by modifying the 3DNS itself with a material having a large lattice constant (e.g., AlInN). In this case, the 3DNS region 190 has a compositional variation period of less than 100 nm in the lateral direction, which causes high-density local stress modulation, preventing through-dislocations from propagating in a straight line and causing them to be annihilated. Due to this high-density defect control effect, the thickness of the buffer zone 140 can be reduced, thereby further improving heat dissipation performance.
[0042] The thickness of the 3DNS region 190 of the present invention is formed in the range of 2 nm or more and 10 nm or less, and preferably ensures a thickness of 3 nm or more to maximize dislocation blocking function. Physically, if it is less than 2 nm, the dislocation blocking capability is reduced due to the lack of structural continuity, and if it exceeds 10 nm, the total epitaxial thickness increases, thereby increasing the vertical thermal resistance. Therefore, by keeping the thickness below 10 nm, defects are effectively blocked while shortening the heat transfer path to improve heat dissipation.
[0043] In the 3DNS region 190, each nanoscale dot structure 191 acts as an independent filter, and by blocking penetrating dislocations propagating upwards from the growth substrate, it fundamentally solves the reliability degradation problem that may occur in the final device. At the same time, based on ensuring crystal quality through 3DNS, the present invention can ultrathin the entire epitaxial structure to below 700 nm, preferably below 500 nm.
[0044] Specifically, the buffer 140 maintains a high-resistivity state by doping with carbon (C) or iron (Fe) to ensure the device's breakdown voltage. In this invention, the dislocation density is significantly reduced by introducing a 3DNS region 190 before, after, or during the buffer formation step. As a result, the crystallinity degradation caused by doping can be offset, and sufficient leakage current blocking characteristics can be ensured using a buffer that is much thinner than a conventional buffer, thereby enabling thinning of the entire epitaxial layer and achieving high heat dissipation capabilities.
[0045] Next, the process of forming the 3DNS region 190 will be described. The process of forming the three-dimensional shape structure involves the following steps: pre-flowing only a group III element source in the absence of a nitrogen (N) source to form nanoscale precursor clusters, followed by supplying a nitrogen source for recrystallization into single crystals. After forming the nucleation region 120 on the growth substrate 110, pre-flowing only a group III element (Al, Ga, In) source in the absence of ammonia (NH3) gas to form precursor clusters 131a. Subsequently, ammonia gas is supplied to recrystallize these clusters into single crystals, thereby completing the final 3DNS region 190.
[0046] In this invention, the formation of the 3DNS region 190 utilizes a pyrolysis reaction of an organometallic source. Thermodynamically, Group III elements preferentially aggregate at high-energy, unstable surface points, i.e., around surfaces where penetrating dislocations exist, thereby forming a three-dimensional point-shaped cluster 191. Through a subsequent recrystallization process, this has the technical effect of physically blocking the growth path of dislocations or altering their properties, and fundamentally inhibiting dislocation propagation to the top.
[0047] In this invention, the formation of the 3DNS region 190 can be repeated two or more times. By repeating this process, the thickness of the 3DNS region can be increased, and the compositional variation cycle in the lateral direction can be precisely controlled, thereby further enhancing dislocation filtering and stress relaxation functions. This repeatable process allows for arbitrary adjustments based on the design conditions of the channel and barrier regions to be grown thereon, thereby ensuring optimal crystallinity.
[0048] Simultaneously, in this invention, process parameters at each step are precisely controlled to induce three-dimensional growth. The 3DNS region 190 is formed at temperatures ranging from 600 to 1300°C and pressures ranging from 30 to 400 Torr, with the V / III ratio maintained in the range of 300 to 4000. An N2 / H2 mixture is used in the growth atmosphere to optimize the crystallinity of the recrystallized 3DNS, which forms the basis for ensuring high electron mobility in a 100% H2 atmosphere during subsequent channel region growth.
[0049] Figure 6 and Figure 7 The TEM images visually demonstrate the effectiveness of the 3DNS invention. (Reference) Figure 6 The TEM images show that the 3DNS regions inserted into the AlN nucleation region effectively block the penetrating dislocations in the lower region. As a result, the upper region maintains a high-purity crystal state with almost no defects (no penetrating dislocations). Figure 7 This is a further magnified photograph of the interface, clearly showing the nanoscale 3DNS layer formed between the AlN layer and the upper layer. This 3DNS region maintains an optimal thickness of 2 nm to 10 nm and has a structure in which the composition ratio varies in the lateral direction, thereby maximizing the crystal quality of the upper active layer.
[0050] Figure 2 The diagram illustrates a structure in which 3DNS regions are inserted between regions within a stress-relieving region 130. In this embodiment, between AlGaN regions with different Al compositions, the 3DNS region 190 is preferably composed of GaN or AlGaN with a lower Al content than the underlying layer. This mitigates abrupt changes in the interlayer lattice constant, thus addressing thermomechanical stress and suppressing crack initiation. Here, the stress relaxation effect can be maximized by arranging 3DNS at each step interface of the stepped hierarchical structure (where the Al composition gradually decreases towards the top).
[0051] Figure 3A structure in which a 3DNS region is formed between a stress-relief region 130 and a buffer zone 140 is shown. In this embodiment, the 3DNS region 190 is preferably composed of GaN, MgN, or SiN. This immediately reorganizes the crystallinity before the high-resistivity doping begins in the buffer zone and enhances the energy barrier with MgN or SiN, thereby maximizing the vertical leakage current blocking performance during high-voltage drive. Here, to enhance the leakage current blocking performance, a composite 3DNS structure combining a very thin AlN layer and a MgN or SiN 3DNS region can be applied, or the insulating properties can be enhanced by locally pre-flowing insulating dopants (e.g., high concentrations of Fe) during 3DNS formation.
[0052] Figure 4 This embodiment involves inserting a 3DNS region between the buffer zone 140 and the channel region 160. In this embodiment, the 3DNS region 190 is preferably composed of InGaN or AlGaInN. Therefore, it acts as a diffusion barrier layer to physically block impurities (e.g., carbon (C) or iron (Fe)) doped in the lower buffer zone from diffusing into the active channel. This improves the quality of the channel interface, significantly enhancing the electron mobility characteristics of the 2DEG. Here, the electrical purity of the lower part of the channel can be maximized by fluctuating the In composition of the InGaN 3DNS region in the horizontal direction, or by alternately stacking 2H-Al(Ga)N / 4H-SiC(N) superlattice structures and 3DNS.
[0053] Figure 5 A structure is shown in which a 3DNS region is arranged between the barrier region 170 and the pGaN region 180. In this embodiment, preferably, a nitride with a high GaN or InN content is used for the 3DNS region 190. This provides a physical environment for reducing crystal defects in the upper pGaN and increasing hole concentration. Furthermore, it is important for ensuring the thermal stability of the device and optimizing heat dissipation performance by rapidly dispersing heat generated from the lower part of the gate horizontally.
Claims
1. A method for manufacturing high-quality GaN HEMT power semiconductor epitaxial wafers, the method comprising: Nucleation regions are formed on the growth substrate; And on the nucleation region, a three-dimensional nitride structure region (3DNS region), stress relief region, buffer zone, channel region and barrier region are formed. The 3DNS region is formed at one or more locations selected from the group consisting of: between the nucleation region and the stress relief region, between the various regions within the stress relief region, between the stress relief region and the buffer zone, between the buffer zone and the channel region, and between the barrier region and the pGaN region formed thereon. The 3DNS region is formed of a nitride material with a band gap smaller than that of the lower region.
2. The method as described in claim 1, wherein, The 3DNS region is formed of at least one material selected from the group consisting of GaN, AlGaN, InN, AlN, AlInN, InGaN, AlGaInN, MgN, and SiN.
3. The method as described in claim 1, wherein, The thickness of the 3DNS region is 2 nm to 10 nm.
4. The method of claim 1, wherein, The 3DNS region formed between the nucleation region and the stress relief region is formed of GaN, InGaN, or AlGaN with a lower Al composition than the stress relief region, in order to block the propagation of crystal defects.
5. The method of claim 1, wherein, The 3DNS region formed between the stress relief region and the buffer zone is made of GaN, MgN or SiN to reorganize crystallinity and block vertical leakage current before the buffer zone is grown.
6. The method of claim 1, wherein, The 3DNS region formed between the buffer and the channel region is formed of InGaN or AlGaInN to block the diffusion of dopants from the buffer.
7. The method of claim 1, wherein, The stress relief region comprises a stack of multiple AlGaN regions or an Al(Ga)N / AlGaN superlattice structure.
8. The method of claim 1, further comprising: Before forming the channel region, a back barrier region of AlGaN or 2H-Al(Ga)N / 4H-SiC(N) superlattice structure is formed.
9. The method of claim 1, wherein, The formation of the 3DNS zone includes: Pre-flowing a group III element source without supplying a nitrogen (N) source to form nanoscale precursor clusters; and A nitrogen source is supplied to the precursor cluster to form the 3DNS region in which the precursor cluster recrystallizes into a single crystal.
10. The method of claim 9, wherein, The 3DNS region has a composition ratio that varies along the lateral direction, and the variation period of the composition ratio is less than 100 nm.