A p-type silicon carbide wafer and a method of processing the same

Abstract

The application provides a processing method of a P-type silicon carbide wafer, and the processing method comprises the following steps: (1) cutting a P-type silicon carbide single crystal to obtain a plurality of wafers; (2) respectively grinding and polishing each wafer to obtain the P-type silicon carbide wafer; wherein the polishing comprises first stage polishing and second stage polishing, the polishing liquid used in the first stage polishing is an polishing liquid containing aluminum oxide, and the polishing liquid used in the second stage polishing is an polishing liquid containing silicon oxide. The P-type silicon carbide wafer is processed by using the processing method, and processing defects are not prone to occurring, and the P-type silicon carbide wafer with small surface roughness can be obtained.

Description

Technical Field

[0001] The invention relates to the field of silicon carbide wafer processing technology, and in particular to a P-type silicon carbide wafer and its processing method. Background Technology

[0002] n-channel SiC insulated-gate bipolar transistors (SBBTs) offer significant performance advantages and promising applications as high-voltage switches. The fabrication of these devices requires highly doped, low-resistivity p-type silicon carbide substrates (i.e., p-type silicon carbide wafers). Generally, the surface quality of the substrate has a direct and decisive impact on the final performance of the device; therefore, obtaining smooth, defect-free silicon carbide wafers is crucial to fully realizing the superior performance of silicon carbide materials. However, due to the strong chemical bonds between silicon and carbon atoms, silicon carbide materials possess very high mechanical hardness and chemical stability. Consequently, the material removal rate during silicon carbide wafer processing is relatively low, and various processing defects are highly likely to occur.

[0003] In existing technologies, the processing techniques for semi-insulating silicon carbide wafers and N-type silicon carbide wafers have become relatively stable. However, the processing technology for P-type silicon carbide wafers is still in the exploratory stage. During processing, P-type silicon carbide wafers are prone to defects, which severely limits their application. Therefore, in order to fill the market gap for P-type silicon carbide wafers, the technical difficulties in processing P-type silicon carbide wafers urgently need to be overcome. Summary of the Invention

[0004] This invention provides a method for processing P-type silicon carbide wafers. Using this method to process P-type silicon carbide wafers reduces the likelihood of processing defects and yields P-type silicon carbide wafers with low surface roughness.

[0005] In a first aspect, a method for processing a P-type silicon carbide wafer includes the following steps:

[0006] (1) Cut the P-type silicon carbide single crystal to obtain multiple wafers;

[0007] (2) Each wafer is ground and polished separately to obtain the P-type silicon carbide wafer; wherein the polishing includes a first stage polishing and a second stage polishing, the polishing liquid used in the first stage polishing is a polishing liquid containing aluminum oxide, and the polishing liquid used in the second stage polishing is a polishing liquid containing silicon oxide.

[0008] Preferably, in step (1), the cutting fluid used for cutting is diamond cutting fluid; wherein the diamond particle size in the diamond cutting fluid is 4 to 6 μm.

[0009] Preferably, in step (2), each wafer is polished sequentially using a first polishing slurry and a second polishing slurry; both the first polishing slurry and the second polishing slurry are diamond polishing slurries, the diamond particle size in the first polishing slurry is 2 to 4 μm, and the diamond particle size in the second polishing slurry is 0 to 1 μm.

[0010] Preferably, in step (2), the surface roughness of the wafer after grinding is less than 1 nm, the thickness difference within the same wafer is less than 3 μm, and the thickness difference between different wafers is less than 5 μm.

[0011] Preferably, in step (2), the polishing liquid used in the first stage of polishing includes alumina abrasive particles, an oxidant, and an acid-base regulator; the polishing liquid used in the second stage of polishing includes silicon oxide abrasive particles, an oxidant, and an acid-base regulator.

[0012] Preferably, the alumina abrasive particles have a particle size of 50-80 nm, and the silicon oxide abrasive particles have a particle size of 20-40 nm; the oxidant is at least one of potassium permanganate, sodium hypochlorite, or hydrogen peroxide; and the acid-base regulator is at least one of nitric acid, hydrochloric acid, sodium hydroxide, or potassium hydroxide.

[0013] Preferably, by mass percentage, the polishing liquid used in the first stage of polishing contains 1-5% alumina abrasive particles, 0.5-5% oxidant, and 0.3-1% acid-base adjuster.

[0014] In the polishing slurry used in the second stage of polishing, the amount of silicon oxide abrasive particles is 5-10%, the amount of oxidant is 1-6%, and the amount of acid-base adjuster is 0.3-1%.

[0015] Preferably, in step (1), after cutting the P-type silicon carbide single crystal, the step further includes selecting the cut wafers;

[0016] The selection criteria are: the thickness difference of each wafer is less than 15μm, the warpage is less than 30μm, and the thickness difference between different wafers is less than 5μm.

[0017] In a second aspect, the present invention provides a P-type silicon carbide wafer, which is processed using any of the processing methods described in the first aspect above.

[0018] Preferably, the surface roughness of the P-type silicon carbide wafer is less than 0.2 nm.

[0019] Compared with the prior art, the present invention has at least the following beneficial effects:

[0020] (1) In this invention, the polished wafer is polished in the first stage and the second stage in sequence. First, polishing is performed with polishing liquid containing alumina, and then polishing is performed with polishing liquid containing silicon oxide. In this way, a P-type silicon carbide wafer with a smooth surface and low roughness can be obtained, thereby effectively improving the problem that P-type silicon carbide wafers are prone to defects during processing.

[0021] (2) The present invention can improve the processing quality of P-type silicon carbide wafers. The surface shape of the P-type silicon carbide wafers obtained by processing using the processing method of the present invention is inspected. The TTV (total thickness variation) is 2.526 μm, the LTV (local thickness variation) is 0.85 μm, and the Ra (surface roughness) is less than 0.2 nm. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a surface morphology image of a P-type silicon carbide wafer obtained by processing using the processing method in Embodiment 1 of the present invention;

[0024] Figure 2 This is a roughness test result diagram of a P-type silicon carbide wafer obtained after processing using the processing method in Embodiment 1 of the present invention;

[0025] Figure 3 This is a diagram showing the surface profile inspection results of a P-type silicon carbide wafer obtained by processing using the processing method described in Embodiment 1 of the present invention.

[0026] Figure 4 This is a surface morphology image of a P-type silicon carbide wafer obtained after processing using the processing method of Embodiment 6 of the present invention;

[0027] Figure 5 This is a surface morphology image of an N-type silicon carbide wafer obtained by processing using the processing method of Comparative Example 1 of the present invention.

[0028] Figure 6 The roughness test results of the N-type silicon carbide wafer obtained by processing using the processing method of Comparative Example 1 of this invention are shown in the figure.

[0029] Figure 7 This is a surface morphology image of a P-type silicon carbide wafer obtained by processing using the processing method of Comparative Example 1 of the present invention.

[0030] Figure 8The image shows the roughness test results of the P-type silicon carbide wafer obtained after processing using the processing method of Comparative Example 1 of this invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0032] Common silicon carbide wafers include semi-insulating silicon carbide wafers, P-type silicon carbide wafers, and N-type silicon carbide wafers. In related technologies, some silicon carbide wafer processing methods have poor universality and are generally only applicable to semi-insulating silicon carbide wafers and N-type silicon carbide wafers. Due to the different types of doped particles, N-type silicon carbide wafers and P-type silicon carbide wafers also have different intrinsic properties. For example, there are certain differences in properties such as hardness, density, and oxidation rate. Therefore, when using the original processing methods to process P-type silicon carbide wafers, P-type silicon carbide wafers are very prone to wavy processing defects, and their surface roughness is large, which cannot meet the market use standards.

[0033] To address the aforementioned problems, this invention provides a method for processing P-type silicon carbide wafers, comprising the following steps:

[0034] (1) Cut the P-type silicon carbide single crystal to obtain multiple wafers;

[0035] (2) Each wafer is ground and polished separately to obtain the P-type silicon carbide wafer; wherein the polishing includes a first stage polishing and a second stage polishing, and the polishing liquid used in the first stage polishing is different from the polishing liquid used in the second stage polishing.

[0036] In this embodiment, by sequentially performing a first-stage polishing and a second-stage polishing on the ground wafer, and by selecting and controlling the type and content of the polishing liquid used in the first-stage polishing and the second-stage polishing, a P-type silicon carbide wafer with a smooth surface and low roughness can be obtained, thereby effectively improving the problem of defects easily generated in the processing of P-type silicon carbide wafers.

[0037] According to some preferred embodiments, in step (1), the cutting fluid used for cutting is diamond cutting fluid; wherein, the diamond particle size in the diamond cutting fluid is 4 to 6 μm (for example, it can be 4 μm, 5 μm or 6 μm).

[0038] In this embodiment, the P-type silicon carbide single crystal is first cut using a 0.16mm steel wire and a diamond cutting fluid with a certain particle size. After cutting, multiple wafers are obtained. Wafers with a thickness variation of less than 15μm, a warpage of less than 30μm, and a thickness difference of less than 5μm between wafers are selected for grinding and polishing. By using the diamond cutting fluid with the above-mentioned particle size to cut the P-type silicon carbide single crystal, this embodiment can not only ensure the flatness of the cut wafers, but also ensure good cutting efficiency.

[0039] According to some preferred embodiments, in step (2), each wafer is polished sequentially using a first polishing slurry and a second polishing slurry; both the first polishing slurry and the second polishing slurry are diamond polishing slurries, the particle size of the first polishing slurry is 2 to 4 μm (for example, it can be 2 μm, 3 μm or 4 μm), and the particle size of the second polishing slurry is 0 to 1 μm (for example, it can be 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm or 1 μm).

[0040] In this embodiment, when grinding the wafer, a first grinding fluid with a particle size of 2 to 4 μm is first used for grinding, which can quickly remove the damaged layer generated after wafer cutting and accelerate the grinding efficiency of the wafer; then a second grinding fluid with a particle size of 0 to 1 μm is used for further grinding, which can ensure that the wafer surface has good flatness.

[0041] According to some preferred embodiments, in step (2), the surface roughness of the polished wafer is less than 1 nm, the thickness difference within the same wafer is less than 3 μm, and the thickness difference between different wafers is less than 5 μm.

[0042] In this implementation, the main process is to remove the damaged layer on the wafer and gradually reduce the surface roughness of the wafer by grinding, in order to prepare for subsequent polishing. During grinding, the above-mentioned particle size grinding fluid is used in conjunction with the grinding machine to grind and thin the wafer. When the surface roughness of the wafer is less than 1nm, the thickness difference within a single wafer is less than 3μm, and the thickness difference between different wafers is less than 5μm, grinding can be stopped.

[0043] According to some preferred embodiments, in step (2), the polishing liquid used in the first stage polishing includes alumina abrasive particles, an oxidant and an acid-base regulator; the polishing liquid used in the second stage polishing includes silicon oxide abrasive particles, an oxidant and an acid-base regulator.

[0044] According to some preferred embodiments, the alumina abrasive particles have a particle size of 50-80 nm (e.g., 50 nm, 60 nm, 70 nm, or 80 nm), and the silicon oxide abrasive particles have a particle size of 20-40 nm (e.g., 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm); the oxidant is at least one of potassium permanganate, sodium hypochlorite, or hydrogen peroxide; and the acid-base regulator is at least one of nitric acid, hydrochloric acid, sodium hydroxide, or potassium hydroxide.

[0045] In this embodiment, a two-stage polishing process is used to polish the wafer. The type of polishing slurry used in the first stage is different from that used in the second stage. First, a polishing slurry containing alumina abrasive particles is used in conjunction with a polishing machine to polish both sides (silicon side and carbon side) of the wafer separately. This can accelerate the polishing efficiency of the wafer and ensure that the silicon side and carbon side of the wafer have good smoothness. In order to ensure that the silicon side of the wafer has good application performance, in the second stage of polishing, a polishing slurry containing silicon oxide abrasive particles is used in conjunction with polishing gold to further polish the silicon side of the wafer, thereby further reducing the roughness of the silicon side and ensuring its good epitaxial growth performance.

[0046] It should be noted that the nitric acid used in this invention is dilute nitric acid with a concentration of 6 mol / L.

[0047] According to some preferred embodiments, the polishing liquid used in the first stage of polishing contains, by mass percentage, 1-5% alumina abrasive particles (e.g., 1%, 2%, 3%, 4%, or 5%), 0.5-5% oxidant (e.g., 0.5%, 1%, 2%, 3%, or 5%), and 0.3-1% acid-base adjuster (e.g., 0.3%, 0.5%, 0.8%, or 1%).

[0048] In the polishing slurry used in the second stage of polishing, the amount of silicon oxide abrasive particles is 5-10% (e.g., 5%, 6%, 7%, 8%, 9% or 10%), the amount of oxidant is 1-6% (e.g., 1%, 2%, 3%, 4%, 5% or 6%), and the amount of acid-base adjuster is 0.3-1% (e.g., 0.3%, 0.5%, 0.8% or 1%).

[0049] In this embodiment, when using a polishing slurry containing alumina in conjunction with a polishing machine to perform the first stage polishing of the silicon and carbon surfaces of the wafer, the preferred speed of the lower platen of the polishing machine is 75–85 rpm / min, the preferred speed of the upper platen is 85–95 rpm / min, and the preferred pressure is 0.35–0.45 kg / cm². 2The polishing time for each side is 1.5–2.5 hours. When using a polishing slurry containing silicon oxide in conjunction with a polishing machine to perform the second stage polishing of the silicon surface of the wafer, the preferred lower platen speed of the polishing machine is 55–65 rpm / min, the preferred upper platen speed is 65–75 rpm / min, and the preferred pressure is 0.25–0.35 kg / cm². 2 The polishing time is 2.5 to 3.5 hours.

[0050] In this embodiment, the inventors considered the differences between N-type and P-type silicon carbide wafers from a mechanistic perspective. The main difference between N-type and P-type silicon carbide wafers lies in the different doped particles, resulting in significant differences in properties such as hardness, density, and oxidation rate. Therefore, by using different types of polishing slurries in two stages to polish the wafers, and further comprehensively controlling the types and contents of each component in the polishing slurry and the various process parameters in each stage, the surface roughness of the silicon surface of the polished wafer is reduced, resulting in better smoothness and effectively avoiding the problem of surface defects easily generated during the processing of P-type silicon carbide wafers. The abrasive particles (such as alumina or silicon oxide particles) in the polishing slurry mainly serve to reduce the surface roughness of the wafer. The oxidant can cooperate with the abrasive particles to accelerate the polishing efficiency of the wafer. If the oxidant content is too low, it is not conducive to ensuring good polishing efficiency; if the oxidant content is too high, it will easily cause wavy defects on the wafer surface. Simultaneously, controlling the pH value of the polishing slurry within a certain range further ensures good processing performance of the wafer. It should be noted that the pH value of the polishing solution used in the first and second polishing stages in this embodiment is 6 to 8.

[0051] In this embodiment, by controlling the type of polishing slurry and the content of each component in the polishing slurry, a polishing slurry with a specific concentration and particle size is used. Furthermore, the polishing pressure, rotation speed, and pH are controlled. This enables fine polishing, which not only prevents defects from forming on the surface of P-type silicon carbide wafers, but also makes it less likely for micro-damage layers to form on the wafer surface. As a result, nanoscale defects-free and ultra-low roughness surfaces can be achieved.

[0052] According to some preferred embodiments, in step (1), after cutting the P-type silicon carbide single crystal, the step of selecting the cut wafers is also included;

[0053] The selection criteria are: the thickness variation of each wafer is less than 15 μm, the warpage is less than 30 μm, and the thickness difference between different wafers is less than 5 μm.

[0054] In this embodiment, to ensure wafer consistency during subsequent processing, the wafers are first selected and grouped after dicing, ensuring that the thickness difference between different wafers within the same group is less than 5 μm. This allows for better control of the process parameters during subsequent wafer processing, thereby helping to maintain a low surface roughness.

[0055] The present invention also provides a P-type silicon carbide wafer, which is processed using any of the above-described processing methods.

[0056] According to some preferred embodiments, the surface roughness of the P-type silicon carbide wafer is less than 0.2 nm.

[0057] This invention overcomes the problem of wavy defects that easily occur during the processing of P-type silicon carbide wafers, and can obtain P-type silicon carbide wafers with low surface roughness. It can not only shorten the processing time of P-type silicon carbide wafers, but also improve the processing quality of P-type silicon carbide wafers. The P-type silicon carbide wafers processed by the processing method of this invention have a silicon surface roughness of less than 0.2 nm, a total thickness variation (TTV) of 2.526 μm, and a local thickness variation (LTV) of 0.85 μm.

[0058] To more clearly illustrate the technical solution and advantages of the present invention, a P-type silicon carbide wafer and its processing method are described in detail below through several embodiments.

[0059] Example 1:

[0060] (1) P-type silicon carbide single crystal (4 inches in diameter) was cut using 0.16 mm steel wire and diamond cutting fluid with a particle size of 5 μm to obtain multiple wafers; 24 wafers were selected as experimental wafers, with 6 wafers per group, divided into 4 groups, and the thickness difference between wafers in each group was less than 5 μm, the thickness difference within each wafer was less than 15 μm, the warpage was <30 μm, and there were no bright line cutting marks.

[0061] (2) Each group of wafers was polished using a diamond polishing slurry with a particle size of 4 μm and a polishing machine. Then, a diamond polishing slurry with a particle size of 1 μm was used to continue polishing the wafers. Polishing was stopped when the thickness difference between each group of wafers was less than 3 μm, the intra-wafer thickness difference of each wafer was less than 1 μm, and the surface roughness of the wafer was less than 1 nm. Afterward, the wafers underwent a first-stage polishing and a second-stage polishing process. First, a polishing slurry (pH 7.0) containing alumina abrasive particles (60 nm particle size) was used with a polishing machine to polish the silicon and carbon surfaces of the wafers respectively. Polishing was performed for 2 hours, followed by 3 hours of polishing using a polishing slurry (pH 7.0) containing silicon oxide abrasive particles (30 nm in diameter) and a polishing machine. Finally, the wax and visible particles adhering to the wafer surface were removed to obtain a P-type silicon carbide wafer. In the first stage of polishing, the polishing slurry contained 3% alumina abrasive particles, 0.5% oxidant (potassium permanganate), and 0.4% acid-base adjuster (dilute nitric acid). The lower platen speed of the polishing machine was 80 rpm / min, the upper platen speed was 90 rpm / min, and the pressure was 0.4 kg / cm². 2 The polishing slurry used in the second stage of polishing contained 6% silica abrasive particles, 1% oxidant (potassium permanganate), and 0.6% acid-base adjuster (dilute nitric acid). The lower platen of the polishing machine rotated at 60 rpm / min, the upper platen at 70 rpm / min, and the pressure was 0.3 kg / cm². 2 .

[0062] In this embodiment, the surface morphology of the P-type silicon carbide wafer is inspected using an optical microscope, such as... Figure 1 As shown, the wafer surface is smooth and defect-free, and roughness was measured using an atomic force microscope, such as... Figure 2 As shown, the surface roughness of the Si surface is 0.187 nm. The surface shape is inspected using a flatness measuring instrument. Figure 3 It can be seen that the TTV of the chip is 2.526μm and the LTV is 0.85μm.

[0063] Example 2:

[0064] (1) P-type silicon carbide single crystal (4 inches in diameter) was cut using 0.16 mm steel wire and diamond cutting fluid with a particle size of 6 μm to obtain multiple wafers; 24 wafers were selected as experimental wafers, with 6 wafers per group, divided into 4 groups, and the thickness difference between wafers in each group was less than 5 μm, the thickness difference within each wafer was less than 15 μm, the warpage was <30 μm, and there were no bright line cutting marks.

[0065] (2) First, each group of wafers was polished using a diamond polishing slurry with a particle size of 2 μm and a polishing machine. Then, the wafers were polished again using a diamond polishing slurry with a particle size of 0.5 μm and a polishing machine. Polishing was stopped when the thickness difference between each group of wafers was less than 3 μm, the thickness difference within each wafer was less than 1 μm, and the surface roughness of the wafer was less than 1 nm. Then, the wafers were polished in the first stage and the second stage. First, a polishing slurry (pH 9.0) containing alumina abrasive particles (80 nm in diameter) was used with a polishing machine to polish the silicon and carbon surfaces of the wafers respectively. Polishing was performed for 2 hours, followed by 3 hours of polishing using a polishing slurry (pH 9.0) containing silicon oxide abrasive particles (20 nm in diameter) and a polishing machine. Finally, the wax and visible particles adhering to the wafer surface were removed to obtain a P-type silicon carbide wafer. In the first stage of polishing, the polishing slurry contained 1% alumina abrasive particles, 3% oxidant (sodium hypochlorite), and 0.3% acid-base adjuster (sodium hydroxide). The lower platen speed of the polishing machine was 85 rpm / min, the upper platen speed was 95 rpm / min, and the pressure was 0.35 kg / cm². 2 The polishing slurry used in the second stage of polishing contains 10% silica abrasive particles, 5% oxidant (sodium hypochlorite), and 0.3% acid-base adjuster (sodium hydroxide). The lower platen of the polishing machine rotates at 65 rpm / min, the upper platen rotates at 75 rpm / min, and the pressure is 0.3 kg / cm². 2 .

[0066] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.195 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 3.235 μm and the LTV was 0.9 μm.

[0067] Example 3:

[0068] Example 3 is basically the same as Example 1, except that in step (2), the polishing liquid used in the first stage of polishing contains 0.9% alumina abrasive particles, 0.4% oxidant (potassium permanganate) and 0.2% acid-base regulator; the polishing liquid used in the second stage of polishing contains 4% silicon oxide abrasive particles, 0.8% oxidant (potassium permanganate) and 0.3% acid-base regulator.

[0069] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.235 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 3.55 μm and the LTV was 1.05 μm.

[0070] Example 4:

[0071] Example 4 is basically the same as Example 1, except that in step (2), the polishing liquid used in the first stage polishing contains 6% alumina abrasive particles, 6% oxidant (potassium permanganate) and 1.5% acid-base regulator; the polishing liquid used in the second stage polishing contains 11% silicon oxide abrasive particles, 7% oxidant (potassium permanganate) and 2% acid-base regulator.

[0072] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.19 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 4.562 μm and the LTV was 1.29 μm.

[0073] Example 5:

[0074] Example 5 is basically the same as Example 1, except that in step (2), the alumina abrasive particles in the polishing liquid used for the first stage of polishing have a particle size of 90 nm; and the silicon oxide abrasive particles in the polishing liquid used for the second stage of polishing have a particle size of 50 nm.

[0075] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.302 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 3.56 μm and the LTV was 0.98 μm.

[0076] Example 6:

[0077] Example 6 is basically the same as Example 1, except that in step (2), the pH value of the polishing liquid used in the first stage of polishing is 5.0, and the pH value of the polishing liquid used in the second stage of polishing is 5.0.

[0078] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.342 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 2.987 μm and the LTV was 0.98 μm.

[0079] Example 7:

[0080] Example 7 is basically the same as Example 1, except that in step (2), the wafer is polished in the first stage and the second stage in sequence. First, a polishing slurry containing silicon oxide abrasive particles (particle size 80nm) (pH 9.0) is used with a polishing machine to polish the silicon surface and carbon surface of the wafer for 2 hours respectively. Then, a polishing slurry containing alumina abrasive particles (particle size 20nm) (pH 9.0) is used with a polishing machine to polish the silicon surface of the wafer for 3 hours. Finally, the wax and visible particles attached to the wafer surface are removed to obtain a P-type silicon carbide wafer.

[0081] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.325 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 2.99 μm and the LTV was 0.79 μm.

[0082] Example 8:

[0083] Example 8 is basically the same as Example 1, except that in step (2), only diamond polishing slurry with a particle size of 2μm is used in conjunction with a polishing machine to polish each group of wafers for 64 hours.

[0084] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 70 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 5.65 μm and the LTV was 2.32 μm.

[0085] Comparative Example 1:

[0086] (1) Using 0.16 mm steel wire and diamond cutting fluid with a particle size of 5 μm, N-type and P-type silicon carbide single crystals (4 inches in diameter) were cut to obtain multiple wafers; 24 wafers of each type were selected as experimental wafers, and 6 wafers were divided into 4 groups. The thickness difference between wafers in each group was less than 15 μm, the thickness difference within each wafer was less than 5 μm, the warpage was <30 μm, and there were no bright line cutting marks.

[0087] (2) Each group of wafers was polished using a diamond polishing slurry with a particle size of 3 μm and a polishing machine. Then, a diamond polishing slurry with a particle size of 1 μm was used to continue polishing the wafers. Polishing was stopped when the thickness difference between each group of wafers was less than 3 μm, the thickness difference within each wafer was less than 1 μm, and the surface roughness of the wafer was less than 1 nm. Afterward, the wafers underwent a first-stage polishing and a second-stage polishing process sequentially. First, a polishing slurry (pH 9.6) containing alumina abrasive particles (300 nm particle size) was used with a polishing machine to polish the silicon and carbon surfaces of the wafers respectively. After h, a polishing slurry containing silicon oxide abrasive particles (80nm diameter) (pH 8.6) was used in conjunction with a polishing machine to polish the silicon surface of the wafer for 3 hours. Finally, the wax and visible particles adhering to the wafer surface were removed to obtain N-type and P-type silicon carbide wafers. The polishing slurry used in the first stage of polishing contained 1% alumina abrasive particles, 3% oxidant (potassium permanganate), and 0.3% acid-base adjuster (sodium hydroxide). The polishing machine used in the second stage of polishing had a lower plate speed of 55 rpm / min, an upper plate speed of 65 rpm / min, and a pressure of 0.2 kg / cm². 2The polishing slurry used in the second stage of polishing contained 10% silica abrasive particles, 5% oxidant (hydrogen peroxide), and 0.3% acid-base adjuster (dilute nitric acid). The polishing machine used in the second stage had a lower plate speed of 55 rpm / min, an upper plate speed of 65 rpm / min, and a pressure of 0.2 kg / cm². 2 .

[0088] In this embodiment, N-type silicon carbide wafers and P-type silicon carbide wafers are processed using existing technology. Figures 5 to 8 As can be seen, when the same processing technology is used to process N-type silicon carbide wafers and P-type silicon carbide wafers, there are obvious differences in the surface of P-type wafers and N-type wafers. The surface of N-type wafers is smooth, while the surface of P-type wafers has wavy processing defects. This indicates that the existing processing technology is only suitable for N-type silicon carbide wafers and not for P-type silicon carbide wafers.

[0089] Comparative Example 2:

[0090] Comparative Example 2 is basically the same as Example 1, except that in step (2), the wafer is polished. A polishing liquid containing alumina abrasive particles (particle size 80nm) (pH 9.0) is used in conjunction with a polishing machine to polish the silicon surface and carbon surface of the wafer for 2 hours to remove the wax and visible particles attached to the wafer surface and obtain a P-type silicon carbide wafer.

[0091] In this embodiment, an atomic force microscope was used for roughness detection, and the roughness of the Si surface was 0.85 nm. A flatness tester was used for surface shape detection, and the TTV of the wafer was 2.697 μm and the LTV was 0.981 μm.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of processing a P-type silicon carbide wafer, comprising: The processing method comprises the following steps: (1) cutting the P-type silicon carbide single crystal to obtain a plurality of wafers; (2) grinding and polishing each wafer respectively to obtain the P-type silicon carbide wafer; wherein the polishing comprises first stage polishing and second stage polishing, the polishing liquid used in the first stage polishing is a polishing liquid containing alumina, and the polishing liquid used in the second stage polishing is a polishing liquid containing silica; the polishing liquid used in the first stage polishing comprises alumina abrasive, oxidant and acid-base adjusting agent; the polishing liquid used in the second stage polishing comprises silica abrasive, oxidant and acid-base adjusting agent; the oxidant is at least one of potassium permanganate, sodium hypochlorite or hydrogen peroxide; the particle size of the alumina abrasive is 50-80 nm, and the particle size of the silica abrasive is 20-40 nm; in terms of mass percentage, the amount of alumina abrasive in the polishing liquid used in the first stage polishing is 1-5%, the amount of oxidant is 0.5-5%, and the amount of acid-base adjusting agent is 0.3-1%; in the polishing liquid used in the second stage polishing, the amount of silica abrasive is 5-10%, the amount of oxidant is 1-6%, and the amount of acid-base adjusting agent is 0.3-1%; the pH value of the polishing liquid used in the first stage and the second stage polishing is 6-8.

2. The processing method of the P-type silicon carbide wafer according to claim 1, wherein in step (1), the cutting liquid used in the cutting is a diamond cutting liquid; wherein the particle size of the diamond in the diamond cutting liquid is 4-6 μm.

3. The processing method of the P-type silicon carbide wafer according to claim 1, wherein in step (2), each wafer is ground in turn using a first grinding liquid and a second grinding liquid; the first grinding liquid and the second grinding liquid are both diamond grinding liquids, the particle size of the diamond in the first grinding liquid is 2-4 μm, and the particle size of the diamond in the second grinding liquid is 0-1 μm.

4. The processing method of the P-type silicon carbide wafer according to claim 1, wherein in step (2), the surface roughness of the ground wafer is less than 1 nm, the in-wafer thickness difference of the same wafer is less than 3 μm, and the inter-wafer thickness difference of different wafers is less than 5 μm.

5. The processing method of the P-type silicon carbide wafer according to claim 1, wherein the acid-base adjusting agent is at least one of nitric acid, hydrochloric acid, sodium hydroxide or potassium hydroxide.

6. The processing method of the P-type silicon carbide wafer according to claim 1, wherein in step (1), after cutting the P-type silicon carbide single crystal, the step of selecting and grouping the cut wafers is further included; The selection criteria are: the thickness difference of each wafer is less than 15 μm, the warping degree is less than 30 μm, and the thickness difference between different wafers is less than 5 μm. The P-type silicon carbide wafer is processed by the processing method according to any one of claims 1-6. The surface roughness of the P-type silicon carbide wafer is less than 0.2 nm. ​ ​ ​ 7. A P-type silicon carbide wafer, characterized by, ​ 8. A P-type silicon carbide wafer as claimed in claim 7, wherein, ​

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