A highly robust SCR device that uses secondary hysteresis to increase the holding current

Abstract

The present invention belongs to the field of electrostatic discharge (ESD: Electrostatic Discharge) protection for integrated circuits, and provides a highly robust SCR device with improved holding current utilizing secondary hysteresis characteristics. Compared with the traditional SCR structure, the positions of the N-type heavily doped region and the P-type heavily doped region in the N-type well region are swapped, increasing the current required to generate the desired voltage drop across its two ends. An additional N-type floating heavily doped region is added in the N-type well region, increasing a new NPN current path and raising the current required for the parasitic PNP transistor to turn on. An N-type moderately doped region is added in the N-type well region to reduce the injection efficiency of the emitter junction of the parasitic PNP, suppressing the positive feedback between the parasitic PNP and the parasitic NPN, thereby increasing the holding current of the SCR. The high holding current enables this new type of SCR device to provide strong protection capabilities in high-voltage integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the field of electrostatic discharge (ESD) protection for integrated circuits, and particularly relates to an ESD protection device, especially a silicon controlled rectifier (SCR) device, specifically a highly robust SCR device that uses secondary hysteresis to increase the holding current. Background Art

[0002] Electrostatic discharge is a phenomenon that commonly exists in nature. It is generated by the rapid transfer of charges between two objects at different electric potentials. Although electrostatic discharge is basically harmless to the human body, when it occurs in a precision integrated circuit, the transient high voltage and large current may damage the components in the integrated circuit, interfere with the normal operation of the chip, and even cause irreversible damage. For integrated circuits, electrostatic discharge is likely to occur on the pins of the integrated circuit during the processes from production to transportation, system integration, and user use.

[0003] For on-chip ESD protection, the operating range of the protection device is limited by the ESD design window of the corresponding process. Traditional ESD design windows, as Figure 1 shown, have two voltage boundary conditions. The lower limit voltage of the window is 1.1*VDD (VDD is the peak signal or power supply voltage at the chip I / O terminal). The trigger voltage V t1 and the clamping voltage V h of the protection device should be higher than this voltage to avoid latch-up effects and false triggering of the ESD device, and lower than the upper limit voltage of the design window. The upper limit voltage is the maximum voltage that the internal circuit of the chip can withstand. Generally, the upper limit voltage of the window is 0.9*BVmax (BVmax is usually the breakdown voltage of the gate oxide layer).

[0004] In addition to the above traditional ESD design windows, there is also an ESD design window based on a high holding current, as Figure 2 shown. This design window is determined by three boundaries, namely 1.1*VDD, 0.9*BVmax, and Imax (Imax is the maximum current when the chip is operating normally). Within this ESD design window, the trigger voltage V t1 of the protection device should be higher than the lower limit voltage to prevent false triggering and lower than the upper limit voltage. The clamping voltage V h1 can be lower than the lower limit voltage, but I h1 must be higher than Imax to avoid latch-up effects.

[0005] In on-chip ESD protection, the three most commonly used protection devices are diodes, MOSFETs, and SCRs. Diodes have the advantages of fast turn-on speed and simple structure, but their trigger voltage and ESD robustness are relatively low; MOSFETs have a higher trigger voltage and a hysteresis characteristic after turning on, so their ESD protection ability is higher than that of diodes; while after the SCR device turns on, it can generate deep hysteresis under the action of positive current feedback, keeping its holding voltage low, so it has the strongest ESD robustness per unit area.

[0006] As Figure 3 shown in the structural diagram and equivalent circuit of a traditional SCR device, the structure includes a P-type silicon substrate 110; an N-type well region 120 and a P-type well region 130 are formed on the substrate, and the N-type well region 120 is adjacent to the P-type well region 130; an N-type heavily doped region 121 and a P-type doped region 122 are provided in the N-type well region 120, and the N-type heavily doped region 121 and the P-type heavily doped region 122 are connected to the anode; an N-type heavily doped region 131 and a P-type heavily doped region 132 are provided in the P-type well region 130, and the N-type heavily doped region 131 and the P-type heavily doped region 132 are connected to the cathode.

[0007] The equivalent circuit of a traditional SCR device is composed of a parasitic PNP transistor Q1 and a parasitic NPN transistor Q2. Among them, the P-type heavily doped region 122, the N-type well region 120, the P-type well region 130, and the P-type heavily doped region 132 form the parasitic PNP transistor Q1; the N-type heavily doped region 131, the P-type well region 130, the N-type well region 120, and the N-type heavily doped region 121 form the parasitic NPN transistor Q2; R NW is the resistance of the N-type well region 120, and R PW is the resistance of the P-type well region 130.

[0008] When a positive pulse is applied to the anode of the SCR device (the cathode is grounded), the PN junction formed by the N-type well region 120 and the P-type well region 130 is reverse-biased. When the pulse voltage is greater than the breakdown voltage of the well PN junction, a large number of electron-hole pairs are generated near the well PN junction; electrons reach the anode through the N-type well region 120 and the N-type heavily doped region 121, and a voltage drop occurs on the resistance R NW of the N-type well region 120, finally causing the PN junction formed by the P-type heavily doped region 122 and the N-type well region 120 to be forward-biased, and the parasitic PNP Q1 transistor turns on; at the same time, holes reach the cathode through the P-type well region 130 and the P-type heavily doped region 132, and a voltage drop occurs on the resistance R PWA voltage drop is generated thereon, eventually causing the PN junction formed by the P-type well region 130 and the N-type heavily doped region 131 to be forward-biased, and the parasitic NPN Q2 transistor to turn on. After that, the collector current of the parasitic PNP transistor provides the base current for the parasitic NPN transistor, and the collector current of the parasitic NPN transistor provides the base current for the parasitic PNP transistor. The two transistors form a current positive feedback mechanism, the SCR low-resistance path conducts, and the voltage across the device is clamped in a lower range, generally about 1.5V. Due to the above characteristics, the SCR device can discharge current at a lower voltage and has strong ESD robustness. Therefore, the ESD protection device based on the SCR structure has become an important choice in the ESD protection scheme.

[0009] Under the limitation of the traditional ESD design window as shown in Figure 1 , in order to prevent the latch-up effect, it is necessary to increase the holding voltage V h1 of the SCR device. Therefore, the SCR device cannot clamp the voltage to a lower level, thus greatly reducing the ESD protection ability. This problem is more prominent in the protection of high-voltage integrated circuits. To solve the above problems, an ESD design window based on a high holding current as shown in Figure 2 can be adopted. By increasing the holding current I h1 of the SCR device, the protection device has a lower holding voltage V h1 under the condition of the high holding current I h1 . This means that the device can utilize the high robustness of the SCR while avoiding the latch-up effect and ensuring the normal operation of the internal circuit. Summary of the Invention

[0010] The object of the present invention is to provide a highly robust SCR device that utilizes the secondary hysteresis characteristic to increase the holding current. Based on the traditional SCR structure, this structure improves the holding current of the SCR device through the two hysteresis characteristics of the device and maintains a high device robustness.

[0011] An implementation of the present invention is a highly robust SCR device that utilizes the secondary hysteresis characteristic to increase the holding current. The device structure and equivalent circuit are as shown in Figure 4As shown. In this high-holding-current SCR device, the positions of the N-type heavily doped region 122 and the P-type heavily doped region 121 in the N-type well region 120 are swapped based on the traditional SCR device, and a floating N-type heavily doped region 123 and an N-type moderately doped region 124 are added in the N-type well region 120. When a positive pulse is applied to the anode of the high-holding-current SCR device (the cathode is grounded), first, the PN junction formed by the N-type well region 120 and the P-type well region 130 is reverse-biased. When the voltage applied across the PN junction is greater than its avalanche breakdown voltage, a large number of electron-hole pairs are generated near the PN junction. The generated electrons reach the anode through the N-type well region 120, the N-type doped region 123, and the N-type heavily doped region 122. At the same time, the generated holes reach the cathode through the P-type well region 130 and the P-type heavily doped region 132. When the current causes the voltage drop across the well resistance R of the P-type well region 130 to increase to make the PN junction formed by the P-type well region 130 and the N-type heavily doped region 131 forward-biased, since the resistance of the N-type heavily doped region 123 is less than that of the N-type well region 120, initially the current mainly flows from the anode through the N-type heavily doped region 122, the N-type well region 120, the N-type heavily doped region 123, the P-type well region 130, and the N-type heavily doped region 131 to the cathode, and the parasitic lateral NPN transistor Q1 is turned on, and its current is as shown by the dashed line 201 in PW . As the current further increases, the voltage drop across the well resistance R of the P-type well region 130 increases, and the parasitic vertical NPN transistor Q2 is turned on, and the current path gradually expands into the device body. The current flows from the anode through the N-type heavily doped region 122, the N-type well region 120, the P-type well region 130, and the N-type heavily doped region 131 to the cathode. The current path at this stage is as shown by the dashed line 202 in Figure 4 . When the voltage drop across the resistance R of the N-type well region 120 increases to make the PN junction formed by the P-type heavily doped region 121 and the N-type moderately doped region 124 forward-biased, the emitter junction of the parasitic PNP transistor Q3 is forward-biased. The current flows from the anode through the P-type heavily doped region 121, the N-type moderately doped region 124, the N-type well region 120, the P-type well region 130, and the P-type heavily doped region 132 to the cathode, and the parasitic PNP transistor Q3 is turned on. The current path is as shown by the dashed line 203 in PW Figure 4 . Finally, the collector current of the parasitic PNP transistor provides the base current for the parasitic NPN transistor, and the collector current of the parasitic NPN transistor provides the base current for the parasitic PNP transistor. The two transistors form a current positive feedback mechanism. The current flows from the anode through the P-type heavily doped region 121, the N-type moderately doped region 124, the N-type well region 120, the P-type well region 130, and the N-type heavily doped region 131 to the cathode, and the SCR path is formed. At this time, the current path is as shown by the dashed line 204 in Figure 4 NW Figure 4 . The schematic diagram of the I-V characteristic curve of this high-holding-current SCR device is as shown in Figure 4 Figure 4 , and this device has the characteristic of two hysteresis loops. Figure 5 As shown.

[0012] The beneficial effects of the present invention are as follows:

[0013] The present invention provides a highly robust SCR device that uses secondary hysteresis to increase the holding current. Compared with the traditional SCR structure, the positions of the heavily doped N-region 122 and the heavily doped P-region 121 in the N-well region 120 are swapped, effectively reducing the resistance R of the N-well region 120 NW , thereby increasing the magnitude of the holding current; an additional floating heavily doped N-region 123 is added to the N-well region 120, adding a parasitic NPN transistor Q1 current path, making the turn-on of the simple parasitic NPN transistor become a process in which the lateral NPN transistor and the vertical NPN transistor turn on sequentially, resulting in two hysteresis characteristics of the device and increasing the magnitude of the holding current; a moderately doped N-region 124 is added to the N-well region 120 to reduce the injection efficiency of the emitter junction of the parasitic PNP transistor Q3 and suppress the positive feedback between the parasitic PNP transistor Q3 and the parasitic NPN transistor Q2, thereby increasing the holding current of the SCR. Therefore, this new type of SCR device has a relatively high holding current and a relatively small holding voltage, and can provide strong protection capabilities for high-voltage integrated circuits. Description of the Drawings

[0014] Figure 1 is the traditional ESD design window;

[0015] Figure 2 is the ESD design window based on high holding current;

[0016] Figure 3 is the structure and equivalent circuit of the traditional SCR device;

[0017] Figure 4 is the structure and equivalent circuit of a high holding current SCR device proposed by the present invention;

[0018] Figure 5 is a schematic diagram of the I-V characteristic curve of a high holding current SCR device proposed by the present invention. Detailed Embodiments

[0019] The present invention will be described in detail below in conjunction with the drawings and specific embodiments.

[0020] The embodiments of the present invention are as shown in Figure 4As shown. The device includes a P-type silicon substrate 110, an adjacent N-type well region 120 and a P-type well region 130 formed on the P-type silicon substrate 110; a P-type heavily doped region 121, an N-type heavily doped region 122, an N-type heavily doped region 123 and an N-type moderately doped region 124 are provided in the N-type well region 120. The N-type heavily doped region 123, the N-type heavily doped region 122 and the P-type heavily doped region 121 are sequentially away from the N-type well region 120 and the P-type well region 130 to form the junction surface of the PN junction, and are isolated by a shallow trench isolation region. The N-type moderately doped region 124 is located directly below the P-type heavily doped region 121 and the shallow trench isolation region between the P-type heavily doped region 121 and the N-type heavily doped region 122; an N-type heavily doped region 131 and a P-type heavily doped region 132 are provided in the P-type well region 130;

[0021] The P-type heavily doped region 121 and the N-type heavily doped region 122 in the N-type well region 120 are connected to the anode; the N-type heavily doped region 131 and the P-type heavily doped region 132 in the P-type well region 130 are connected to the cathode.

[0022] When a positive pulse is applied to the anode of the device (the cathode is grounded), first, the PN junction formed by the N-type well region 120 and the P-type well region 130 is reverse-biased. When the voltage applied across the PN junction is greater than its avalanche breakdown voltage, a large number of electron-hole pairs are generated near the PN junction, and the current increases sharply. At this time, the I-V characteristic is as shown in Figure 5 Stage 1 in. The electrons generated near the PN junction reach the anode through the N-type well region 120, the N-type doped region 123 and the N-type heavily doped region 122. At the same time, the holes generated reach the cathode through the P-type well region 130 and the P-type heavily doped region 132. When the voltage drop across the well resistance R PW in the P-type well region 130 increases to make the PN junction formed by the P-type well region 130 and the N-type heavily doped region 131 forward-biased, the parasitic lateral NPN transistor Q1 is turned on. Due to the negative resistance effect of the conduction of the NPN transistor, the I-V characteristic at this time is as shown in Figure 5 Stage 2 in. As the current increases, the voltage decreases, and the curve shows hysteresis. Since the resistance of the N-type heavily doped region 123 is less than that of the N-type well region 120, at the beginning, the initial current mainly flows from the anode through the N-type heavily doped region 122, the N-type well region 120, the N-type heavily doped region 123, the P-type well region 130 and the N-type heavily doped region 131 to the cathode. As the current further increases, the voltage drop across the well resistance R PW in the P-type well region 130 increases, and the parasitic longitudinal NPN transistor Q2 is turned on. The current path gradually expands into the device body. The current flows from the anode through the N-type heavily doped region 122, the N-type well region 120, the P-type well region 130, and the N-type heavily doped region 131 to the cathode. At this time, the I-V characteristic is as shown in Figure 5 Stage 3 in. When the resistance R NWThe voltage drop across both ends increases to forward bias the PN junction formed by the P-type heavily doped region 121 and the N-type moderately doped region 124, and forward bias the emitter junction of the parasitic PNP transistor Q3. The current flows from the anode through the P-type heavily doped region 121, the N-type moderately doped region 124, the N-type well region 120, the P-type well region 130, and the P-type heavily doped region 132 to the cathode, turning on the Q3 transistor. Eventually, the collector current of the parasitic PNP transistor provides the base current for the parasitic NPN transistor, and the collector current of the parasitic NPN transistor provides the base current for the parasitic PNP transistor. The two transistors form a positive current feedback mechanism. The current flows from the anode through the P-type heavily doped region 121, the N-type moderately doped region 124, the N-type well region 120, the P-type well region 130, and the N-type heavily doped region 131 to the cathode, forming a low-resistance SCR path, the voltage decreases sharply, and a deep hysteresis appears in the curve. The I-V characteristic at this time is as Figure 5 shown in stage 4 of

[0023] As described above, the above are only specific embodiments of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similarly acting alternative features; all the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A highly robust SCR device structure that uses secondary hysteresis to increase the holding current, characterized in that: The first conduction type is P-type, and the second conduction type is N-type; The device includes a silicon substrate of the first conduction type, an adjacent well region of the second conduction type and a well region of the first conduction type formed on the silicon substrate of the first conduction type; a heavily doped region of the first conduction type, a first heavily doped region of the second conduction type, a second heavily doped region of the second conduction type, and a moderately doped region of the second conduction type are provided in the well region of the second conduction type. The second heavily doped region of the second conduction type, the first heavily doped region of the second conduction type, and the heavily doped region of the first conduction type are sequentially away from the well region of the second conduction type and the well region of the first conduction type to form the junction surface of the PN junction, and are isolated by a shallow trench isolation region. The moderately doped region of the second conduction type is located directly below the heavily doped region of the first conduction type and the shallow trench isolation region between the heavily doped region of the first conduction type and the first heavily doped region of the second conduction type; a heavily doped region of the second conduction type and a heavily doped region of the first conduction type are provided in the well region of the first conduction type. The heavily doped region of the first conduction type and the first heavily doped region of the second conduction type in the well region of the second conduction type are connected to the anode; the heavily doped region of the second conduction type and the heavily doped region of the first conduction type in the well region of the first conduction type are connected to the cathode.

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