Semiconductor devices

Abstract

A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stack sequentially disposed on a substrate, as well as a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is located within a first device region and includes a first gate, a first source, and a first drain disposed on the compound semiconductor stack. The second transistor is located within a second device region and includes a second gate, a second source, and a second drain disposed on the compound semiconductor stack. The isolation structure is disposed between the first transistor and the second transistor. The conductive structure is located within the second device region, penetrates the compound semiconductor stack, and electrically connects the semiconductor layer to the second source. There is no electrical connection between the semiconductor layer within the first device region and the first source.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to a semiconductor device comprising a high electron mobility transistor. Background Technology

[0002] In semiconductor technology, III-V compound semiconductors can be used to form various integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are transistors with a two-dimensional electron gas (2-DEG), where the 2-DEG is adjacent to the junction (i.e., heterojunction) between two materials with different band gaps. Because HEMTs do not use doped regions as carrier channels but rather use 2-DEGs, they possess several attractive characteristics compared to existing metal-oxide-semiconductor field-effect transistors (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies.

[0003] Half-bridge circuits are widely used in power electronics. However, when the high-side and low-side switching elements of a half-bridge circuit share the same substrate, they are susceptible to crosstalk, making it difficult to implement a System-on-a-Chip (SoC) half-bridge circuit. HEMTs can be used in half-bridge circuits as both high-side and low-side switching elements, achieving the benefits of SoC. However, some problems still need to be overcome when HEMTs are used in half-bridge circuits. Summary of the Invention

[0004] In view of this, the present invention proposes a semiconductor device comprising a high electron mobility transistor with an improved back electrode to solve the problems encountered when high electron mobility transistors are used in half-bridge circuits.

[0005] According to an embodiment of the present invention, a semiconductor device is provided, comprising a substrate, an insulating layer, a semiconductor layer, a compound semiconductor stack, a first transistor, a second transistor, an isolation structure, and a conductive structure. The insulating layer, the semiconductor layer, and the compound semiconductor stack are sequentially disposed on the substrate. The first transistor is located within a first device region and includes a first gate, a first source, and a first drain disposed on the compound semiconductor stack. The second transistor is located within a second device region and includes a second gate, a second source, and a second drain disposed on the compound semiconductor stack. The isolation structure is disposed between the first transistor and the second transistor. The conductive structure is located within the second device region, penetrates the compound semiconductor stack, and electrically connects the semiconductor layer to the second source. The semiconductor layer located within the first device region is not electrically connected to the first source.

[0006] To make the features of the present invention clear and easy to understand, embodiments are provided below, along with accompanying drawings, for detailed explanation. Attached Figure Description

[0007] To facilitate understanding of the following text, reference should be made to the accompanying drawings and their detailed description while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0008] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2 This is a half-bridge circuit illustrated according to an embodiment of the present invention.

[0010] Figure 3 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0012] Figure 5 This is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention.

[0013] Figure 6 This is a half-bridge circuit illustrated according to another embodiment of the present invention.

[0014] The annotations in the attached figures are explained as follows:

[0015] 100 Semiconductor device; 100-1 First transistor; 100-2 First transistor; 101 Substrate; 101-1 First device region; 101-2 Second device region; 103 Insulating layer; 105 Semiconductor layer; 106 Buffer layer; 107 High-resistivity layer; 108 Channel layer; 109 Barrier layer; 110 Compound semiconductor stack; 111 First capping layer; 112 Second capping layer; 113 Conductive structure; 115 Conductive structure; 116 Conductive pad; 117 Interconnect Interconnection structure; 118 wires; 120 isolation structure; 130 half-bridge circuit; 140 sealing ring; 200 semiconductor device; 200-1 first transistor; 200-2 first transistor; 230 half-bridge circuit; G1 first gate; G2 second gate; S1 first source; S2 second source; D1 first drain; D2 second drain; 2DEG two-dimensional electron gas region; B1, B2 back electrodes; Vin input voltage node; GND ground terminal; Cox parasitic capacitance Detailed Implementation

[0016] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0017] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "upper," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one element or feature and another (or more) element or feature in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0018] Although the present invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

[0019] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0020] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means or connections.

[0021] In this invention, "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element may be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Furthermore, "Group III-V semiconductors" can be binary, ternary, or quaternary compound semiconductors, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), and their analogues or combinations thereof, but are not limited thereto. In addition, depending on requirements, Group III-V semiconductors may also include dopants to form Group III-V semiconductors with specific conductivity types, such as n-type or p-type Group III-V semiconductors. In the following text, Group III-V semiconductors may also be referred to as III-V semiconductors.

[0022] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0023] This invention relates to a semiconductor device comprising a high electron mobility transistor (HEMT), which can serve as a high-voltage switching element (or upper-bridge switching element) and a low-voltage switching element (or lower-bridge switching element) in a half-bridge circuit. According to embodiments of the invention, there is no electrical connection between the back electrode and the source electrode of the HEMT serving as the upper-bridge switching element. Instead, the back electrode of the HEMT is electrically connected to ground, or the back electrode of the HEMT serves as an electrically floating layer. This prevents the generation of parasitic capacitance between the back electrode of the upper-bridge switching element and the substrate of the semiconductor device, thereby avoiding the impact on the input / output voltage of the semiconductor device and preventing the thickness between the back electrode and the substrate of the semiconductor device from limiting the device's supply voltage (Vbus) capability.

[0024] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, in one embodiment, the semiconductor device 100 includes a substrate 101, an insulating layer 103, a semiconductor layer 105, and a compound semiconductor stack 110 disposed sequentially from bottom to top. According to some embodiments, the substrate 101 may be made of ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire, or silicon. When the substrate 101 is made of a material with high hardness, high thermal conductivity, and low electrical conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. Here, the aforementioned high hardness, high thermal conductivity, and low electrical conductivity are relative to a single-crystal silicon substrate, and a high-voltage semiconductor device refers to a semiconductor device with an operating voltage higher than 50V. The insulating layer 103 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the semiconductor layer 105 may be made of silicon or polycrystalline silicon. In one embodiment, the substrate 101 is, for example, silicon, the insulating layer 103 is, for example, silicon oxide, and the semiconductor layer 105 is, for example, silicon. The substrate 101, the insulating layer 103, and the semiconductor layer 105 constitute a semiconductor on insulator (SOI) substrate, meaning that the substrate 101, the insulating layer 103, and the semiconductor layer 105 in one embodiment of the present invention can be provided by an SOI substrate. In another embodiment, the substrate 101, the insulating layer 103, and the semiconductor layer 105 can be provided by a composite substrate (also known as a QST substrate) consisting of a core substrate encapsulated by a composite material layer. The core substrate includes ceramic, silicon carbide, aluminum nitride, sapphire, or silicon. The composite material layer includes an insulating material layer and a semiconductor material layer. The insulating material layer can be a single layer or multiple layers of silicon oxide, silicon nitride, or silicon oxynitride. The semiconductor material layer can be silicon or polycrystalline silicon. During the fabrication of the semiconductor device, the composite material layer located on the back side of the core substrate is removed by a thinning process, such as by a grinding or etching process, so that the back side of the core substrate is exposed. In some embodiments, the thickness of the insulating layer 103 may range from about 1 micrometer (μm) to 3 micrometers (μm), for example, about 2 micrometers (μm), and the thickness of the semiconductor layer 105 may range from about 5 nanometers (nm) to 350 nanometers (nm). The thickness of the semiconductor layer 105 may be moderately adjusted to prevent cracking. In some embodiments, the substrate 101 is an insulating substrate, the material of which comprises ceramic, aluminum nitride, or sapphire. In other embodiments, the substrate 101 is electrically connected to a ground terminal.

[0025] According to embodiments of the present invention, a compound semiconductor stack 110 is disposed on a semiconductor layer 105 to form a high electron mobility transistor. The compound semiconductor stack 110 can be formed on the semiconductor layer 105 via epitaxial growth, and the semiconductor layer 105 can serve as a nucleation layer for the compound semiconductor stack 110. According to some embodiments, the compound semiconductor stack 110 may include a buffer layer 106, a high resistance layer (or electrical isolation layer) 107, a channel layer 108, and a barrier layer 109, which are sequentially stacked on the semiconductor layer 105 from bottom to top, and the material of each layer of the compound semiconductor stack 110 includes a group III-V compound semiconductor (also known as a group III-V semiconductor). In one embodiment, the buffer layer 106 may be a superlattice (SL) structure, such as comprising multiple alternating layers of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN), the high-resistivity layer 107 may be, for example, a carbon-doped gallium nitride (c-GaN) layer, the channel layer 108 may be, for example, an undoped gallium nitride (u-GaN) layer, and the barrier layer 109 may be, for example, an aluminum gallium nitride (AlGaN) layer, but is not limited thereto. Furthermore, the compound semiconductor stack 110 may further comprise other layers, such as an epitaxial layer (e.g., AlN) for reducing lattice defects, which may be disposed between the buffer layer 106 and the semiconductor layer 105. The composition and structural configuration of the layers of the compound semiconductor stack 110 may be determined according to the requirements of various semiconductor devices.

[0026] According to an embodiment of the present invention, the semiconductor device 100 further includes a first transistor 100-1 and a second transistor 100-2. The first transistor 100-1 is located within a first device region 101-1 and includes a first gate G1, a first source S1, and a first drain D1 disposed on a compound semiconductor stack 110. The second transistor 100-2 is located within a second device region 101-2 and includes a second gate G2, a second source S2, and a second drain D2 disposed on the compound semiconductor stack 110. Furthermore, the first transistor 100-1 further includes a first capping layer 111 disposed between the first gate G1 and the barrier layer 109, and the second transistor 100-2 further includes a second capping layer 112 disposed between the second gate G2 and the barrier layer 109. In one embodiment, the first capping layer 111 and the second capping layer 112 are, for example, p-type gallium nitride (p-GaN) layers, but are not limited thereto. Because of the discontinuous bandgap between the channel layer 108 and the barrier layer 109, by stacking the channel layer 108 and the barrier layer 109 together, electrons are concentrated at the heterojunction between the channel layer 108 and the barrier layer 109 due to the piezoelectric effect, thus generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas region 2DEG. For normally-off devices, when no voltage is applied to the first gate G1 and the second gate G2, the area covered by the first capping layer 111 and the second capping layer 112 will not form a two-dimensional electron gas (e.g., ...). Figure 1 As shown, this region can be considered a 2DEG cutoff region, where there is no conduction between the first source S1 and the first drain D1, or between the second source S2 and the second drain D2. When a positive voltage is applied to the first gate G1 and the second gate G2, a two-dimensional electron gas is formed in the region covered by the first capping layer 111 and the second capping layer 112, creating a continuous two-dimensional electron gas region between the first source S1 and the first drain D1, and between the second source S2 and the second drain D2, thus enabling conduction between the first source S1 and the first drain D1, and between the second source S2 and the second drain D2. In an embodiment of the present invention, the first transistor 100-1 and the second transistor 100-2 are high electron mobility transistors (HEMTs).

[0027] Furthermore, the semiconductor device 100 also includes an isolation structure 120 disposed between the first transistor 100-1 and the second transistor 100-2. In some embodiments, the isolation structure 120 penetrates the compound semiconductor stack 110 and the semiconductor layer 105, and further extends downward to a depth of the insulating layer 103, wherein the bottom surface of the isolation structure 120 may be lower than the top surface of the insulating layer 103. The isolation structure 120 can be formed by etching deep trenches in the compound semiconductor stack 110, the semiconductor layer 105, and the insulating layer 103, filling the deep trenches with a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof, and performing a chemical-mechanical planarization (CMP) process. In some embodiments, the isolation structure 120 may be one or more annular insulating pillar structures surrounding the first transistor 100-1 and the second transistor 100-2. In an embodiment of the present invention, the semiconductor layer 105 can serve as the backside electrode of the first transistor 100-1 and the second transistor 100-2, while the isolation structure 120 penetrating the compound semiconductor stack 110 and the semiconductor layer 105 can provide good electrical isolation between the first transistor 100-1 and the second transistor 100-2.

[0028] Figure 2 The half-bridge circuit 130 shown is an embodiment of the present invention, such as Figure 2 As shown, the first transistor 100-1 can be a high-voltage switching element (or upper-bridge switching element) of the half-bridge circuit 130, and the second transistor 100-2 can be a low-voltage switching element (or lower-bridge switching element) of the half-bridge circuit 130. The first drain D1 of the upper-bridge switching element is electrically connected to an input voltage node Vin, the second source S2 of the lower-bridge switching element is electrically connected to ground GND, and the first source S1 of the upper-bridge switching element is electrically connected to the second drain D2 of the lower-bridge switching element. Furthermore, they can also be electrically connected to an output voltage node (not shown). Please also refer to... Figure 1 and Figure 2The semiconductor device 100 further includes a conductive structure 113 disposed within the second element region 101-2. The conductive structure 113 penetrates the compound semiconductor stack 110 within the second element region 101-2 and electrically connects the semiconductor layer 105 within the second element region 101-2 to the second source S2. Since the semiconductor layer 105 can serve as the back electrode B1 of the first transistor 100-1 and the back electrode B2 of the second transistor 100-2, the conductive structure 113 can electrically connect the back electrode B2 of the second transistor 100-2 (also known as a lower-bridge switching element) to the second source S2. The second source S2 of the lower-bridge switching element is usually electrically connected to a ground node. Therefore, the back electrode B2 of the second transistor 100-2 can be electrically grounded via the conductive structure 113 and the second source S2.

[0029] Furthermore, according to an embodiment of the present invention, the semiconductor layer 105 located in the first element region 101-1 is not electrically connected to the first source S1. That is, the back electrode B1 of the first transistor 100-1 (also known as the upper bridge switching element) is not directly electrically connected to the first source S1, and there is no conductive structure in the vertical projection region of the first source S1 that penetrates the compound semiconductor stack 110 and is connected to the semiconductor layer 105. Since the first source S1 of the upper bridge switching element is electrically connected to the second drain D2 of the lower bridge switching element through the interconnect structure 117 and has the potential of the output voltage, and the semiconductor layer 105 in the first element region 101-1 of the embodiment of the present invention is not electrically connected to the first source S1, the semiconductor layer 105 in the first element region 101-1 will not have the potential of the output voltage, thereby avoiding the generation of parasitic capacitance between the semiconductor layer 105 in the first element region 101-1 and the substrate 101, thereby preventing the input / output voltage of the semiconductor device 100 from being affected and maintaining the normal operating voltage.

[0030] According to one embodiment of the present invention, please also refer to Figure 1 and Figure 2 The semiconductor layer 105 (back electrode B1 of the upper bridge switching element) in the first element region 101-1 can be electrically connected to the ground terminal via another conductive structure 115 disposed outside the first gate G1, the first source S1 and the first drain D1, such as Figure 2 As shown, in one embodiment, the back electrode B1 of the upper bridge switching element and the second source electrode S2 of the lower bridge switching element are both electrically connected to the same ground node. Figure 1As shown, in one embodiment, another conductive structure 115 is disposed in a region outside the vertical projection region of the first gate G1, the first source S1 and the first drain D1, and the conductive structure 115 penetrates the compound semiconductor stack 110 and is electrically connected to the semiconductor layer 105. The conductive structure 115 can be electrically connected to the ground terminal via the conductive pad 116 disposed above it, thereby making the back electrode B1 of the upper bridge switching element electrically connected to the ground terminal via the conductive structure 115, the conductive pad 116 and other connection structures.

[0031] Figure 3 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 3 As shown, in one embodiment, the periphery of the first component region 101-1 and / or the second component region 101-2 is surrounded by a conductive sealing ring 140. The conductive pad 116 within the first component region 101-1 can be electrically connected via a wire 118 to the sealing ring 140 disposed around the component region of the semiconductor device 100, and electrically connected via the sealing ring 140 to a ground terminal, such that the conductive structure 115 located below the conductive pad 116 within the first component region 101-1 is electrically connected to the ground terminal, thereby electrically grounding the semiconductor layer 105 within the first component region 101-1. The aforementioned wire 118 can be disposed in a dielectric layer (not shown) above the conductive pad 116, but is not limited thereto. Although Figure 3 Only two first element regions 101-1 and two second element regions 101-2 are shown surrounded by sealing rings 140. In reality, there can be more element regions surrounded by sealing rings 140, and each element region is surrounded by an isolation structure 120. In one embodiment, the isolation structures 120 can be interconnected to form a mesh structure. In addition, the isolation structure 120 can be an insulating pillar structure surrounding the conductive structure 115 below the conductive pad 116 to avoid unnecessary electrical connections between adjacent first element regions 101-1 and second element regions 101-2.

[0032] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. Figure 4 Semiconductor device 100 and Figure 1The difference in the semiconductor device 100 is that the first source S1 and first drain D1 of the first transistor 100-1, and the second source S2 and second drain D2 of the second transistor 100-2, all extend downward through the barrier layer 109 to the top surface of the channel layer 108. Furthermore, the conductive structure 113 within the second element region 101-2 is disposed directly below the second source S2, penetrating the entire channel layer 108, the high-resistivity layer 107, and the buffer layer 106, but not penetrating the barrier layer 109. In another embodiment, the first source S1, the first drain D1, the second source S2, and the second drain D2 may further extend downward to a depth within the channel layer 108, and the conductive structure 113 in contact with the second source S2 may penetrate a portion of the channel layer 108, the high-resistivity layer 107, and the buffer layer 106.

[0033] In addition, Figure 4 In the semiconductor device 100, the isolation structure 120 penetrates the compound semiconductor stack 110 and the semiconductor layer 105, reaching the top surface of the insulating layer 103; that is, the bottom surface of the isolation structure 120 and the top surface of the insulating layer 103 are on the same plane. In some embodiments, the substrate 101 is an insulating substrate, the material of which includes ceramic, aluminum nitride, or sapphire. In other embodiments, the substrate 101 is electrically connected to a ground terminal. Furthermore, in Figure 4 In the semiconductor device 100, the semiconductor layer 105 in the first element region 101-1 can be an electrically floating layer, that is, the semiconductor layer 105 in the first element region 101-1 is not electrically floating. Figure 1 The other conductive structure 115 shown is electrically connected to the ground terminal, and instead the semiconductor layer 105 in the first element region 101-1 has a floating potential close to 0V. Since the substrate 101 has a ground potential or is an insulating substrate, no parasitic capacitance is generated between the semiconductor layer 105 in the first element region 101-1 and the substrate 101.

[0034] Figure 5 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. Figure 5 As shown, the semiconductor device 200 in this embodiment and Figure 1 and Figure 4 The difference in the semiconductor device 100 is that the first source S1 of the first transistor 200-1, which is an upper bridge switching element, is electrically connected to the semiconductor layer 105 in the first element region 101-1 via a conductive structure 113. Figure 6 This is a half-bridge circuit 230 illustrated according to another embodiment of the present invention. Please also refer to... Figure 5 and Figure 6Because the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 in this embodiment, that is, the back electrode B1 of the first transistor 200-1, is electrically connected to the first source S1, and the first source S1 is electrically connected to the second drain D2, and is further electrically connected to the node of the output voltage (not shown), the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 in this embodiment will have a floating potential from 0V to the output voltage, which causes a parasitic capacitance Cox to be generated between the semiconductor layer 105 in the first element region 101-1 of the semiconductor device 200 and the substrate 101, affecting the input / output voltage of the semiconductor device 200, causing the power supply to be unable to maintain the normal operating voltage.

[0035] Furthermore, the parasitic capacitance Cox of the semiconductor device 200 in this embodiment is affected by the thickness of the insulating layer 103. To reduce the parasitic capacitance Cox, the thickness of the insulating layer 103 of the semiconductor device 200 must be increased. However, the thicker the insulating layer 103 is, the worse the heat dissipation capacity of the semiconductor device 200 will be, resulting in a decrease in the performance of the semiconductor device 200.

[0036] In comparison, targeting Figures 1 to 4 In the illustrated semiconductor device 100, since the back electrode B1 of the first transistor 100-1 of the first element region 101-1 of the semiconductor device 100 of the embodiment of the present invention is electrically connected to the ground node, or is an electrically floating layer with a potential close to 0V, no parasitic capacitance is generated between the semiconductor layer 105 and the substrate 101 in the first element region 101-1. Therefore, the thickness of the insulating layer 103 is not limited; that is, the thickness of the insulating layer 103 can be relatively thin to maintain the heat dissipation capability of the semiconductor device 100. Furthermore, according to some embodiments of the present invention, the substrate 101 is an electrically insulating and thermally conductive substrate, for example, made of highly insulating and highly thermally conductive aluminum nitride (AlN), whose thermal conductivity is higher than that of the insulating layer 103. At this time, the substrate 101 can not only increase the heat dissipation capacity of the semiconductor device 100, but also increase the overall insulation thickness that constitutes the parasitic capacitance (that is, the thickness of the insulating layer 103 plus the thickness of the substrate 101), thereby significantly reducing the parasitic capacitance. The parasitic capacitance can be largely eliminated and ignored, thus avoiding the limitation of the device supply voltage (Vbus) by the insulation layer thickness (vertical thickness) below the back electrode of the semiconductor device 100.

[0037] Therefore, the semiconductor device of the present invention can use high electron mobility transistors as the upper and lower bridge switching elements of the half-bridge circuit to achieve the benefits of system-on-a-chip (SoC), avoid the parasitic inductance and capacitance effects caused by wire bonding between the upper and lower bridge switching elements, and eliminate the parasitic capacitance between the back electrode of the upper bridge switching element and the substrate. It also avoids the limitation of the device's supply voltage (Vbus) by the thickness of the insulating layer under the back electrode, so as to maintain the heat dissipation function of the semiconductor device and thus improve the performance of the semiconductor device.

[0038] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: An insulating layer, a semiconductor layer, and a compound semiconductor stack are sequentially disposed on a substrate; A first transistor is located in a first element region and includes a first gate, a first source and a first drain disposed on the compound semiconductor stack. The first transistor is a high-voltage switching element. A second transistor is located in a second element region and includes a second gate, a second source and a second drain disposed on the compound semiconductor stack. The second transistor is a low-voltage switching element, the second source is electrically connected to a ground node, and the second drain is electrically connected to the first source. An isolation structure is disposed between the first transistor and the second transistor; as well as A conductive structure is located within the second element region, penetrates the compound semiconductor stack, and electrically connects the semiconductor layer to the second source electrode; The semiconductor layer located in the first element region is not electrically connected to the first source electrode.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor layer located within the first element region is an electrically floating layer or is configured to be electrically connected to the ground node.

3. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor layer located within the first element region is electrically connected to the ground terminal via a sealing ring.

4. The semiconductor device as claimed in claim 3, characterized in that, It also includes another conductive structure located within the first element region and extending through the compound semiconductor stack, wherein the other conductive structure electrically connects the sealing ring to the semiconductor layer.

5. The semiconductor device as claimed in claim 4, characterized in that, The other conductive structure is disposed outside the vertical projection region of the first gate, the first source, and the first drain of the first transistor.

6. The semiconductor device as claimed in claim 1, characterized in that, The first transistor and the second transistor include high electron mobility transistors, the first transistor being the high-voltage switching element of the half-bridge circuit, and the second transistor being the low-voltage switching element of the half-bridge circuit.

7. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor layer located in the first element region and the second source electrode are electrically connected to the ground node.

8. The semiconductor device as claimed in claim 1, characterized in that, The substrate is electrically connected to the ground terminal.

9. The semiconductor device as claimed in claim 1, characterized in that, The substrate, the insulating layer, and the semiconductor layer constitute an insulating layer-surfaced semiconductor substrate.

10. The semiconductor device as claimed in claim 1, characterized in that, The substrate is an insulating substrate.

11. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor layer is a seed layer.

12. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the semiconductor layer is from 5 nanometers to 350 nanometers.

13. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the insulating layer is 1 micrometer to 3 micrometers.

14. The semiconductor device as claimed in claim 1, characterized in that, The substrate includes ceramic, silicon carbide, aluminum nitride, sapphire, or silicon; the insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof; and the semiconductor layer includes silicon or polycrystalline silicon.

15. The semiconductor device as claimed in claim 1, characterized in that, The compound semiconductor stack includes a buffer layer, a high-resistivity layer, a channel layer and a barrier layer, which are sequentially disposed on the semiconductor layer, and the material of the compound semiconductor stack includes a III-V compound semiconductor.

16. The semiconductor device as claimed in claim 15, characterized in that, The first source, the first drain, the second source, and the second drain are disposed on the barrier layer or pass through the barrier layer to the channel layer.

17. The semiconductor device as claimed in claim 15, characterized in that, It also includes a first capping layer disposed between the first gate and the barrier layer, and a second capping layer disposed between the second gate and the barrier layer.

18. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure extends through the compound semiconductor stack and the semiconductor layer, and the bottom surface of the isolation structure is lower than the top surface of the insulating layer, or the bottom surface of the isolation structure and the top surface of the insulating layer are on the same plane.

19. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure is an insulating pillar structure that penetrates the compound semiconductor stack and the semiconductor layer, and surrounds the first transistor and the second transistor.

20. The semiconductor device as claimed in claim 19, characterized in that, It also includes another conductive structure located within the first element region and extending through the compound semiconductor stack, wherein the insulating pillar structure surrounds the other conductive structure and the other conductive structure is electrically connected to a ground terminal.

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