A trench 4H-SiC mosfet device integrated with a channel diode

Abstract

The application belongs to the technical field of power semiconductors, and particularly relates to a trench type 4H-SiC MOSFET device integrated with a channel diode. The MOSFET device of the application has the P-type shielding area to protect the channel and the gate oxide layer when the device is in a blocking state, so as to prevent the device from being broken down in advance and effectively reduce the electric field intensity of the gate oxide layer, thereby making the device of the application have good blocking characteristics and gate oxide layer reliability. The N+ channel area provides a channel diode freewheeling path for the device in reverse, and the channel diode V F is lower and is unipolar conduction, avoids the body diode opening, so that the device has better reverse recovery characteristics and avoids the problem of bipolar degradation.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and particularly relates to a trench type 4H-SiC MOSFET device integrated with a channel diode. BACKGROUND

[0002] SiC material, as a typical representative of the third generation of wide band gap semiconductor materials, has advantages of high critical breakdown field strength, high carrier saturation drift speed, high thermal conductivity, and the like, and has unique advantages in the preparation of high-voltage and high-power semiconductor devices.

[0003] Compared with traditional Si devices, SiC MOS devices can realize low on-resistance, high-speed switching, and high-temperature and high-voltage resistance, and are deeply welcomed in automobiles, industrial equipment, and household consumer electronic devices. Compared with traditional planar MOS devices, SiC trench MOS devices have a more compact cell design and weaken the influence of the JFET region, thereby realizing higher power density and reducing the on-resistance of the device. However, the SiC trench MOS device also has the problem of high forward voltage drop of the body diode and poor reliability of the body diode in operation. Undoubtedly, the external reverse parallel Schottky diode used to provide a new freewheeling path will increase the complexity of the circuit and introduce additional parasitic effects. SUMMARY

[0004] In view of the problems in the prior art, the application provides a trench type 4H-SiC MOSFET device integrated with a channel diode.

[0005] The technical scheme of the application is as follows:

[0006] A trench type 4H-SiC MOSFET device integrated with a channel diode, comprising a drain 1, an N+ substrate 2, an N- epitaxial layer 3, a P-type shielding region 4, an N+ region 5, a P-type base region 6, an N+ channel layer 7, a gate oxide layer 8, a gate 9, and a source 10; wherein the N+ substrate 2 is located on the upper surface of the drain 1, and the N- epitaxial layer 3 is located on the upper surface of the N+ substrate 2; the P-type shielding region 4 is located on the upper layer of the N- epitaxial layer 3, and the upper surface of the N- epitaxial layer 3 between the two P-type shielding regions 4 has the N+ region 5 and the P-type base region 6, wherein the N+ region 5 is located on the upper surface of the P-type base region 6; the gate 9 extends into the N- epitaxial layer 3 from the middle of the N+ region 5 in the vertical direction, sequentially penetrating the N+ region 5 and the P-type base region 6, and the gate oxide layer 8 wraps the gate 9 to isolate the gate 9 from the N+ region 5, the P-type base region 6, and the N- epitaxial layer 3; the N+ channel layer 7 is located between the P-type base region 6 and the gate oxide layer 8; one end of the source 10 is embedded in the P-type shielding region 4, and the other end extends to the upper surface of the N+ region 5 along the upper surface of the P-type shielding region 4.

[0007] Further, the junction depth of the P-type shielding region 4 is greater than the junction depth of the P-type base region 6 and the gate oxide layer 8.

[0008] Further, the junction depth of the gate oxide layer 8 is greater than the junction depth of the P-type base region 6.

[0009] The beneficial effects of the present application are: when the device is in the blocking state, the P-type shielding region protects the channel and the gate oxide layer, preventing the device from breaking down prematurely and effectively reducing the gate oxide layer electric field strength, thereby making the device of the present application have good blocking characteristics and gate oxide layer reliability. The N+ channel region provides a channel diode freewheeling path when the device is reversed, and this channel diode V F is lower and is unipolar conductive, avoiding the opening of the body diode, so that the device has better reverse recovery characteristics and avoids the problem of bipolar degradation. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a structure diagram of a trench-type 4H-SiC MOSFET device integrated with a channel diode. DETAILED DESCRIPTION

[0011] The technical solutions of the present application will be described in detail below in conjunction with the drawings and embodiments:

[0012] Embodiment:

[0013] As Figure 1 shown, the trench-type 4H-SiC MOSFET device integrated with a channel diode provided by the present embodiment includes a drain 1, an N+ substrate 2, an N- epitaxial layer 3, a P-type shielding region 4, an N+ region 5, a P-type base region 6, an N+ channel layer 7, a gate oxide layer 8, a gate 9, and a source 10; wherein the N+ substrate 2 is located on the upper surface of the drain 1, and the N- epitaxial layer 3 is located on the upper surface of the N+ substrate 2; the P-type shielding region 4 is located on the upper layer of the N- epitaxial layer 3 at both ends, and the N- epitaxial layer 3 has the N+ region 5 and the P-type base region 6 on the upper surface between the P-type shielding regions 4 at both sides, wherein the N+ region 5 is located on the upper surface of the P-type base region 6; the gate 9 extends into the N- epitaxial layer 3 from the middle of the N+ region 5 in the vertical direction, sequentially penetrating the N+ region 5 and the P-type base region 6, and the gate oxide layer 8 wraps around the gate 9 to isolate the gate 9 from the N+ region 5, the P-type base region 6, and the N- epitaxial layer 3; the N+ channel layer 7 is located between the P-type base region 6 and the gate oxide layer 8; one end of the source 10 is embedded in the P-type shielding region 4, and the other end extends to the upper surface of the N+ region 5 along the upper surface of the P-type shielding region 4; wherein the junction depth of the P-type shielding region 4 is greater than the junction depth of the P-type base region 6 and the gate oxide layer 8; the junction depth of the gate oxide layer 8 is greater than the junction depth of the P-type base region 6.

[0014] The working principle of the present example is:

[0015] The device of the present application makes the forward current and the third quadrant current of the MOSFET share the same path in opposite directions by integrating a very thin and highly doped N+ channel layer. The device reduces the potential barrier in the channel by heavily doping the N-type channel layer, providing a low potential barrier path, so that the electrons can flow from the drain to the source under the third quadrant working condition, and this process only involves one type of carrier. The diode-like function of the channel diode avoids the bipolar degeneration problem of the body diode. In addition, the channel diode is connected in parallel with the body diode and has a lower on-state voltage drop than the body diode, avoiding the opening of the body diode. Therefore, the device of the present application reduces the switching loss and avoids the bipolar degeneration problem compared with the conventional device.

[0016] In the above embodiment, the drain 1 is formed on the back of the N+ substrate by metal sputtering; the P-type shielding region 4, the N+ region 5, the P-type base region 6 and the N+ channel layer are formed by high-temperature ion implantation; the gate and source trenches are etched by photolithography and etching process; the source 10 is formed by metal sputtering; the gate oxide layer 8 is formed on the surface of the trench by thermal oxidation process; and the gate 9 is formed in the gate oxide layer 8 by polycrystalline silicon deposition.

Claims

1. A trench-type 4H-SiC MOSFET device with an integrated channel diode, characterized in that, The structure includes a drain (1), an N+ substrate (2), an N- epitaxial layer (3), a P-type shielding region (4), an N+ region (5), a P-type base region (6), an N+ channel layer (7), a gate oxide layer (8), a gate (9), and a source (10); wherein the N+ substrate (2) is located on the upper surface of the drain (1), and the N- epitaxial layer (3) is located on the upper surface of the N+ substrate (2); the P-type shielding region (4) is located at both ends of the upper layer of the N-epitaxy layer (3), and the upper surface of the N-epitaxy layer (3) between the two P-type shielding regions (4) has an N+ region (5) and a P-type base region (6), wherein the N+ region (5) is located at the upper surface of the drain (1), the N+ substrate (2), the N- epitaxial layer (3), the P-type shielding region (4), the N+ region (5), the N+ channel layer (7), the gate oxide layer (8), the gate (9), and the source (10); wherein the N+ substrate (2) is located on the upper surface of the drain (1), and the N+ region (5) is located on the upper surface of the drain (1), the N+ epitaxial layer (3), the N+ channel layer (7), the N+ channel layer (8), the gate oxide layer (9), and the source (10); wherein the N+ substrate (2) is located on the upper surface of the drain (1), the N+ channel layer (3), the N+ channel layer (4), the N+ channel layer (5), the N+ channel layer (6), the N+ channel layer (7), the N+ channel layer (8), the gate oxide layer (9), and the source (10). On the upper surface of the P-type base region (6); the gate (9) extends from the middle of the N+ region (5) through the N+ region (5) and the P-type base region (6) in a vertical direction and then into the N-epitaxial layer (3); the gate oxide layer (8) wraps around the gate (9) to isolate the gate (9) from the N+ region (5), the P-type base region (6), and the N-epitaxial layer (3); the N+ channel layer (7) is located between the P-type base region (6) and the gate oxide layer (8); one end of the source (10) is embedded in the P-type shielding region (4), and the other end extends along the upper surface of the P-type shielding region (4) to the upper surface of the N+ region (5).

2. The trench-type 4H-SiC MOSFET device with integrated channel diode according to claim 1, characterized in that, The junction depth of the P-type shielding region (4) is greater than the junction depth of the P-type base region (6) and the gate oxide layer (8).

3. A trench-type 4H-SiC MOSFET device with an integrated channel diode according to claim 1 or 2, characterized in that, The junction depth of the gate oxide layer (8) is greater than the junction depth of the P-type base region (6).

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