Semiconductor device for improving surge resistance of si c mosfet

Abstract

The application discloses a kind of semiconductor devices for improving the surge capacity of SiC MOSFET, it is related to silicon carbide power semiconductor field, including: first cell area, first cell area includes multiple array arranged transistors, transistor includes body diode;First diode region, at least part surrounds first cell area, first diode region includes multiple diodes;Wherein, each diode includes first sub-diode and second sub-diode arranged in parallel;Second cell area, at least part surrounds first diode region, second cell area includes multiple array arranged transistors;Second diode region, at least part surrounds second cell area, and second diode includes multiple diodes.The diode of first diode region and second diode region of the application can reduce the on-voltage drop of the transistor of first cell area and second cell area, reduce junction temperature, also can inhibit current concentration to a certain extent, improve the surge current impact capacity.

Description

Technical Field

[0001] This invention belongs to the field of silicon carbide power semiconductors, and specifically relates to a semiconductor device for improving the surge resistance of SiC MOSFETs. Background Technology

[0002] Silicon carbide (SiC), as a representative material of third-generation semiconductors, has advantages such as a large bandgap, high breakdown electric field, and high electron saturation velocity, making it a promising candidate for applications in high-temperature, high-frequency, and high-power environments.

[0003] In existing technologies, most high-power converter applications require a freewheeling diode to handle reverse current in MOSFET switching devices. However, the parasitic diodes inherent in traditional silicon (Si) MOSFETs are unsuitable for this purpose due to poor reverse recovery characteristics caused by minority carrier storage effects, resulting in significant switching power consumption. In practical applications, fast recovery diodes (FRDs) are typically connected in reverse parallel across the MOSFET source and drain to suppress parasitic body diode conduction and provide a new freewheeling path. However, external FRDs increase circuit module area and introduce additional parasitic parameters. Under large inrush currents, existing devices are prone to damage at the source bond wire connection due to high temperatures, and the metal at the gate bus is also prone to melting.

[0004] Therefore, it is urgent to improve the aforementioned defects in the existing technology. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a semiconductor device that improves the surge resistance of SiC MOSFETs. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a semiconductor device for improving the surge resistance of SiC MOSFETs, comprising:

[0007] The first cell region includes multiple transistors arranged in an array, and the transistors include body diodes;

[0008] A first diode region, at least partially surrounding a first cell region, includes a plurality of diodes; wherein each diode includes a first sub-diode and a second sub-diode arranged in parallel;

[0009] The second cell region at least partially surrounds the first diode region, and the second cell region includes a plurality of transistors arranged in an array;

[0010] The second diode region, at least partially surrounding the second cell region, includes a plurality of diodes; wherein the diodes in the first diode region and the second diode region are used to reduce the voltage drop of the transistors in the first cell region and the second cell region during reverse conduction.

[0011] The beneficial effects of this invention are:

[0012] This invention provides a semiconductor device for improving the surge resistance of SiC MOSFETs. By setting a "U"-shaped panel, diodes are arranged in the first diode region and the second diode region, eliminating reliability risks in the application of SiC MOSFET body diodes and optimizing the surge resistance of SiC MOSFETs. Specifically, multiple diodes are arranged in the first diode region and the second diode region respectively, and each diode includes a first sub-diode and a second sub-diode arranged in parallel. The current is shunted by the parallel connection of the first diode region and the second diode region, which indirectly reduces the surge current of the MOSFET parasitic diode. This allows the diodes in the first diode region and the second diode region to reduce the voltage drop of the transistors in the first cell region and the second cell region during reverse conduction, thereby reducing the junction temperature.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a MOSFET structure in the prior art provided by an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0016] Figure 3 This is another schematic diagram of the structure of the semiconductor device provided in the embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] In the prior art, please refer to Figure 1 As shown, Figure 1 This is a schematic diagram of a MOSFET structure in the prior art provided by the embodiments of the present invention. Typically, a diode is connected to the outside of the MOSFET for current shunting. However, under large surge current, existing devices are prone to damage at the source bonding wire connection due to high temperature. In addition, the metal at the gate bus is also prone to melting.

[0019] In view of this, the present invention provides a semiconductor device for improving the surge resistance of SiC MOSFETs. The first diode region and the second diode region are connected in parallel to shunt the current, thereby indirectly reducing the surge current of the MOSFET parasitic diode. This allows the diodes in the first diode region and the second diode region to reduce the on-state voltage drop of the transistors in the first cell region and the second cell region, and reduce the junction temperature.

[0020] Please refer to Figure 2 as shown Figure 2 which is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. A semiconductor device for improving the surge resistance of a SiC MOSFET provided by the present invention includes:

[0021] A first cell region 10, the first cell region 10 includes a plurality of transistors 50 arranged in an array, and the transistor 50 includes a body diode;

[0022] A first diode region 20, at least partially surrounding the first cell region 10, the first diode region 20 includes a plurality of diodes; wherein, each diode includes a first sub-diode and a second sub-diode arranged in parallel;

[0023] A second cell region 30, at least partially surrounding the first diode region 20, the second cell region 30 includes a plurality of transistors 50 arranged in an array;

[0024] A second diode region 40, at least partially surrounding the second cell region 30, the second diode includes a plurality of diodes; wherein, the diodes in the first diode region 20 and the second diode region 40 are used to reduce the voltage drop when the transistors 50 in the first cell region 10 and the second cell region 30 are reversely conducting.

[0025] Specifically, please continue to refer to Figure 2 as shown. A semiconductor device for improving the surge resistance of a SiC MOSFET provided in this embodiment includes a first cell region 10, a first diode region 20, a second cell region 30 and a second diode region 40. Among them, the first cell region 10 is located in the middle of the chip, the first diode region 20 is arranged around the first cell region 10, the second cell region 30 is arranged around the first diode region 20, and the second diode region 40 is arranged around the second cell region 30, and the entire semiconductor device forms a "hui" - shaped structure; the first cell region 10 and the second cell region 30 include a plurality of transistors 50 arranged in an array, the first diode region 20 and the second diode region 40 include a plurality of diodes, and the diode includes a first sub-diode and a second sub-diode arranged in parallel; it should be noted that the transistor 50 is a silicon carbide field effect transistor (SiC MOSFET).

[0026] In this embodiment, considering that SiC MOSFETs can withstand higher electric fields and have thinner drift regions under the same voltage rating, their body diodes store significantly less charge during forward conduction compared to Si MOSFETs, which helps improve reverse recovery characteristics. These superior reverse recovery characteristics make the body diode a potential replacement for external diodes in converters such as inverters. Although the long-term reliability of SiC MOSFET body diodes has been verified, SiC MOSFETs are easily damaged when subjected to large surge currents with pulse widths on the millisecond scale. Therefore, in this embodiment, a "U"-shaped panel is used, with PiN diodes in the first diode region 20 and the second diode region 40, to eliminate reliability risks associated with SiC MOSFET body diode applications and optimize the SiC MOSFET's performance. The surge resistance of the MOSFET is achieved by setting multiple diodes in the first diode region 20 and the second diode region 40, and each diode includes a first sub-diode and a second sub-diode connected in parallel. The current is shunted by the parallel connection of the first diode region 20 and the second diode region 40, which indirectly reduces the surge current of the MOSFET parasitic diode. This allows the diodes in the first diode region 20 and the second diode region 40 to reduce the on-state voltage drop of the transistor 50 in the first cell region 10 and the second cell region 30, thereby reducing the junction temperature.

[0027] It should be noted that, Figure 2 The illustrated embodiment only schematically shows the positional relationship between the first cell region 10, the first diode region 20, the second cell region 30, and the second diode region 40, and does not represent the actual dimensions. Figure 2 The number of transistors 50 in the first cell region 10 and the second cell region 30 does not represent the actual number. Figure 2 The number of diodes in the first diode region 20 and the second diode region 40 does not represent the actual number.

[0028] It should also be noted that, Figure 2 The embodiment shown only illustrates a schematic diagram of the entire semiconductor device including two cell regions and two diode regions. The number of cell regions and diode regions can also be 3, 4 or 5, and this embodiment does not limit it.

[0029] In an optional embodiment of the present invention, please refer to Figure 3 As shown, Figure 3 This is another schematic diagram of the semiconductor device provided in an embodiment of the present invention, which further includes:

[0030] Drain;

[0031] The N+ substrate is located on one side of the drain.

[0032] The N-drift layer is located on the side of the N+ substrate away from the drain.

[0033] The drain is electrically connected to the metal substrate. The transistor 50 in the first cell region 10, the diode in the first diode region 20, the transistor 50 in the second cell region 30, and the diode in the second diode region 40 share the same drain, N+ substrate, and N-drift layer.

[0034] For details, please continue to see Figure 3 As shown, in this embodiment, the transistor 50 located in the first cell region 10, the diode located in the first diode region 20, the transistor 50 located in the second cell region 30, and the diode located in the second diode region 40 share the same drain, N+ substrate, and N-drift layer. It can also be understood that the drain, N+ substrate, and N-drift layer of the entire device are an integrated structure, which can save process steps and improve manufacturing efficiency.

[0035] In an optional embodiment of the present invention, please continue to refer to Figure 3 As shown, transistor 50 includes:

[0036] The P-well layer is located on the side of the N-drift layer away from the drain. The P-well layer includes a first P-well layer and a second P-well layer that are arranged opposite to each other. The P-well layer is L-shaped.

[0037] The N+ source region is located on the side of the P-well layer away from the drain electrode. The N+ source region includes a first N+ source region and a second N+ source region that are set opposite to each other.

[0038] The P+ source region is located on the side of the P-well layer away from the drain. The P+ source region includes a first P+ source region and a second P+ source region that are arranged opposite to each other. The P+ source region and the N+ source region are arranged in the same layer.

[0039] A gate oxide layer is located on the side of at least a portion of the N+ source region and at least a portion of the P-well layer away from the drain; a gate metal is disposed in the gate oxide layer;

[0040] The source metal is located on the side of at least a portion of the P+ source region, at least a portion of the N+ source region, and the gate oxide layer away from the drain, and the source metal covers the gate oxide layer;

[0041] The source electrode is located on the side of the source metal that faces away from the drain electrode.

[0042] In an optional embodiment of the present invention, please continue to refer to Figure 3 As shown, the diode is a PiN diode, which includes:

[0043] The diode P+ source region is located on the side of the N-drift layer away from the drain. The diode P+ source region includes a first diode P+ source region and a second diode P+ source region that are disposed opposite to each other, forming a first sub-PiN diode and a second sub-PiN diode, respectively.

[0044] The source metal of the diode is located on the side of the P+ source region away from the drain; the source metal of the diode and the P+ source region of the diode are electrically connected through an ohmic contact.

[0045] The diode anode is located on the side of the source metal that is away from the drain.

[0046] For details, please continue to see Figure 3 As shown, in this embodiment, the diode P+ source region includes a first diode P+ source region and a second diode P+ source region disposed opposite to each other. The first diode P+ source region forms a first sub-PiN diode, and the second diode P+ source region forms a second sub-PiN diode; or, the first diode P+ source region forms a second sub-PiN diode, and the second diode P+ source region forms a first sub-PiN diode. In this embodiment, the PiN diodes of the first diode region 20 and the second diode region 40 are connected in parallel, which can more effectively reduce the on-state voltage drop of the transistor 50 in the first cell region 10 and the second cell region 30.

[0047] It should be noted that the diode in this embodiment can also be a Schottky diode.

[0048] In an optional embodiment of the present invention, it further includes:

[0049] The source pad is located on the side of the source of the transistor and the source of the diode away from the drain, and the source pad is located in the first cell region 10; the source pad is electrically connected to the source of the transistor and the anode of the diode through the source bonding wire.

[0050] Specifically, this embodiment also includes source pads located in the first cell region 10. It can be understood that the source pads are concentrated in the first cell region 10, which will cause current concentration in the source pads. However, this embodiment adopts a "U"-shaped structure, and the diodes in the first diode region 20 and the second diode region 40 can effectively suppress the current concentration in the source pads and reduce the failure risk of thermal runaway and breakdown of the source bonding wire chip.

[0051] It should be noted that the large surge current is input from the source pad, transmitted through the source bonding wire to the source of the transistor and the anode of the diode, turning on the transistor 50 and the diode. The diodes in the first diode region 20 and the second diode region 40 can effectively reduce the on-state voltage drop of the source and drain of the transistors in the first cell region 10 and the second cell region 30.

[0052] In an optional embodiment of the present invention, the number of source bonding wires is set to 2 to 6, and the width of the source bonding wire is 50 μm to 500 μm. Optionally, the number of source bonding wires can be 3, 4, or 5, and the width of the source bonding wire can be 100 μm, 200 μm, 300 μm, or 400 μm.

[0053] In an optional embodiment of the present invention, please continue to refer to Figure 2 As shown, the first diode region 20 is disposed around the first cell region 10, the second cell region 30 is disposed around the first diode region 20, and the second diode region 40 is disposed around the second cell region 30.

[0054] Specifically, please continue to refer to Figure 2 As shown, in this embodiment, the cell region and the diode region in the semiconductor device form a "hui" - shaped structure.

[0055] In an optional embodiment of the present invention, along the first direction, the size of the diode P + source region is 10 μm to 35 μm; along the second direction, the size of the diode P + source region is 0.7 μm to 1.5 μm, and the doping concentration of the diode P + source region is 1×10 17 cm -3 ~1×10 19 cm -3 ; wherein, the first direction intersects with the second direction.

[0056] Specifically, please continue to refer to Figure 3 As shown, in this embodiment, along the first direction, the size of the diode P + source region can be 20 μm, 25 μm, or 30 μm; along the second direction, the size of the diode P + source region can be 0.8 μm, 1 μm, 1.2 μm, or 1.5 μm; optionally, the first direction is perpendicular to the second direction.

[0057] In an optional embodiment of the present invention, to ensure the blocking ability of the device, along the second direction, the size of the N - drift layer is 10 μm to 15 μm, and the doping concentration of the N - drift layer is 1×10 15 cm -3 ~6×10 15 cm -3 .

[0058] Specifically, please continue to refer to Figure 3As shown, in this embodiment, the size of the N-drift layer along the second direction can be 12μm, 13μm, or 14μm.

[0059] In an optional embodiment of the present invention, the size of the first cell region 10 and the second cell region 30 along the second direction is 50 μm to 1000 μm. Optionally, the size of the first cell region 10 and the second cell region 30 can be 50 μm, 100 μm, 500 μm or 800 μm.

[0060] In an optional embodiment of the present invention, the dimensions of the first diode region 20 and the second diode region 40 along the second direction are 30μm to 500μm. Optionally, the dimensions of the first diode region 20 and the second diode region 40 can be 50μm, 200μm or 300μm.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A semiconductor device for improving the surge resistance of SiC MOSFETs, characterized in that, include: A first cell region, comprising a plurality of transistors arranged in an array, wherein the transistors include body diodes; A first diode region, at least partially surrounding the first cell region, the first diode region comprising a plurality of diodes; wherein each of the diodes comprises a first sub-diode and a second sub-diode arranged in parallel; The second cell region at least partially surrounds the first diode region, and the second cell region includes a plurality of transistors arranged in an array; A second diode region, at least partially surrounding the second cell region, the second diode comprising a plurality of diodes; wherein the diodes in the first diode region and the second diode region are used to reduce the voltage drop of the transistors in the first cell region and the second cell region during reverse conduction; Also includes: Drain; An N+ substrate is located on one side of the drain electrode; The N- drift layer is located on the side of the N+ substrate away from the drain electrode; The drain is electrically connected to the metal substrate, and the transistor in the first cell region, the diode in the first diode region, the transistor in the second cell region, and the diode in the second diode region share the same drain, the N+ substrate, and the N- drift layer. The transistor includes: The P-well layer is located on the side of the N-drift layer away from the drain electrode. The P-well layer includes a first P-well layer and a second P-well layer disposed opposite to each other. The P-well layer is L-shaped. The N+ source region is located on the side of the P-well layer away from the drain. The N+ source region includes a first N+ source region and a second N+ source region that are disposed opposite to each other. The P+ source region is located on the side of the P-well layer away from the drain. The P+ source region includes a first P+ source region and a second P+ source region disposed opposite to each other. The P+ source region is disposed on the same layer as the N+ source region. A gate oxide layer is located on the side of at least a portion of the N+ source region and at least a portion of the P-well layer opposite to the drain; a gate metal is disposed in the gate oxide layer; The source metal is located on the side of the at least part of the P+ source region, the at least part of the N+ source region, and the gate oxide layer away from the drain, and the source metal covers the gate oxide layer; The source electrode is located on the side of the source electrode metal that is away from the drain electrode; The diode is a PiN diode, and the PiN diode includes: The diode P+ source region is located on the side of the N-drift layer away from the drain. The diode P+ source region includes a first diode P+ source region and a second diode P+ source region disposed opposite to each other, forming a first sub-PiN diode and a second sub-PiN diode, respectively. The source metal of the diode is located on the side of the P+ source region of the diode away from the drain; the source metal of the diode and the P+ source region of the diode are electrically connected through an ohmic contact. The diode anode is located on the side of the diode source metal that is away from the drain. Along the first direction, the size of the P+ source region of the diode is 10 μm to 35 μm; along the second direction, the size of the P+ source region of the diode is 0.7 μm to 1.5 μm, and the doping concentration of the P+ source region of the diode is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 Wherein, the first direction intersects with the second direction.

2. The semiconductor device for improving the surge resistance of SiC MOSFETs according to claim 1, characterized in that, Also includes: The source pad is located on the side of the source of the transistor and the anode of the diode away from the drain, and the source pad is located in the first cell region; The source pad is electrically connected to the source of the transistor and the anode of the diode via a source bonding wire.

3. The semiconductor device for improving the surge resistance of SiC MOSFETs according to claim 1, characterized in that, The first diode region is arranged around the first cell region, the second cell region is arranged around the first diode region, and the second diode region is arranged around the second cell region.

4. The semiconductor device for improving the surge resistance of SiC MOSFETs according to claim 1, characterized in that, Along the second direction, the size of the N-drift layer is 10 μm to 15 μm, and the doping concentration of the N-drift layer is 1 × 10⁻⁶. 15 cm -3 ~6×10 15 cm -3 .

5. The semiconductor device for improving the surge resistance of SiC MOSFETs according to claim 1, characterized in that, The transistor is a silicon carbide field-effect transistor.

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