A SOI MOS device and its preparation method

Abstract

The present invention provides an SOI MOS device and a method for fabricating the same. The SOI MOS device comprises: a substrate, a bias electrode structure, a gate structure, a source region, a drain region, a gate metal layer, a source metal layer, and a drain metal layer, wherein the substrate comprises a substrate, a buried oxide layer, an active layer, a cavity, and a cavity opening disposed at the top of the cavity; the bias electrode structure comprises a dielectric layer covering the inner wall of the cavity, a conductive layer filling the conductive layer, and a bias electrode electrically connected to the conductive layer, wherein the dielectric layer wraps the conductive layer; the gate structure comprises a gate and a gate dielectric layer; the source region and the drain region are respectively located in the active layer on either side of the gate structure; and the gate metal layer, the source metal layer, and the drain metal layer are electrically connected to the gate, the source region, and the drain region, respectively. The SOI MOS device and method for fabricating the same reduce the parasitic capacitance of the SOI MOS device, reduce leakage current, and improve device performance by providing the bias electrode structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a SOI MOS device and a preparation method thereof. Background Art

[0002] Fully depleted silicon on insulator (FDSOI) generally uses the technology of back gate bias to adjust the threshold voltage of the device, such as Figure 1 As shown in the figure, it is a schematic diagram of the structure of FDSOI, including substrate 01, buried oxide layer 02 and active layer 03. After applying bias, the working state of the device can be flexibly adjusted to meet the application requirements of different scenarios such as low power consumption / high performance. However, since the buried oxide layer (BOX) of FDSOI is relatively thin, generally around 20nm, the plasticity of the oxide layer in the high-temperature bonding process is reduced. The silicon-on-insulator (SOI) substrate containing an ultra-thin layer of BOX poses a great challenge to the substrate preparation process, and the cost of the substrate is also high. In addition, since the back gate bias must be applied to the device by structures such as P-type well (Pwell) and N-type well (Nwell), there are large parasitic capacitances and leakage currents between structures such as Pwell and Nwell and the silicon substrate, and large mutual interference is easily generated between Pwell and Nwell, making the back gate bias unstable and the working state of the device unstable. As shown in the figure, the working state of the device is relatively low. Figure 2 and Figure 3 As shown in the figures, there are schematic diagrams of the structure of an SOI metal oxide semiconductor field effect transistor (MOS) device and a schematic diagram of the structure of an inversion well SOI MOS device, including a substrate 01, a buried oxide layer 02, an active layer 03, an N well 011, a P well 012, a P-type doped region 031, an N-type doped region 032, a gate 04, a gate dielectric layer 05, an isolation structure 06, a channel 07 and a sidewall 08. Although the buried oxide layer of FDSOI can be thinned to 10-25nm, it is still a relatively thick back gate dielectric, which is not conducive to the control of the back gate. In addition, due to process limitations, it is difficult to further thin the buried oxide layer using the existing FDSOI substrate preparation process, which in turn limits the control capability of the back gate.

[0003] Therefore, there is an urgent need to find a SOIMOS device with strong gate structure control capability and reduced parasitic capacitance and leakage current of the device. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a SOI MOS device and a method for manufacturing the same, so as to solve the problems of poor gate structure controllability, large parasitic capacitance and leakage current, and severe interference between different devices in the prior art SOI MOS devices.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a SOI MOS device, comprising:

[0006] A base, comprising a substrate, a buried oxide layer, an active layer, and a cavity stacked in sequence, wherein the cavity is embedded in the base and a top of the cavity is spaced a preset distance from an upper surface of the active layer, and the top of the cavity is provided with at least one cavity opening communicating with the outside;

[0007] a bias electrode structure comprising a dielectric layer covering an inner wall of the cavity, a conductive layer filling the cavity, and a bias electrode electrically connected to the conductive layer, wherein the dielectric layer wraps the conductive layer;

[0008] a gate structure comprising a gate and a gate dielectric layer stacked in sequence, wherein the gate structure is located above the cavity, and a preset distance is separated from the cavity opening;

[0009] a source region and a drain region, respectively located in the active layer on both sides of the gate structure along the X direction;

[0010] A gate metal layer, a source metal layer and a drain metal layer, wherein the gate metal layer is electrically connected to the gate, the source metal layer is electrically connected to the source region, and the drain metal layer is electrically connected to the drain region.

[0011] Optionally, a doping region is provided in the active layer between the bias electrode structure and the gate structure, and a doping type of the doping region is the same as or opposite to a doping type of the active layer.

[0012] Optionally, the doping type of the doping region is opposite to the doping type of the active layer, and the SOI MOS device is provided with a body contact electrode electrically connected to the doping region.

[0013] Optionally, a trench penetrating the gate dielectric layer and the active layer is further provided in the gap between the gate structure and the bias electrode structure.

[0014] Optionally, an isolation layer is provided in the bias electrode structure, covering the sidewalls of the conductive layer protruding from the upper surface of the active layer.

[0015] Optionally, at least one cavity extension portion is further provided in the base, and the cavity extension portion is communicated with the cavity.

[0016] Optionally, the gate is a metal electrode, and the gate dielectric layer is a high-K dielectric layer.

[0017] The present invention also provides a method for preparing a SOI MOS device, which is characterized by comprising the following steps:

[0018] A substrate is provided, comprising a substrate, a buried oxide layer, an active layer, and a cavity stacked in sequence, wherein the cavity is embedded in the substrate and a top of the cavity is spaced a predetermined distance from an upper surface of the active layer, and at least two cavity openings communicating with the outside are formed at the top of the cavity;

[0019] forming a bias electrode structure in the cavity, the bias electrode structure comprising a dielectric layer covering an inner wall of the cavity, a conductive layer filling the cavity, and a bias electrode electrically connected to the conductive layer, wherein the dielectric layer wraps the conductive layer;

[0020] forming a gate structure above the cavity, the gate structure comprising a gate and a gate dielectric layer stacked in sequence, and a preset distance between the gate structure and the cavity opening;

[0021] forming a source region and a drain region in the active layer on both sides of the gate structure along the X direction;

[0022] A gate metal layer electrically connected to the gate is formed, a source metal layer electrically connected to the source region is formed, and a drain metal layer electrically connected to the surface of the drain region is formed to obtain an SOI MOS device.

[0023] Optionally, after forming the dielectric layer and before forming the conductive layer, the method further includes forming a doped region in the active layer at the edge of the cavity opening above the cavity, wherein the doping type of the doped region is opposite to the doping type of the active layer.

[0024] Optionally, the doping type of the doping region is opposite to the doping type of the active layer, and forming the source metal layer also includes forming a body contact electrode electrically connected to the doping region.

[0025] Optionally, after forming the gate structure and before forming the source metal layer, the method further includes forming a trench penetrating the gate dielectric layer and the active layer in a gap between the gate structure and the bias electrode structure.

[0026] Optionally, a cavity extension portion communicating with the cavity is further provided in the base.

[0027] As described above, the SOI MOS device and the preparation method thereof of the present invention have the following beneficial effects: the SOI MOS device of the present invention reduces the conductive channel area in the active layer area controlled by the gate structure by providing the cavity and the bias electrode structure filling the cavity in the substrate, thereby enhancing the control capability of the gate structure, reducing the leakage current of the device, improving the performance of the device, and reducing the parasitic capacitance of the device; the bias electrode structure cooperates with the gate structure to reduce the influence of the substrate on the device, thereby reducing the mutual interference between different devices; by applying different voltages to the bias electrode structure, the threshold voltage of the SOI MOS device is dynamically adjusted; by providing the doping region with a doping type opposite to that of the active layer in the active layer, a PN junction is formed between the doping region and the active layer, further reducing the control range of the gate, increasing the control capability of the gate, reducing the leakage current, and by providing the doping region with a doping type opposite to that of the active layer in the SOI The body contact electrode electrically connected to the doped region is provided in the MOS device, which can further reduce the area of ​​the gate structure control region and thereby reduce the leakage current of the device; by forming a groove penetrating the gate dielectric layer and the active layer in the gap between the gate structure and the bias electrode structure, the conductive channel region in the active layer below the gate structure is isolated from the active layer region between the groove and the bias electrode structure, further reducing the control range of the gate structure and reducing the leakage current of the device; by providing a cavity extension portion in the substrate and providing the bias electrode electrically connected to the conductive layer in the cavity extension portion, the electric field distribution in the conductive layer is made more uniform, further reducing the parasitic capacitance of the device, and having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of the FDSOI structure.

[0029] Figure 2 Shown is a schematic structural diagram of an SOI MOS device.

[0030] Figure 3 Schematic diagram of the structure of a SOI MOS device showing an inversion well.

[0031] Figure 4 FIG. 1 is a schematic cross-sectional view of the SOI MOS device of the present invention along the X direction.

[0032] Figure 5 It is a schematic cross-sectional view of the SOI MOS device of the present invention along the Y direction.

[0033] Figure 6 Shown is a top view of the SOI MOS device of the present invention.

[0034] Figure 7 It is a schematic structural diagram of a substrate of the SOI MOS device of the present invention.

[0035] Figure 8 Another structural schematic diagram of the substrate of the SOI MOS device of the present invention is shown.

[0036] Figure 9 It is a schematic diagram showing a third structure of the substrate of the SOI MOS device of the present invention.

[0037] Figure 10 It shows a fourth structural schematic diagram of the substrate of the SOI MOS device of the present invention.

[0038] Figure 11 It is a schematic diagram showing a fifth structure of the substrate of the SOI MOS device of the present invention.

[0039] Figure 12 It shows a sixth structural schematic diagram of the substrate of the SOI MOS device of the present invention.

[0040] Figure 13 It shows a seventh structural schematic diagram of the substrate of the SOI MOS device of the present invention.

[0041] Figure 14 It is a schematic diagram showing an eighth structural embodiment of the substrate of the SOI MOS device of the present invention.

[0042] Figure 15 It shows a ninth structural schematic diagram of the substrate of the SOI MOS device of the present invention.

[0043] Figure 16 It is a tenth structural schematic diagram of the substrate of the SOI MOS device of the present invention.

[0044] Figure 17 Shown is a process flow chart of a method for preparing a SOI MOS device of the present invention.

[0045] Figure 18 A top view of a substrate showing a fourth structure of the SOI MOS device of the present invention is shown.

[0046] Figure 19 FIG. 1 is a schematic cross-sectional view of a substrate along the X direction showing a fourth structure of the SOI MOS device of the present invention.

[0047] Figure 20 FIG. 1 is a schematic cross-sectional view of a substrate along the Y direction showing a fourth structure of the SOI MOS device of the present invention.

[0048] Figure 21It is a schematic cross-sectional view of the substrate along the Y direction after a cavity opening is formed in the SOI MOS device of the present invention.

[0049] Figure 22 FIG. 1 is a top view of a substrate after a cavity opening is formed in the SOI MOS device of the present invention.

[0050] Figure 23 It is a schematic cross-sectional view along the X direction of the SOI MOS device after forming the bias electrode structure and the gate structure of the present invention.

[0051] Figure 24 It is a schematic cross-sectional view along the Y direction of the SOI MOS device after forming the bias electrode structure and the gate structure of the present invention.

[0052] Figure 25 It shows a top view of the SOI MOS device of the present invention after forming the bias electrode structure and the gate structure.

[0053] Figure 26 It is a schematic cross-sectional view along the X direction showing a doped region in the SOI MOS device of the present invention.

[0054] Figure 27 FIG. 1 is a top view of the SOI MOS device of the present invention after forming the doped regions.

[0055] Figure 28 It is a schematic cross-sectional view along the Y direction of the SOI MOS device after the doping region is formed according to the present invention.

[0056] Figure 29 It is a schematic cross-sectional view along the Y direction showing a trench provided in the SOI MOS device of the present invention.

[0057] Figure 30 A top view of a substrate provided with a cavity extension of the SOI MOS device of the present invention is shown.

[0058] Figure 31 FIG. 1 is a top view of the SOI MOS device of the present invention after a cavity opening is formed in a substrate having a cavity extension.

[0059] Figure 32 The figure shows a top view of a body contact electrode provided in the SOI MOS device of the present invention.

[0060] Figure 33 FIG. 1 is a schematic cross-sectional view along the X direction showing a portion of the SOI MOS device provided with a body contact electrode according to the present invention.

[0061] Figure 34The figure shows an SEM image of a SOI MOS device provided with a body contact electrode according to the present invention.

[0062] Figure 35 Display as Figure 34 An enlarged view of the dotted box part.

[0063] Component number description

[0064] 01 substrate, 02 buried oxide layer, 03 active layer, 011N well, 012P well, 031P-type doped region, 032N-type doped region, 04 gate, 05 gate dielectric layer, 06 isolation structure, 07 channel, 08 sidewall, 1 base, 11 substrate, 12 buried oxide layer, 13 active layer, 14 cavity, 15 cavity mouth, 16 doped region, 2 bias electrode structure, 21 dielectric layer, 22 conductive layer, 23 bias electrode, 24 isolation layer, 3 gate structure, 31 gate, 32 gate dielectric layer, 33 sidewall, 4 source region, 5 drain region, 61 gate-source metal layer, 62 source metal layer, 63 drain metal layer, 7 trench, 8 cavity extension, 9 body contact electrode. DETAILED DESCRIPTION

[0065] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0066] See also Figures 1 to 35 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0067] Example 1

[0068] This embodiment provides a SOI MOS device, such as Figure 4-6, which are respectively a cross-sectional schematic diagram of the SOI MOS device along the X direction, a cross-sectional schematic diagram along the Y direction, and a top view (the X direction and the Y direction are perpendicular to each other), the SOI MOS device includes: a substrate 1, a bias electrode structure 2, a gate structure 3, a source region 4, a drain region 5, a gate metal layer 61, a source metal layer 62, and a drain metal layer 63, wherein the substrate 1 includes a substrate 11, a buried oxide layer 12, an active layer 13, and a cavity 14 located below the active layer 13, the cavity 14 is embedded in the substrate 1, and the top of the cavity 14 is spaced a preset distance from the upper surface of the active layer 13, and the top of the cavity 14 is provided with at least one cavity opening 15 connected to the outside; the bias electrode structure 2 includes a dielectric layer 21 covering the inner wall of the cavity 14, a conductive layer 22 filling the cavity 14, and a conductive layer 23 connected to the conductive layer 13. 22 is electrically connected to the bias electrode 23, the dielectric layer 21 wraps the conductive layer 22; the gate structure 3 includes a gate 31 and a gate dielectric layer 32 stacked in sequence, the gate structure 3 is located above the cavity 14, and the gate structure 3 is separated from the cavity opening 15 by a preset distance; the source region 4 and the drain region 5 are respectively located in the active layer 13 on both sides of the gate structure 3 along the X direction; the gate metal layer 61, the source metal layer 62 and the drain metal layer 63, the gate metal layer 61 is electrically connected to the gate 31, the source metal layer 62 is electrically connected to the source region 4, and the drain metal layer 63 is electrically connected to the drain region 5.

[0069] Specifically, the substrate 11 is made of silicon, carbon silicon, germanium silicon or other suitable materials.

[0070] Specifically, under the condition that the performance of the device is satisfied, the shape, transverse cross-sectional dimensions and thickness of the substrate 11 can be selected according to actual conditions and are not limited here.

[0071] Specifically, the doping type of the substrate 11 includes at least one of P-type doping and N-type doping.

[0072] Specifically, the buried oxide layer 12 is made of silicon dioxide or other suitable dielectric materials.

[0073] Specifically, under the condition that the performance of the device is satisfied, the shape, transverse cross-sectional dimensions and thickness of the buried oxide layer 12 can be selected according to actual conditions and are not limited here.

[0074] Specifically, the active layer 13 is made of silicon, carbon silicon, germanium silicon or other suitable semiconductor materials.

[0075] Specifically, under the condition that the performance of the device is satisfied, the shape, transverse cross-sectional dimensions and thickness of the active layer 13 can be selected according to actual conditions and are not limited here.

[0076] Specifically, such as Figure 7-16 As shown, there are respectively a schematic diagram of a structure of the substrate 1, another schematic diagram of a structure of the substrate 1, a schematic diagram of a third structure of the substrate 1, a schematic diagram of a fourth structure of the substrate 1, a schematic diagram of a fifth structure of the substrate 1, a schematic diagram of a sixth structure of the substrate 1, a schematic diagram of a seventh structure of the substrate 1, a schematic diagram of a eighth structure of the substrate 1, a schematic diagram of a ninth structure of the substrate 1, and a schematic diagram of a tenth structure of the substrate 1. Under the condition that the performance of the SOI MOS device is met, the position of the cavity 14 can be selected according to actual conditions and is not limited here. For example, the upper surface of the cavity 14 can be located in the active layer 13, and the lower surface of the cavity 14 coincides with the lower surface of the active layer 13 (refer to Figure 7 ); The upper surface of the cavity 14 may be located in the active layer 13, and the lower surface of the cavity 14 is located in the buried oxide layer 12 (reference Figure 8 ); The upper surface of the cavity 14 may be located in the active layer 13, and the lower surface of the cavity 14 coincides with the lower surface of the buried oxide layer 12 (reference Figure 9 ); The upper surface of the cavity 14 may coincide with the lower surface of the active layer 13, and the lower surface of the cavity 14 is located in the buried oxide layer 12 (reference Figure 10 ); The upper surface of the cavity 14 may coincide with the lower surface of the active layer 13, and the lower surface of the cavity 14 may coincide with the lower surface of the buried oxide layer 12 (reference Figure 11 ); It is also possible that the upper surface of the cavity 14 coincides with the lower surface of the active layer 13, and the lower surface of the cavity 14 is located in the substrate 11 (reference Figure 12 ); it is also possible that the upper surface and the lower surface of the cavity 14 are both located in the buried oxide layer 12 (reference Figure 13 ); The upper surface of the cavity 14 may be located in the buried oxide layer 12, and the lower surface of the cavity 14 is located in the substrate 11 (reference Figure 14 ); The upper surface of the cavity 14 may be located in the buried oxide layer 12, and the lower surface of the cavity 14 coincides with the lower surface of the buried oxide layer 12 (reference Figure 15 ); The upper surface of the cavity 14 may coincide with the lower surface of the buried oxide layer 12, and the lower surface of the cavity 14 is located in the substrate 11 (reference Figure 16 ).

[0077] While satisfying the performance of the SOI MOS device, the distance between the top of the cavity 14 and the upper surface of the active layer 13 can be selected according to actual conditions and is not limited here. Specifically, while satisfying the performance of the SOI MOS device, the number, size, and cross-sectional shape of the cavities 14 can be selected according to actual conditions and are not limited here.

[0078] Specifically, the bias electrode structure 2 covers the sidewalls and bottom surface of the conductive channel region in the active layer 13 controlled by the gate 31 along the Y direction.

[0079] Specifically, under the condition that the performance of the SOI MOS device is met, the size and cross-sectional shape of the cavity opening 15 can be selected according to actual conditions and are not limited here.

[0080] Specifically, the conductive layer 22 is made of polysilicon or other suitable conductive materials.

[0081] Specifically, under the condition that the withstand voltage performance of the SOI MOS device is met, the thickness of the dielectric layer 21 can be selected according to actual conditions and is not limited here.

[0082] Specifically, when the performance of the SOI MOS device is met, the material of the bias electrode 23 includes one of titanium, titanium nitride, silver, gold, copper, tungsten, platinum and aluminum, and may also be other suitable conductive materials.

[0083] Specifically, the work function of the conductive layer 22 is related to the inherent properties of the material constituting the conductive layer 22 , and the work function of the conductive layer 22 can be adjusted by adjusting the growth material and the doping ion type.

[0084] As an example, the bias electrode structure 2 is provided with an isolation layer 24 covering the sidewalls of the conductive layer 22 protruding from the upper surface of the active layer 13 to achieve electrical insulation between electrodes.

[0085] Specifically, while satisfying the performance requirements of the SOI MOS device, the shape, size, and thickness of the isolation layer 24 can be selected based on actual conditions and are not limited herein. The thickness of the isolation layer herein refers to the distance between the sidewall of the isolation layer 24 away from the conductive layer 22 and the sidewall of the conductive layer 22.

[0086] Specifically, the isolation layer 24 is made of silicon oxide, silicon nitride or other suitable dielectric materials.

[0087] Specifically, the gate 31 is made of polysilicon or other suitable semiconductor materials.

[0088] Specifically, the gate dielectric layer 32 is made of silicon oxide, silicon nitride, or other suitable dielectric materials.

[0089] Specifically, while meeting the performance of the SOI MOS device, the size of the gate 31 can be selected according to actual conditions and is not limited here; the thickness of the gate dielectric layer 32 can be selected according to actual conditions and is not limited here.

[0090] Specifically, the gate structure 3 further includes a sidewall 33 covering the sidewall of the gate 31 .

[0091] Specifically, the sidewall spacer 33 is made of silicon oxide, silicon nitride or other suitable materials.

[0092] Specifically, under the condition that the performance of the device is met, the shape and size of the sidewall 33 can be selected according to actual conditions and are not limited here.

[0093] Specifically, while meeting the performance requirements of the SOI MOS device, the distance between the sidewalls of the gate structure 3 and the sidewalls of the bias electrode structure 2 can be selected based on actual conditions and is not limited herein. The sidewalls of the bias electrode structure 2 herein refer to the side surfaces of the portion of the conductive layer 22 that protrudes from the upper surface of the active layer 13.

[0094] Specifically, the provision of the sidewall 33 can ensure the insulation between the gate structure 3 and the bias electrode structure 2 , thereby ensuring the withstand voltage performance of the SOI MOS device.

[0095] Specifically, under the condition that the device performance is satisfied and the source region 4 can form an ohmic contact with the source metal layer 62 , the doping ion concentration and size of the source region 4 can be selected according to actual conditions and are not limited here.

[0096] Specifically, under the condition that the device performance is satisfied and the drain region 5 can form an ohmic contact with the drain metal layer 63 , the doping ion concentration and size of the drain region 5 can be selected according to actual conditions and are not limited here.

[0097] Specifically, the doping type of the source region 4 is the same as the doping type of the drain region 5 and the active layer 13 .

[0098] Specifically, the material of the gate metal layer 61 includes titanium, titanium nitride, silver, gold, copper, tungsten, platinum and aluminum or other suitable conductive materials; the material of the source metal layer 62 includes titanium, titanium nitride, silver, gold, copper, tungsten, platinum and aluminum or other suitable conductive materials; the material of the drain metal layer 63 includes titanium, titanium nitride, silver, gold, copper, tungsten, platinum and aluminum or other suitable conductive materials.

[0099] Specifically, by providing the cavity 14 and the independent bias electrode structure 2 filling the cavity 14 , the parasitic capacitance of the SOI MOS device is reduced, and by applying different voltages to the bias electrode structure 2 , the threshold voltage of the SOI MOS device can be dynamically adjusted.

[0100] Specifically, the bias electrode structure 2 reduces the Y-direction size of the active layer 13 area controlled by the gate structure 3, thereby enhancing the control capability of the gate structure 3, reducing leakage current, and improving the performance of the SOI MOS device. In addition, the gate structure 3 and the bias electrode structure 2 cooperate with each other to control the operation of the SOI MOS device, thereby weakening the influence of the substrate 11 on the device and reducing mutual interference between different devices.

[0101] The SOI MOS device of this embodiment utilizes an SOI having the cavity 14 as the substrate 1, fills the cavity 1 with the bias electrode structure 2, and isolates the bias electrode structure 2 from the substrate 1 by the dielectric layer 21. This reduces the parasitic capacitance of the SOI MOS device. Furthermore, due to the provision of the cavity opening 15, the area of ​​the conductive channel region in the active layer 13 controlled by the gate structure 3 is reduced, thereby enhancing the control capability of the gate structure 3, reducing leakage current, and improving the performance of the SOI MOS device. Furthermore, the gate structure 3 and the bias electrode structure 2 cooperate with each other to weaken the influence of the substrate 11 on the device and reduce mutual interference between different devices. Furthermore, by applying different voltages to the bias electrode structure 2, the threshold voltage of the SOI MOS device can be dynamically adjusted.

[0102] Example 2

[0103] This embodiment provides a method for preparing a SOI MOS device, such as Figure 17 FIG. 1 is a process flow chart of a method for preparing a SOI MOS device, comprising the following steps:

[0104] S1: providing a substrate, the substrate comprising a substrate, a buried oxide layer, an active layer, and a cavity located below the active layer, the cavity being embedded in the substrate and a top of the cavity being spaced a preset distance from an upper surface of the active layer, and at least one cavity opening communicating with the outside being formed at the top of the cavity;

[0105] S2: forming a bias electrode structure in the cavity, wherein the bias electrode structure includes a dielectric layer covering an inner wall of the cavity, a conductive layer filling the cavity, and a bias electrode electrically connected to the conductive layer, wherein the dielectric layer wraps the conductive layer;

[0106] S3: forming a gate structure above the cavity, wherein the gate structure includes a gate and a gate dielectric layer stacked in sequence, and a preset distance is spaced between the gate structure and the cavity opening;

[0107] S4: forming a source region and a drain region in the active layer on both sides of the gate structure along the X direction;

[0108] S5: forming a gate metal layer electrically connected to the gate structure, forming a source metal layer electrically connected to the source region, and forming a drain metal layer electrically connected to the surface of the drain region to obtain an SOI MOS device.

[0109] For details, please refer to Figure 18-22 , perform step S1, provide a base 1, the base 1 includes a substrate 11, a buried oxide layer 12, an active layer 13 and a cavity 14 located below the active layer 13 stacked in sequence, the cavity 14 is embedded in the base and the top of the cavity 14 is spaced a preset distance from the upper surface of the active layer 13, and at least one cavity opening 15 connected to the outside is formed at the top of the cavity 14.

[0110] Specifically, such as Figure 18-20 As shown, they are respectively a top view of the substrate 1 of the fourth structure, a cross-sectional schematic diagram of the substrate 1 of the fourth structure along the X direction, and a cross-sectional schematic diagram of the substrate 1 of the fourth structure along the Y direction (wherein Figure 18 The dotted box in the figure represents the cavity 14. Under the condition that the performance of the SOI MOS device is met, the number, size and cross-sectional shape of the cavity 14 can be selected according to actual conditions and are not limited here.

[0111] Specifically, before forming the cavity opening 15 , a step of pre-doping the active layer 13 is further included to adjust the threshold voltage of the SOI MOS device.

[0112] Specifically, the method of pre-doping the active layer 13 includes ion implantation or other suitable methods.

[0113] Specifically, under the condition that the performance of the SOI MOS device is satisfied, the dosage and energy of the pre-doping ion implantation in the active layer 13 can be selected according to actual conditions and are not limited here.

[0114] Specifically, such as Figure 21-22 As shown, the cross-sectional view of the substrate 1 along the Y direction after the cavity opening 15 is formed and the top view of the substrate 1 after the cavity opening 15 is formed (wherein Figure 22The dotted box in the figure represents the cavity 14), and forming the cavity opening 15 includes the following steps: forming a first photoresist layer covering the upper surface of the active layer 13; patterning the first photoresist layer and etching the active layer 13 based on the patterned first photoresist layer to expose the cavity 14, thereby forming the cavity opening 15 at the top of the cavity 14.

[0115] Specifically, the method of forming the first photoresist layer and patterning the first photoresist layer is a commonly used photoresist forming and developing method, which will not be described in detail here.

[0116] Specifically, execute steps S2-S3, as shown in FIG. Figure 23-25 As shown, there are respectively a cross-sectional schematic diagram along the X direction after the bias electrode structure 2 and the gate structure 3 are formed, a cross-sectional schematic diagram along the Y direction after the bias electrode structure 2 and the gate structure 3 are formed, and a top view after the bias electrode structure 2 and the gate structure 3 are formed. The bias electrode structure 2 is formed in the cavity 14, and the bias electrode structure 2 includes a dielectric layer 21 covering the inner wall of the cavity 14, a conductive layer 22 filling the cavity 14, and a bias electrode 23 electrically connected to the conductive layer 22, and the dielectric layer 21 wraps the conductive layer 22; a gate structure 3 is formed above the cavity 14, and the gate structure 3 includes a gate 31 and a gate dielectric layer 32 stacked in sequence, and the gate structure 3 is spaced a preset distance from the cavity opening 15.

[0117] Specifically, the method for forming the dielectric layer 21 includes thermal oxidation or other suitable methods; the method for forming the conductive layer 22 includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method for forming the bias electrode 23 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0118] Specifically, after forming the conductive layer 22 and before forming the source metal layer 62 , the method further includes forming an isolation layer 24 in the bias electrode structure 2 to cover the sidewalls of the conductive layer 22 protruding from the cavity 14 .

[0119] Specifically, the isolation layer 24 is formed by dry etching, wet etching or other suitable methods.

[0120] Specifically, the gate structure 3 further includes the sidewall 33 covering the sidewall of the gate 31 .

[0121] Specifically, forming the gate structure 3 includes the following steps: forming a gate dielectric material layer covering the upper surface of the substrate 1, and forming a gate material layer on the upper surface of the gate dielectric material layer; forming a patterned second photoresist layer on the upper surface of the gate material layer, and etching the gate material layer based on the patterned second photoresist layer to obtain the gate 31 and the gate dielectric layer 32; forming a sidewall material layer covering the exposed surface of the gate 31 and the gate dielectric layer 32, and etching the sidewall material layer to obtain the sidewall 33.

[0122] Specifically, the method of forming the gate dielectric material layer includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the gate material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0123] Specifically, the method of forming the second photoresist layer and patterning the second photoresist layer is a commonly used photoresist forming and developing method, which will not be described in detail here.

[0124] Specifically, the method of forming the gate 31 includes dry etching, wet etching or other suitable etching methods; the method of forming the gate dielectric layer 32 includes dry etching, wet etching or other suitable etching methods.

[0125] Specifically, the method of forming the spacer material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0126] Specifically, the method of forming the sidewall spacer 33 includes dry etching, wet etching or other suitable methods.

[0127] Specifically, under the condition of ensuring device performance, the gate 31 and the conductive layer 22 can be formed simultaneously; the dielectric layer 21 and the gate dielectric layer 32 can be formed simultaneously.

[0128] Specifically, step S4 is performed to form a source region 4 and a drain region 5 in the active layer 13 on both sides of the gate structure 3 along the X direction.

[0129] Specifically, the method for forming the source region 4 includes ion implantation or other suitable methods; the method for forming the drain region 5 includes ion implantation or other suitable methods.

[0130] Specifically, step S5 is performed to form a gate metal layer 61 electrically connected to the gate structure 3, a source metal layer 62 electrically connected to the source region 4, and a drain metal layer 63 electrically connected to the surface of the drain region 5 to obtain a SOI MOS device.

[0131] Specifically, the method of forming the gate metal layer 61 includes sputtering, chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the source metal layer 62 includes sputtering, chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the drain metal layer 63 includes sputtering, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0132] Specifically, by forming the bias electrode structure 2, the parasitic capacitance of the SOI MOS device is reduced, and the setting of the cavity opening 15 reduces the control range of the gate structure 3 on the conductive channel region in the active layer 13, thereby increasing the control capability of the gate structure 3, reducing leakage current, and improving device performance.

[0133] The SOI MOS device of this embodiment forms the bias electrode structure 2, which is isolated from the substrate 1, thereby reducing the parasitic capacitance of the SOI MOS device. The formation of the cavity opening 15 reduces the control range of the gate structure 3 on the conductive channel region in the active layer 13, thereby increasing the control capability of the gate structure 3, reducing leakage current, and improving the performance of the SOI MOS device.

[0134] Example 3

[0135] This embodiment provides another SOI MOS device, such as Figure 26 , which is a schematic cross-sectional view of the doped region 16 in the SOI MOS device in the X direction. The SOI MOS device of this embodiment is improved based on the SOIMOS device described in the first embodiment, that is, a doped region 16 is provided between the bias electrode structure 2 and the gate structure 3. The doping type of the doped region 16 is the same as or opposite to the doping type of the active layer 13. For example, when the device is an NMOS device, the doped region 16 is P-type doped and the active layer 13 is N-type doped; when the device is a PMOS device, the doped region 16 is N-type doped and the active layer 13 is P-type doped.

[0136] As an example, Figure 27 and Figure 28 As shown, there is a top view after forming the doped region 16 and a schematic cross-sectional view along the Y direction after forming the doped region 16 (wherein the dotted boxes in the figure represent the cavity 14 and the doped region 16, respectively). After forming the dielectric layer 21 and before forming the conductive layer 22, the step of forming the doped region 16 in the active layer 13 at the edge of the cavity opening 15 above the cavity 14 is also included. The doping type of the doped region 16 is opposite to or the same as the doping type of the active layer 13.

[0137] Specifically, the method of forming the doped region 16 includes lightly doped drain (LDD) doping, ultra-thin (Halo) doping or other suitable methods.

[0138] Specifically, under the condition that the performance of the SOI MOS device is met, the doping ion concentration of the doping region 16 can be selected according to actual conditions and is not limited here. In this embodiment, the doping ion concentration of the doping region 16 is less than the doping ion concentration of the source region 4.

[0139] Specifically, the method of forming the doping region 16 includes ion implantation or other suitable methods.

[0140] Specifically, when the doping region 16 is formed, the doping region 16 extends from both sides of the gate structure 3 to the edge of the cavity opening 15, that is, the doping region 16 extends from the edge of the active layer 13 above the cavity to below the side wall of the gate 31, thereby reducing the conductive channel area of ​​the active layer 13 controlled by the gate structure 3.

[0141] Specifically, the doping type of the doping region 16 is opposite to the doping type of the active layer 13, and the doping region 16 forms a PN junction with the active layer 13, further reducing the control range of the gate structure 3 on the active layer 13, enhancing the control ability of the gate structure 3, thereby reducing leakage current and improving the performance of the SOI MOS device.

[0142] The SOI MOS device of this embodiment forms a doped region 16 having a doping type opposite to that of the active layer 13 in the active layer 13 of the SOI MOS device described in the first embodiment, so that the doped region 16 forms a PN junction with the active layer 13, thereby further reducing the area of ​​the control region of the gate structure 3 on the active layer 13, enhancing the control capability of the gate structure 3, reducing leakage current, and improving device performance.

[0143] Example 4

[0144] This embodiment provides a third SOI MOS device, such as Figure 29 , which is a schematic cross-sectional view along the Y direction of the groove 7 provided in the SOI MOS device. The SOI MOS device of this embodiment is an improvement of the SOI MOS device in the first embodiment, that is, a groove 7 penetrating the gate dielectric layer 32 and the active layer 13 is provided in the gap between the gate structure 3 and the bias electrode structure 2.

[0145] Specifically, under the condition that the performance of the SOI MOS device is met, the width of the trench 7 can be selected according to actual conditions and is not limited here.

[0146] Specifically, a dielectric layer (not shown) is further provided in the trench 7 to cover the inner wall of the trench 7 to improve device performance.

[0147] Specifically, the trench 7 isolates the gate structure 3 and the channel region in the active layer 13 located below the gate structure 3 from the rest of the active layer 13 .

[0148] As an example, after forming the gate structure 3 and before forming the source metal layer 62 , the method further includes forming a groove 7 penetrating the gate dielectric layer 32 and the active layer 13 in the gap between the gate structure 3 and the bias electrode structure 2 .

[0149] Specifically, the method of forming the trench 7 includes dry etching, wet etching or other suitable methods.

[0150] Specifically, the provision of the trench 7 isolates the conductive channel region in the active layer 13 located below the gate structure 3 from the portion of the active layer 13 located at the bias electrode structure 2 and the trench 7, further reducing the control range of the gate structure 3 on the conductive channel region in the active layer 13, reducing the leakage current of the SOI MOS device, and improving the performance of the SOI MOS device.

[0151] The SOI MOS device of this example improves the structure of the SOI MOS device in Example 1 by forming a trench 7 penetrating the gate dielectric layer 32 and the active layer 13 in the gap between the gate structure 3 and the bias electrode structure 2. This isolates the channel region in the active layer 13 below the gate structure 3 from the portion of the active layer 13 between the bias electrode structure 2 and the trench 7, further reducing the area of ​​the control region of the gate structure 3, thereby reducing the leakage current of the SOI MOS device and improving device performance.

[0152] Example 5

[0153] This embodiment provides a fourth SOI MOS device, such as Figure 30 and Figure 31As shown in the figures, there are respectively a top view of the substrate 1 provided with the cavity extension 8 in the SOI MOS device and a top view of the substrate 1 provided with the cavity extension 8 after the cavity opening 15 is formed. The SOI MOS device of this embodiment is improved based on the SOIMOS device in the first embodiment, that is, at least one cavity extension 8 is further provided in the substrate 1, and the cavity extension 8 is connected to the cavity 14.

[0154] Specifically, under the condition that the performance of the SOI MOS device is met, the size and number of the cavity extension portion 8 can be selected according to actual conditions and are not limited here.

[0155] Specifically, the conductive layer 22 fills the cavity extension portion 8 , and the conductive layer 22 disposed in the cavity extension portion 8 is electrically connected to the bias electrode 23 .

[0156] As an example, a cavity extension portion 8 communicating with the cavity 14 is further provided in the substrate 1 .

[0157] Specifically, at least one of the cavity openings 15 overlaps with the cavity extension portion 8 .

[0158] Specifically, by setting the cavity extension portion 8 in the substrate 1, and the cavity extension portion 8 is also filled with the conductive layer 22, the conductive layer 22 in the cavity extension portion 8 is electrically connected to the bias electrode 23, so that the electric field distribution in the SOI MOS device is more uniform, and the parasitic capacitance of the device is reduced.

[0159] The SOI MOS device of this embodiment provides the cavity extension portion 8 communicating with the cavity 14 in the SOI MOS device of the first embodiment, and also provides the bias electrode 23 electrically connected to the conductive layer 22 in the cavity extension portion 8, thereby making the electric field distribution in the SOI MOS device more uniform and reducing the parasitic capacitance of the SOI MOS device.

[0160] Example 6

[0161] This embodiment provides a fifth SOI MOS device, such as Figure 32-Figure 35 As shown, they are respectively a top view of the SOI MOS device provided with the body contact electrode 9, a cross-sectional schematic diagram of the portion of the SOI MOS device provided with the body contact electrode 9 along the X direction, a SEM image of the portion provided with the body contact electrode 9, and Figure 34As shown in the enlarged view of the dotted frame portion in FIG, the SOI MOS device of this embodiment is improved based on the SOI MOS device of the third embodiment, that is, the doping type of the doping region 16 is opposite to the doping type of the active layer 13, and the SOI MOS device is provided with a body contact electrode 9 electrically connected to the doping region 16.

[0162] As an example, the doping type of the doping region 16 is opposite to the doping type of the active layer 13 , and forming the source metal layer 62 also includes forming a body contact electrode 9 electrically connected to the doping region 16 .

[0163] Specifically, the material of the body contact electrode 9 includes titanium, titanium nitride, silver, gold, copper, tungsten, platinum, aluminum or other suitable conductive materials.

[0164] Specifically, the method of forming the body contact electrode 9 includes sputtering, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0165] Specifically, when the body contact electrode 9 is provided in the device, the doping type of the doping region 16 is opposite to that of the active layer 13 .

[0166] Specifically, by providing the body contact electrode 9 with the doped region 16, when the body contact electrode 9 is connected to a potential, the width of the PN junction formed by the doped region 16, the source region 4 and the drain region 5 can be regulated, thereby further reducing the control area of ​​the gate structure 3 on the active layer 13 and reducing the leakage current of the device.

[0167] The SOI MOS device of this embodiment is improved based on the SOI MOS device described in the third embodiment. By providing the body contact electrode 9 electrically connected to the doped region 16 in the SOI MOS device, the control area of ​​the gate structure 3 is further reduced, the leakage current of the device is reduced, and the performance of the device is improved.

[0168] Example 7

[0169] This embodiment provides a sixth SOI MOS device. The structure of the SOI MOS device of this embodiment is improved based on the gate structure 3 of the SOI MOS device described in the first embodiment. The gate 31 is a metal electrode, and the gate dielectric layer 32 is a high-K dielectric layer.

[0170] Specifically, the material of the high-K dielectric layer includes tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate or other suitable high-K dielectric materials.

[0171] Specifically, the metal electrode includes a buffer layer, a barrier layer, a work function adjustment layer and a metal electrode layer stacked in sequence.

[0172] Specifically, the method for forming the metal electrode is a conventional metal gate forming method, which will not be described in detail here.

[0173] Specifically, when the gate structure 3 is configured as the metal electrode and the high-K dielectric layer, the leakage current and parasitic capacitance of the device can be reduced by combining the gate structure 3 with the bias electrode structure 2 .

[0174] The SOI MOS device of this embodiment improves the gate structure 3 of the SOI MOS device in the first embodiment. When the gate 31 is set as the metal electrode and the gate dielectric layer is set as the high-K dielectric layer, the leakage current and parasitic capacitance of the device can be reduced through the combination of the gate structure 3 and the bias electrode structure 2.

[0175] In summary, the SOI MOS device and its preparation method in the present invention reduce the parasitic capacitance of the device by providing a cavity and a bias electrode structure filling the cavity; the provision of the bias electrode and the cavity opening also reduces the control range of the gate structure on the active layer, increases the control capability of the gate structure, reduces the leakage current, and improves the performance of the SOI MOS device; the gate structure and the bias electrode structure cooperate with each other to control the SOI The invention relates to a MOS device that operates by reducing the influence of the substrate on the device's operating state and reducing mutual interference between different devices; by applying different voltages to the bias electrode structure, dynamic adjustment of the device's threshold voltage is achieved; by providing a doped region with a doping type opposite to that of the active layer in the active layer, a PN junction formed by the doped region and the active layer further reduces the control range of the gate, increases the control capability of the gate, and reduces leakage current; a trench penetrating the gate dielectric layer and the active layer is formed in the gap between the gate structure and the bias electrode structure, isolating the conductive channel region in the active layer below the gate structure from the portion of the active layer between the bias electrode structure and the trench, further reducing the control range of the gate structure and reducing the leakage current of the device; providing a body contact electrode electrically connected to the doped region, further reducing the area of ​​the gate structure control region, thereby reducing the leakage current of the device; and by providing a cavity extension portion in the substrate, the electric field distribution in the SOI MOS device is more uniform, further reducing the parasitic capacitance of the device. Therefore, the invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0176] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A SOIMOS device, characterized in that: include: A base, comprising a substrate, a buried oxide layer, an active layer, and a cavity stacked in sequence, wherein the cavity is embedded in the base and a top of the cavity is spaced a preset distance from an upper surface of the active layer, and the top of the cavity is provided with at least one cavity opening communicating with the outside; a bias electrode structure comprising a dielectric layer covering an inner wall of the cavity, a conductive layer filling the cavity, and a bias electrode electrically connected to the conductive layer, wherein the dielectric layer wraps the conductive layer; a gate structure comprising a gate and a gate dielectric layer stacked in sequence, wherein the gate structure is located above the cavity, and a preset distance is separated from the cavity opening; a source region and a drain region, respectively located in the active layer on both sides of the gate structure along the X direction; A gate metal layer, a source metal layer and a drain metal layer, wherein the gate metal layer is electrically connected to the gate, the source metal layer is electrically connected to the source region, and the drain metal layer is electrically connected to the drain region.

2. The SOI MOS device according to claim 1, wherein: A doping region is provided in the active layer between the bias electrode structure and the gate structure, and a doping type of the doping region is the same as or opposite to a doping type of the active layer.

3. The SOI MOS device according to claim 2, wherein: The doping type of the doping region is opposite to the doping type of the active layer, and the SOIMOS device is provided with a body contact electrode electrically connected to the doping region.

4. The SOI MOS device according to claim 1, wherein: A trench penetrating the gate dielectric layer and the active layer is provided in the gap between the gate structure and the bias electrode structure.

5. The SOI MOS device according to claim 1, wherein: The bias electrode structure is provided with an isolation layer covering the sidewall of the conductive layer protruding from the upper surface of the active layer.

6. The SOI MOS device according to claim 1, wherein: At least one cavity extension portion is provided in the base, and the cavity extension portion is communicated with the cavity.

7. The SOI MOS device according to claim 1, wherein: The gate is a metal electrode, and the gate dielectric layer is a high-K dielectric layer.

8. A method for preparing a SOIMOS device, characterized in that: The following steps are involved: A substrate is provided, comprising a substrate, a buried oxide layer, an active layer, and a cavity stacked in sequence, wherein the cavity is embedded in the substrate and a top of the cavity is spaced a preset distance from an upper surface of the active layer, and at least one cavity opening communicating with the outside is formed at the top of the cavity; forming a bias electrode structure in the cavity, the bias electrode structure comprising a dielectric layer covering an inner wall of the cavity, a conductive layer filling the cavity, and a bias electrode electrically connected to the conductive layer, wherein the dielectric layer wraps the conductive layer; forming a gate structure above the cavity, the gate structure comprising a gate and a gate dielectric layer stacked in sequence, and a preset distance between the gate structure and the cavity opening; forming a source region and a drain region in the active layer on both sides of the gate structure along the X direction; A gate metal layer electrically connected to the gate is formed, a source metal layer electrically connected to the source region is formed, and a drain metal layer electrically connected to the surface of the drain region is formed to obtain a SOIMOS device.

9. The method for preparing a SOI MOS device according to claim 8, wherein: After forming the dielectric layer and before forming the conductive layer, the method further includes forming a doped region in the active layer below the gate structure, wherein the doping type of the doped region is opposite to or the same as the doping type of the active layer.

10. The method for preparing a SOIMOS device according to claim 9, wherein: The doping type of the doping region is opposite to the doping type of the active layer. The step of forming the source metal layer also includes forming a body contact electrode electrically connected to the doping region.

11. The method for preparing a SOIMOS device according to claim 8, wherein: After forming the gate structure and before forming the source metal layer, the method further includes forming a trench penetrating the gate dielectric layer and the active layer in the gap between the gate structure and the bias electrode structure.

12. The method for preparing a SOIMOS device according to claim 8, wherein: The base is also provided with a cavity extension portion communicating with the cavity.

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