Ga2o3 / si topcon photovoltaic cell and preparation method

Abstract

The application discloses a Ga2O3 / Si TOPCon photovoltaic cell, which comprises an n-type silicon wafer, a tunneling layer, an n-type polycrystalline silicon layer and a back electrode are sequentially arranged on the back surface of the n-type silicon wafer from near to far, and an intrinsic beta-Ga2O3 layer, a passivation layer and an anti-reflection layer are sequentially arranged on the front surface of the n-type silicon wafer from near to far; a pair of top electrodes are further arranged on the intrinsic beta-Ga2O3 layer, and the two top electrodes sequentially penetrate the passivation layer and the anti-reflection layer and extend out of the anti-reflection layer. The application solves the problem of low photovoltaic conversion efficiency caused by optical loss due to the absorption of the polycrystalline silicon layer on the front surface to incident visible light in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic cell technology, specifically relating to a Ga2O3 / Si TOPCon photovoltaic cell, and also to a method for preparing a Ga2O3 / Si TOPCon photovoltaic cell. Background Technology

[0002] Tunneling oxide passivated contacts (TOPCon) in silicon-based solar cells are popular due to their simple ohmic contact structure, high photoelectric conversion efficiency, and ease of industrialization. With a theoretical limiting efficiency of up to 28.7%, they are among the most sought-after commercial crystalline silicon solar cells. Current TOPCon technology is primarily applied to the back surface of the cell, consisting of an extremely thin oxide layer and a thin polycrystalline silicon layer. It provides good passivation for minority carriers and excellent conductivity for majority carriers. The front side uses doped polycrystalline silicon as the emitter, with Al2O3 thin film and SiN... x The thin films serve as passivation layers and antireflection layers, respectively. Currently, thin films are fabricated on n-type c-Si wafers with n... + -poly-Si / SiO x n-TOPCon structures are widely used due to their excellent passivation quality and high photoelectric conversion efficiency. However, in traditional TOPCon structures, the bandgap of polycrystalline silicon, which serves as the top photon absorption layer, is 1.1 eV to 1.7 eV. Therefore, during the light capture process, a considerable portion of the incident visible light is absorbed by the front polycrystalline silicon layer, reducing the cell's ability to capture light and thus affecting the cell's photoelectric conversion efficiency.

[0003] Gallium oxide (β-Ga₂O₃), as a novel direct bandgap wide bandgap semiconductor material, is compatible with n... + Compared to polycrystalline silicon, gallium oxide (β-Ga₂O₃) has a larger bandgap, which effectively increases the cell's ability to capture visible light. Meanwhile, gallium oxide (β-Ga₂O₃) has a higher work function than (n)c-Si, thus forming hole-selective contacts and reducing recombination losses between the light-absorbing layer and the contacts. The Ga₂O₃ / Si-based TOPCon photovoltaic cell designed in this invention can significantly improve the conversion efficiency of n-TOPCon cells and has great application potential. Summary of the Invention

[0004] The purpose of this invention is to provide a Ga2O3 / Si TOPCon photovoltaic cell that solves the problem of low photoelectric conversion efficiency caused by optical loss due to the absorption of incident visible light by the polycrystalline silicon layer on the front side in the prior art.

[0005] Another objective of this invention is to provide a method for preparing Ga2O3 / Si TOPCon photovoltaic cells.

[0006] The first technical solution adopted in this invention is a Ga2O3 / Si TOPCon photovoltaic cell, characterized in that it includes an n-type silicon wafer, on the back side of which a tunneling layer, an n-type polycrystalline silicon layer, and a back electrode are sequentially disposed from near to far; on the front side of the n-type silicon wafer, an intrinsic β-Ga2O3 layer, a passivation layer, and an antireflection layer are sequentially disposed from near to far; a pair of top electrodes are also disposed on the intrinsic β-Ga2O3 layer, the two top electrodes sequentially penetrating the passivation layer and the antireflection layer and extending beyond the antireflection layer.

[0007] The first technical solution of the present invention is further characterized in that,

[0008] The n-type silicon wafer has a thickness of 100μm to 200μm and a resistivity of 0.1Ω·cm to 5Ω·cm. The tunneling layer is made of one of SiO2, Al2O3, or SiC and has a thickness of 1nm to 3nm. The n-type polycrystalline silicon layer has a thickness of 100nm to 200nm. The intrinsic β-Ga2O3 layer is made of one of the following crystal planes: β-Ga2O3(-201), β-Ga2O3(001), or β-Ga2O3(010) and has a thickness of 50nm to 200nm. The passivation layer is made of Al2O3 and has a thickness of 5nm to 20nm. The antireflection layer is made of one of the following crystal planes: Si3N4 or Si2N2O and has a thickness of 60nm to 150nm.

[0009] The second technical solution adopted in this invention is a method for preparing Ga2O3 / Si TOPCon photovoltaic cells, which is implemented according to the following steps:

[0010] Step 1: Perform alkaline polishing on the n-type silicon wafer;

[0011] Step 2: Texturing the front side of the n-type silicon wafer after polishing in Step 1 to form a surface pyramid structure;

[0012] Step 3: Clean the n-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF);

[0013] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3;

[0014] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4, and remove the oxide layer and polysilicon layer coated on the front side of the n-type silicon wafer using an acidic etching solution;

[0015] Step 6: Grow an intrinsic β-Ga2O3 heteroepitaxial layer on the front side of the n-type silicon wafer;

[0016] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x film;

[0017] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x film;

[0018] Step 9: Fabricate the back electrode on the n-type polycrystalline silicon layer obtained in step 5;

[0019] Step 10, the SiN obtained in step 8 x The top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell.

[0020] The second technical solution of the present invention is further characterized in that,

[0021] In step 1, an alkaline polishing process is performed on the n-type silicon wafer using a KOH solution with a concentration of 3% to 5% to remove surface damage. In step 2, a NaOH solution with a concentration of 3% to 5% is used to uniformly etch the surface of the n-type silicon wafer during texturing.

[0022] In step 3, the n-type silicon wafer is cleaned and briefly immersed in hydrofluoric acid (HF). The specific cleaning process is as follows: the n-type silicon wafer is cleaned step by step using the first cleaning solution, the second cleaning solution, hydrofluoric acid, alcohol, and deionized water in sequence. The first cleaning solution is a mixture of NH3H2O, H2O2, and deionized water in a volume ratio of 1:1:5. The second cleaning solution is a mixture of HCl, H2O2, and deionized water in a volume ratio of 1:1:5. The concentration of hydrofluoric acid is 3%~6%, and the concentration of alcohol is 99.9%.

[0023] In step 4, the oxide layer is grown using the hot nitric acid oxidation method, which involves placing the n-type silicon wafer in a 65%~70% HNO3 solution for 10 to 20 minutes, with the HNO3 solution temperature being 90℃~110℃.

[0024] In step 5, when depositing n-type polycrystalline silicon on the oxide layer, a radio frequency PECVD system is used for plasma-enhanced chemical vapor deposition. A mixture of SiH4 and PH3 is used as the source gas, and a mixture of H2 and Ar is used as the dilution gas. The radio frequency power is controlled at 3W~15W. The acid etching solution is a 5% hydrofluoric acid solution by volume.

[0025] In step 6, during the growth of the intrinsic β-Ga2O3 heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O2 as the growth source gas, as detailed below:

[0026] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0027] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0028] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0029] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 550℃~650℃; the working temperature of the substrate in the second temperature zone is 700℃~1050℃.

[0030] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 1h~3h to deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0031] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0032] In step 7, atomic layer deposition (ALD) is used with Al(CH3)3 and H2O as precursors, and the deposition temperature is 100℃~350℃. In step 8, plasma-enhanced chemical vapor deposition (PECVD) is used with SiH4 and NH3 as gas sources, the n-type silicon wafer temperature is 200℃~500℃, and the radio frequency power is 3W~5W. In step 9, when fabricating the back electrode on the n-type polycrystalline silicon layer, Ag back electrode is deposited by thermal evaporation.

[0033] In step 10, photolithography is first used to create an opening, and AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

[0034] The beneficial effect of this invention is that the Ga2O3 / Si TOPCon photovoltaic cell uses a Ga2O3 / Si structure instead of the existing n-type structure. +The poly-Si / Si structure, utilizing the high work function of Ga2O3 material, enables hole-selective contact, effectively reducing recombination losses between the light absorption layer and the contact. At the same time, the large bandgap of Ga2O3 material reduces the optical loss of photovoltaic cells and improves light-harvesting ability, thereby effectively improving the conversion efficiency of photovoltaic cells. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of a Ga2O3 / Si TOPCon photovoltaic cell according to the present invention;

[0036] Figure 2 This is a flowchart of a method for preparing Ga2O3 / Si TOPCon photovoltaic cells according to the present invention.

[0037] In the figure, 1. Tunneling layer, 2. n-type doped polycrystalline silicon layer, 3. Back electrode, 4. Intrinsic β-Ga2O3 layer, 5. Passivation layer, 6. Anti-reflection layer, 7. Top electrode, 8. n-type silicon wafer. Detailed Implementation

[0038] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0039] Ga2O3 / Si TOPCon photovoltaic cells, structure as follows Figure 1 As shown, it includes an n-type silicon wafer 8. On the back side of the n-type silicon wafer 8, from near to far, a tunneling layer 1, an n-type polycrystalline silicon layer 2, and a back electrode 3 are arranged sequentially. On the front side of the n-type silicon wafer 8, from near to far, an intrinsic β-Ga2O3 layer 4, a passivation layer 5, and an anti-reflection layer 6 are arranged sequentially. A pair of top electrodes 7 are also arranged on the intrinsic β-Ga2O3 layer 4. The two top electrodes 7 pass through the passivation layer 5 and the anti-reflection layer 6 in sequence and extend outside the anti-reflection layer 6.

[0040] The n-type silicon wafer 8 has a thickness of 100μm to 200μm and a resistivity of 0.1Ω·cm to 5Ω·cm. The tunneling layer 1 is made of one of SiO2, Al2O3, or SiC and has a thickness of 1nm to 3nm. The n-type polycrystalline silicon layer 2 has a thickness of 100nm to 200nm. The intrinsic β-Ga2O3 layer 4 is made of one of the following crystal planes: β-Ga2O3(-201), β-Ga2O3(001), or β-Ga2O3(010) and has a thickness of 50nm to 200nm. The passivation layer 5 is made of Al2O3 and has a thickness of 5nm to 20nm. The antireflection layer 6 is made of one of Si3N4 or Si2N2O and has a thickness of 60nm to 150nm.

[0041] The fabrication method of Ga2O3 / Si TOPCon photovoltaic cells, flowchart as follows: Figure 2 As shown, please follow these steps:

[0042] Step 1: Perform alkaline polishing on the n-type silicon wafer;

[0043] In step 1, an alkaline polishing process is performed on the n-type silicon wafer using a 3%~5% KOH solution to remove surface serrations.

[0044] Step 2: Texturing the front side of the n-type silicon wafer after polishing in Step 1 to form a surface pyramid structure;

[0045] In step 2, a 3% to 5% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer during texturing.

[0046] Step 3: Clean the n-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF);

[0047] In step 3, the n-type silicon wafer is cleaned and briefly immersed in hydrofluoric acid (HF). The specific cleaning process is as follows: the n-type silicon wafer is cleaned step by step using the first cleaning solution, the second cleaning solution, hydrofluoric acid, alcohol, and deionized water in sequence. The first cleaning solution is a mixture of NH3H2O, H2O2, and deionized water in a volume ratio of 1:1:5. The second cleaning solution is a mixture of HCl, H2O2, and deionized water in a volume ratio of 1:1:5. The concentration of hydrofluoric acid is 3%~6%, and the concentration of alcohol is 99.9%.

[0048] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3;

[0049] In step 4, the oxide layer is grown using the hot nitric acid oxidation method, which involves placing the n-type silicon wafer in a 65%~70% HNO3 solution for 10 to 20 minutes, with the HNO3 solution temperature being 90℃~110℃.

[0050] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4, and remove the oxide layer and polysilicon layer coated on the front side of the n-type silicon wafer using an acidic etching solution;

[0051] In step 5, when depositing n-type polycrystalline silicon on the oxide layer, a radio frequency PECVD system is used for plasma-enhanced chemical vapor deposition. A mixture of SiH4 and PH3 is used as the source gas, and a mixture of H2 and Ar is used as the dilution gas. The radio frequency power is controlled at 3W~15W. The acid etching solution is a 5% hydrofluoric acid solution by volume.

[0052] Step 6: Grow an intrinsic β-Ga2O3 heteroepitaxial layer on the front side of the n-type silicon wafer;

[0053] In step 6, during the growth of the intrinsic β-Ga2O3 heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O2 as the growth source gas, as detailed below:

[0054] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0055] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0056] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0057] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 550℃~650℃; the working temperature of the substrate in the second temperature zone is 700℃~1050℃.

[0058] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 1h~3h to deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0059] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0060] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x film;

[0061] In step 7, atomic layer deposition (ALD) is used with Al(CH3)3 and H2O as precursors, and the deposition temperature is 100℃~350℃.

[0062] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x film;

[0063] In step 8, plasma-enhanced chemical vapor deposition (PECVD) is used, with SiH4 and NH3 as gas sources, the temperature of the n-type silicon wafer is 200℃~500℃, and the radio frequency power is 3W~5W.

[0064] Step 9: Fabricate the back electrode on the n-type polycrystalline silicon layer obtained in step 5;

[0065] In step 9, when fabricating the back electrode on the n-type polycrystalline silicon layer, the Ag back electrode is deposited by thermal evaporation.

[0066] Step 10, the SiN obtained in step 8 x The top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell.

[0067] In step 10, photolithography is first used to create an opening, and AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

[0068] Example 1

[0069] This invention discloses a method for preparing a Ga2O3 / Si TOPCon photovoltaic cell, which is implemented according to the following steps:

[0070] Step 1: Perform alkaline polishing on the n-type silicon wafer. The alkaline polishing process is as follows: use a 3% KOH solution to perform alkaline polishing on the n-type silicon wafer to remove surface saw damage.

[0071] Step 2: After polishing in Step 1, texturing is performed on the front side of the n-type silicon wafer to form a surface pyramid structure. During texturing, a 3% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer.

[0072] Step 3: Clean the p-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF). The specific cleaning process is as follows: use the first cleaning solution (NH3H2O:H2O2:deionized water = 1:1:5) ~ the second cleaning solution (HCl:H2O2:deionized water = 1:1:5) ~ 3% hydrofluoric acid ~ 99.9% alcohol ~ deionized water to gradually clean the n-type silicon wafer.

[0073] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3. The oxide layer is grown using the hot nitric acid oxidation method, that is, the n-type silicon wafer is placed in a 70% HNO3 solution for 10 minutes and the temperature of the HNO3 solution is 110℃.

[0074] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4. When depositing the n-type polysilicon layer on the oxide layer, use an RF PECVD system for plasma-enhanced chemical vapor deposition, with a mixture of SiH4 and PH3 as the source gas and a mixture of H2 and Ar as the dilution gas, and control the RF power to 3W.

[0075] Step 6: An intrinsic β-Ga₂O₃ heteroepitaxial layer is grown on the front side of the n-type silicon wafer. During the growth of the intrinsic β-Ga₂O₃ heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O₂ as the growth source gas. The specific details are as follows:

[0076] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0077] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0078] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0079] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 550℃; the working temperature of the substrate in the second temperature zone is 1050℃.

[0080] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 1 hour and deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0081] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0082] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x Thin film, AlO deposited on intrinsic β-Ga2O3 heteroepitaxial layer x Atomic layer deposition (ALD) was used for thin film deposition, with Al(CH3)3 and H2O as precursors and a deposition temperature of 100℃.

[0083] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x Thin film, in AlO x SiN deposition on thin film xThe thin film was produced using plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and NH3 as gas sources. The temperature of the p-type silicon wafer was 500℃, and the RF power was 5W.

[0084] Step 9: Fabricate a back electrode on the n-type polysilicon layer obtained in step 5. When fabricating the back electrode on the n-type polysilicon layer, the Ag back electrode is deposited by thermal evaporation.

[0085] Step 10, the SiN obtained in step 8 x A top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell. Among them, SiN... x When fabricating the top electrode on the thin film, photolithography is first used to create an opening, and then AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

[0086] Example 2

[0087] This invention discloses a method for preparing a Ga2O3 / Si TOPCon photovoltaic cell, which is implemented according to the following steps:

[0088] Step 1: Perform alkaline polishing on the n-type silicon wafer. The alkaline polishing process is as follows: use a 3.5% KOH solution to perform alkaline polishing on the n-type silicon wafer to remove surface saw damage.

[0089] Step 2: After polishing in Step 1, texturing is performed on the front side of the n-type silicon wafer to form a surface pyramid structure. During texturing, a 3.5% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer.

[0090] Step 3: Clean the p-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF). The specific cleaning process is as follows: use the first cleaning solution (NH3H2O:H2O2:deionized water = 1:1:5) ~ the second cleaning solution (HCl:H2O2:deionized water = 1:1:5) ~ 4% hydrofluoric acid ~ 99.9% alcohol ~ deionized water to gradually clean the n-type silicon wafer.

[0091] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3. The oxide layer is grown using the hot nitric acid oxidation method, that is, the n-type silicon wafer is placed in a 68% HNO3 solution for 12 minutes, and the temperature of the HNO3 solution is 100℃.

[0092] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4. When depositing the n-type polysilicon layer on the oxide layer, use an RF PECVD system for plasma-enhanced chemical vapor deposition, with a mixture of SiH4 and PH3 as the source gas and a mixture of H2 and Ar as the dilution gas, and control the RF power to 5W.

[0093] Step 6: An intrinsic β-Ga₂O₃ heteroepitaxial layer is grown on the front side of the n-type silicon wafer. During the growth of the intrinsic β-Ga₂O₃ heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O₂ as the growth source gas. The specific details are as follows:

[0094] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0095] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0096] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0097] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 570℃; the working temperature of the substrate in the second temperature zone is 1000℃.

[0098] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 1.5h and deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0099] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0100] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x Thin film, AlO deposited on intrinsic β-Ga2O3 heteroepitaxial layer x Atomic layer deposition (ALD) was used for thin film deposition, with Al(CH3)3 and H2O as precursors, and the deposition temperature was 200℃.

[0101] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x Thin film, in AlO x SiN deposition on thin film x The thin film was produced using plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and NH3 as gas sources. The p-type silicon wafer temperature was 400℃ and the radio frequency power was 4.5W.

[0102] Step 9: Fabricate a back electrode on the n-type polysilicon layer obtained in step 5. When fabricating the back electrode on the n-type polysilicon layer, the Ag back electrode is deposited by thermal evaporation.

[0103] Step 10, the SiN obtained in step 8 x A top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell. Among them, SiN... x When fabricating the top electrode on the thin film, photolithography is first used to create an opening, and then AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

[0104] Example 3

[0105] This invention discloses a method for preparing a Ga2O3 / Si TOPCon photovoltaic cell, which is implemented according to the following steps:

[0106] Step 1: Perform alkaline polishing on the n-type silicon wafer. The alkaline polishing process is as follows: use a 4% KOH solution to perform alkaline polishing on the n-type silicon wafer to remove surface saw damage.

[0107] Step 2: Texturing the front side of the n-type silicon wafer after polishing in Step 1 to form a surface pyramid structure. During texturing, a 4% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer.

[0108] Step 3: Clean the p-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF). The specific cleaning process is as follows: use the first cleaning solution (NH3H2O:H2O2:deionized water = 1:1:5) ~ the second cleaning solution (HCl:H2O2:deionized water = 1:1:5) ~ 4% hydrofluoric acid ~ 99.9% alcohol ~ deionized water to gradually clean the n-type silicon wafer.

[0109] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3. The oxide layer is grown using the hot nitric acid oxidation method, that is, the n-type silicon wafer is placed in a 67% HNO3 solution for 15 minutes, and the temperature of the HNO3 solution is 100℃.

[0110] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4. When depositing the n-type polysilicon layer on the oxide layer, use an RF PECVD system for plasma-enhanced chemical vapor deposition, with a mixture of SiH4 and PH3 as the source gas and a mixture of H2 and Ar as the dilution gas, and control the RF power to 8W.

[0111] Step 6: An intrinsic β-Ga₂O₃ heteroepitaxial layer is grown on the front side of the n-type silicon wafer. During the growth of the intrinsic β-Ga₂O₃ heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O₂ as the growth source gas. The specific details are as follows:

[0112] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0113] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0114] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0115] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 590℃; the working temperature of the substrate in the second temperature zone is 800℃.

[0116] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 2 hours and deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0117] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0118] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x Thin film, AlO deposited on intrinsic β-Ga2O3 heteroepitaxial layer x Atomic layer deposition (ALD) was used for thin film deposition, with Al(CH3)3 and H2O as precursors, and the deposition temperature was 250℃.

[0119] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x Thin film, in AlO x SiN deposition on thin film x The thin film was produced using plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and NH3 as gas sources. The temperature of the p-type silicon wafer was 300℃, and the radio frequency power was 4W.

[0120] Step 9: Fabricate a back electrode on the n-type polysilicon layer obtained in step 5. When fabricating the back electrode on the n-type polysilicon layer, the Ag back electrode is deposited by thermal evaporation.

[0121] Step 10, the SiN obtained in step 8 x A top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell. Among them, SiN... x When fabricating the top electrode on the thin film, photolithography is first used to create an opening, and then AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

[0122] Example 4

[0123] This invention discloses a method for preparing a Ga2O3 / Si TOPCon photovoltaic cell, which is implemented according to the following steps:

[0124] Step 1: Perform alkaline polishing on the n-type silicon wafer. The alkaline polishing process is as follows: use a 4.5% KOH solution to perform alkaline polishing on the n-type silicon wafer to remove surface saw damage.

[0125] Step 2: After polishing in Step 1, texturing is performed on the front side of the n-type silicon wafer to form a surface pyramid structure. During texturing, a 4.5% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer.

[0126] Step 3: Clean the p-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF). The specific cleaning process is as follows: use the first cleaning solution (NH3H2O:H2O2:deionized water = 1:1:5) ~ the second cleaning solution (HCl:H2O2:deionized water = 1:1:5) ~ 5% hydrofluoric acid ~ 99.9% alcohol ~ deionized water to gradually clean the n-type silicon wafer.

[0127] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3. The oxide layer is grown using the hot nitric acid oxidation method, that is, the n-type silicon wafer is placed in a 66% HNO3 solution for 17 minutes and the temperature of the HNO3 solution is 90℃.

[0128] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4. When depositing the n-type polysilicon layer on the oxide layer, use an RF PECVD system for plasma-enhanced chemical vapor deposition, with a mixture of SiH4 and PH3 as the source gas and a mixture of H2 and Ar as the dilution gas, and control the RF power to 12W.

[0129] Step 6: An intrinsic β-Ga₂O₃ heteroepitaxial layer is grown on the front side of the n-type silicon wafer. During the growth of the intrinsic β-Ga₂O₃ heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O₂ as the growth source gas. The specific details are as follows:

[0130] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0131] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0132] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0133] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 630℃; the working temperature of the substrate in the second temperature zone is 900℃.

[0134] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 2.5h and deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0135] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0136] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. xThin film, AlO deposited on intrinsic β-Ga2O3 heteroepitaxial layer x Atomic layer deposition (ALD) was used for thin film deposition, with Al(CH3)3 and H2O as precursors and a deposition temperature of 300℃.

[0137] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x Thin film, in AlO x SiN deposition on thin film x The thin film was produced using plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and NH3 as gas sources. The p-type silicon wafer temperature was 200℃ and the radio frequency power was 3.5W.

[0138] Step 9: Fabricate a back electrode on the n-type polysilicon layer obtained in step 5. When fabricating the back electrode on the n-type polysilicon layer, the Ag back electrode is deposited by thermal evaporation.

[0139] Step 10, the SiN obtained in step 8 x A top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell. Among them, SiN... x When fabricating the top electrode on the thin film, photolithography is first used to create an opening, and then AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

[0140] Example 5

[0141] This invention discloses a method for preparing a Ga2O3 / Si TOPCon photovoltaic cell, which is implemented according to the following steps:

[0142] Step 1: Perform alkaline polishing on the n-type silicon wafer. The alkaline polishing process is as follows: use a 5% KOH solution to perform alkaline polishing on the n-type silicon wafer to remove surface saw damage.

[0143] Step 2: After polishing in Step 1, texturing is performed on the front side of the n-type silicon wafer to form a surface pyramid structure. During texturing, a 5% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer.

[0144] Step 3: Clean the p-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF). The specific cleaning process is as follows: use the first cleaning solution (NH3H2O:H2O2:deionized water = 1:1:5) ~ the second cleaning solution (HCl:H2O2:deionized water = 1:1:5) ~ 6% hydrofluoric acid ~ 99.9% alcohol ~ deionized water to gradually clean the n-type silicon wafer.

[0145] Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3. The oxide layer is grown using the hot nitric acid oxidation method, that is, the n-type silicon wafer is placed in a 65% HNO3 solution for 20 minutes, and the temperature of the HNO3 solution is 90℃.

[0146] Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4. When depositing the n-type polysilicon layer on the oxide layer, use an RF PECVD system for plasma-enhanced chemical vapor deposition, with a mixture of SiH4 and PH3 as the source gas and a mixture of H2 and Ar as the dilution gas, and control the RF power to 15W.

[0147] Step 6: An intrinsic β-Ga₂O₃ heteroepitaxial layer is grown on the front side of the n-type silicon wafer. During the growth of the intrinsic β-Ga₂O₃ heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) system is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O₂ as the growth source gas. The specific details are as follows:

[0148] Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace;

[0149] The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa.

[0150] Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber;

[0151] Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 650℃; the working temperature of the substrate in the second temperature zone is 700℃.

[0152] Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 3 hours and deposit an intrinsic β-Ga2O3 thin film on the substrate.

[0153] Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer.

[0154] Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x Thin film, AlO deposited on intrinsic β-Ga2O3 heteroepitaxial layer x Atomic layer deposition (ALD) was used for thin film deposition, with Al(CH3)3 and H2O as precursors, and the deposition temperature was 350℃.

[0155] Step 8, the AlO obtained in step 7 x SiN deposition on thin film x Thin film, in AlO x SiN deposition on thin film x The thin film was produced using plasma-enhanced chemical vapor deposition (PECVD) with SiH4 and NH3 as gas sources. The temperature of the p-type silicon wafer was 200℃, and the radio frequency power was 3W.

[0156] Step 9: Fabricate a back electrode on the n-type polysilicon layer obtained in step 5. When fabricating the back electrode on the n-type polysilicon layer, the Ag back electrode is deposited by thermal evaporation.

[0157] Step 10, the SiN obtained in step 8 x A top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell. Among them, SiN... x When fabricating the top electrode on the thin film, photolithography is first used to create an opening, and then AlO at the top electrode location is removed through exposure and development. x and SiN x The top electrode of the Ga2O3 / Si TOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

Claims

1. A method for preparing Ga2O3 / Si TOPCon photovoltaic cells, characterized in that, The specific steps are as follows: Step 1: Perform alkaline polishing on the n-type silicon wafer; In step 1, an alkaline polishing process is performed on the n-type silicon wafer using a KOH solution with a concentration of 3% to 5% to remove surface saw damage. Step 2: Texturing the front side of the n-type silicon wafer after polishing in Step 1 to form a surface pyramid structure; in Step 2, a 3%~5% NaOH solution is used to uniformly etch the surface of the n-type silicon wafer during texturing. Step 3: Clean the n-type silicon wafer obtained in Step 2 and briefly immerse it in hydrofluoric acid (HF); The cleaning process in step 3 is as follows: the n-type silicon wafer is cleaned sequentially using a first cleaning solution, a second cleaning solution, hydrofluoric acid, alcohol, and deionized water. The first cleaning solution is a mixture of NH3H2O, H2O2, and deionized water in a volume ratio of 1:1:

5. The second cleaning solution is a mixture of HCl, H2O2, and deionized water in a volume ratio of 1:1:

5. The concentration of hydrofluoric acid is 3%~6%, and the concentration of alcohol is 99.9%. Step 4: An oxide layer is grown on the back side of the n-type silicon wafer after cleaning in Step 3; In step 4, the oxide layer is grown using a hot nitric acid oxidation method, which involves placing the n-type silicon wafer in a 65%~70% HNO3 solution for 10 to 20 minutes, with the HNO3 solution temperature being 90℃~110℃. Step 5: Deposit an n-type polysilicon layer on the oxide layer obtained in step 4, and remove the oxide layer and polysilicon layer coated on the front side of the n-type silicon wafer using an acidic etching solution; In step 5, when depositing n-type polycrystalline silicon on the oxide layer, an RF PECVD system is used for plasma-enhanced chemical vapor deposition, with a mixture of SiH4 and PH3 as the source gas and a mixture of H2 and Ar as the dilution gas. The RF power is controlled at 3W~15W. The acid etching solution is a 5% hydrofluoric acid solution by volume. Step 6: Grow an intrinsic β-Ga2O3 heteroepitaxial layer on the front side of the n-type silicon wafer; In step 6, when growing the intrinsic β-Ga2O3 heteroepitaxial layer on the front side of the n-type silicon wafer, a chemical vapor deposition (CVD) device is used, with 99.99999% pure gallium metal as the gallium source, an inert gas as the carrier gas, and O2 as the growth source gas, as detailed below: Step 6.1: Place the gallium metal source into the quartz boat, and place the quartz boat into the first temperature zone of the dual-temperature zone quartz tube furnace; The n-type silicon wafers obtained in steps 6.2 and 5 are placed on a substrate holder as substrates. The substrate holder carrying the substrate is placed in the second temperature zone of the quartz tube furnace. The reaction chamber is evacuated, and the pressure in the chamber after evacuation is 1 Pa. Step 6.3: Inert gas, which serves as a carrier gas, is introduced into the quartz reaction chamber; Step 6.4: Simultaneously heat the quartz boat carrying the gallium source in the first temperature zone and the substrate in the second temperature zone of the tube furnace; by setting the heating time, make the working temperature of the first temperature zone and the working temperature of the second temperature zone reach the corresponding set temperature at the same time. The working temperature of the gallium source in the first temperature zone is 550℃~650℃; the working temperature of the substrate in the second temperature zone is 700℃~1050℃. Step 6.5: When the working temperature of the reaction boat in the first temperature zone and the working temperature of the substrate in the second temperature zone in the quartz tube reach the set temperature, open the O2 gas path to allow the inert gas to carry O2 into the quartz reaction tube; set the growth time to 1h~3h to deposit an intrinsic β-Ga2O3 thin film on the substrate. Step 6.6: After the intrinsic β-Ga2O3 thin film growth is completed, close the O2 gas path and SiH4 gas path and cool down to complete the preparation of the intrinsic β-Ga2O3 heteroepitaxial layer. Step 7: Deposit AlO on the intrinsic β-Ga2O3 heteroepitaxial layer obtained in step 6. x film; In step 7, atomic layer deposition (ALD) technology is used, with Al(CH3)3 and H2O as precursors, and the deposition temperature is 100℃~350℃. Step 8, the AlO obtained in step 7 x SiN deposition on thin film x Thin film; In step 8, plasma-enhanced chemical vapor deposition (PECVD) is used with SiH4 and NH3 as gas sources, the temperature of the n-type silicon wafer is 200℃~500℃, and the radio frequency power is 3W~5W. Step 9: Fabricate a back electrode on the n-type polysilicon layer obtained in step 5; In step 9, the Ag back electrode is deposited by thermal evaporation when fabricating the back electrode on the n-type polysilicon layer. Step 10, the SiN obtained in step 8 x A top electrode is fabricated on the thin film, ultimately forming the Ga2O3 / Si TOPCon photovoltaic cell; In step 10, photolithography is first used to create an opening, and AlO at the top electrode location is removed by exposure and development. x and SiN x The top electrode of the Ga2O3 / SiTOPCon photovoltaic cell is then deposited using an electron beam evaporation coating machine to form the Ti / Pd / Ag stacked layer.

Images