A fully differential ring amplifier circuit and a fully differential ring amplifier thereof

Abstract

The present invention provides a fully differential ring amplifier circuit and a fully differential ring amplifier thereof, relating to the technical field of ring amplifiers. A first amplifying stage unit adopts common-mode feedback of a resistance detection type and an auto-zeroing technology, thereby increasing the bandwidth of the overall ring amplifier and better maintaining the static operating point in the amplifying region without generating offset. A second amplifying stage unit adopts a MOS tube biased in a linear region as a resistor and an adaptive bias fusion technology, thereby improving the circuit's anti-PVT characteristics and dynamically biasing the third amplifying stage unit. A cascode structure is adopted in the third amplifying stage unit to increase the output resistance, thereby increasing the circuit gain and improving the precision of the fully differential ring amplifier. While ensuring circuit stability, the overall precision and bandwidth of the fully differential ring amplifier are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of ring amplifiers, and more particularly, to a fully differential ring amplifier circuit and a fully differential ring amplifier thereof. Background Art

[0002] The ring amplifier is a new amplifier structure that has emerged in recent years. Its compatibility with advanced processes has made it a hot topic of research. The open-loop gain of a ring amplifier is obtained by multiplying the gains of three inverters, resulting in impressive open-loop gain. However, it also has some drawbacks, such as instability. However, continuous improvements in its structure have also improved loop stability.

[0003] Currently, ring amplifier architectures are primarily divided into two types: single-ended input and single-ended output. While this architecture offers a wide bandwidth, it also carries the drawbacks of single-ended structures, such as poor common-mode rejection, high even-order harmonic distortion, and weak noise immunity. The other is a fully differential architecture. While this architecture offers slightly smaller bandwidth and lower precision, it offers better common-mode rejection and enhanced noise immunity. Currently, however, no ring amplifier exists that combines the advantages of both architectures. Therefore, balancing bandwidth and precision in fully differential ring amplifier circuits presents a significant challenge in circuit design. Summary of the Invention

[0004] To address the problem that current ring amplifiers cannot balance circuit bandwidth, accuracy, and other performance issues, the present invention proposes a fully differential ring amplifier circuit and its fully differential ring amplifier. In the first amplification stage unit, common-mode feedback and auto-zeroing technology using resistor detection are adopted; in the second amplification stage unit, a MOS tube biased in the linear region is used as a resistor and adaptive bias fusion technology is used; and in the third amplification stage unit, a cascode structure is adopted. This ensures circuit stability while increasing the overall accuracy and bandwidth of the ring amplifier.

[0005] In order to achieve the above technical effects, the technical solutions of the present invention are as follows:

[0006] A fully differential ring amplifier circuit comprises: a first amplifying stage unit and a common-mode feedback unit of the first amplifying stage unit, a second amplifying stage unit, a third amplifying stage unit, a full-circuit common-mode feedback circuit unit, a clock circuit unit, and a bias circuit unit;

[0007] The first amplifier stage unit and the common-mode feedback unit of the first amplifier stage unit include four stacked MOS tubes, and use resistance detection common-mode feedback and self-zeroing technology to output voltages VON1 and VOP1;

[0008] The second amplifier stage unit is connected to the output voltages VON1 and VOP1 of the first amplifier stage unit, and uses a MOS tube biased in a linear region as a resistor;

[0009] The third amplifier stage unit adopts a cascode structure, the third amplifier stage unit is connected to the second amplifier stage unit, and the MOS tube in the third amplifier stage unit is biased in the linear region by the MOS tube in the second amplifier stage unit to bias the MOS tube, outputting voltages VOUTN and VOUTP;

[0010] The input end of the full-circuit common-mode feedback circuit unit is connected to the output voltages VOUTN and VOUTP of the third amplifier stage unit, and the output end is connected to the first amplifier stage unit to provide voltage feedback for the first amplifier stage unit;

[0011] The clock circuit unit is connected to the first amplification stage unit and the full-circuit common-mode feedback circuit unit to control the working process of the full-differential ring amplifier;

[0012] The bias circuit unit is connected to the first amplifying stage unit and the second amplifying stage unit to provide a bias voltage for the first amplifying stage unit and the second amplifying stage unit.

[0013] This technical solution adopts common-mode feedback and self-zeroing technology of resistance detection in the first amplifier stage unit, adopts MOS tube biased in the linear region as a resistor and adaptive bias fusion technology in the second amplifier stage unit, and adopts cascode structure in the third amplifier stage unit. While ensuring circuit stability, it increases the overall accuracy and bandwidth of the ring amplifier.

[0014] Preferably, the first amplifier stage unit and the common-mode feedback unit of the first amplifier stage unit include MOS tubes MP1, MP2, MP3, MN1, MN2, MN3, MN4, transmission gates P1, P2, and resistors R1, R2; the gate of MP1 is connected to the bias circuit unit, the source of MP1 is connected to the operating voltage VDD, the drain of MP1 is connected to the source of MP2 and the source of MP3, the gate of MP2 is connected to the input VIN and the gate of MN1, the drain of MP2 is connected to the drain of MN1, the gate of MP3 is connected to the input VIP and the gate of MN2, the drain of MP3 is connected to the drain of MN2, the source of MN1 is connected to the source of MN2, the drain of MN4 and the drain of MN3, and the drain of MN3 is connected. The gate is connected to the full-circuit common-mode feedback circuit unit, the source of MN3 is connected to VSS, the gate of MN4 is connected to the full-circuit common-mode feedback circuit unit, the source of MN4 is connected to VSS, one end of the transmission gate P1 is connected to the input VIN, the other end of the transmission gate P1 and one end of the resistor R1 are connected to the first connection point a, the output voltage of the first connection point is VOP1, the upper and lower ends of P1 are respectively connected to the clock circuit unit, one end of the transmission gate P2 is connected to the input VIP, the other end of the transmission gate P2 and one end of the resistor R2 are connected to the second connection point b, the output voltage of the second connection point b is VON1, the upper and lower ends of P2 are respectively connected to the clock circuit unit, the other end of the resistor R1, the other end of the resistor R2 and the gate of MN4 are connected to the third connection point c.

[0015] Here, a common-mode feedback with resistance detection is adopted. Compared with the first amplifier stage unit of a traditional fully differential ring amplifier, the stacked MOS tubes are reduced from five to four, which speeds up the first amplifier stage unit and thus increases the bandwidth of the overall ring amplifier. In addition, the self-zeroing technology is adopted in the first amplifier stage unit, so that the static operating point is better maintained in the amplification range without offset.

[0016] Preferably, the second amplifier stage unit includes MOS tubes MP4, MP5, MP6, MP7, MP8, MP11, MP12, MP13, MP14, MP15, MN5, MN6, MN7, MN8, MN9, MN10, MN13, MN14, MN15, MN16, MN17, MN18, capacitors C1, C2, C3, C4, the gate of MP4 is connected to the clock circuit unit, the source of MP4 is connected to the bias circuit unit, the drain of MP4 is connected to the right plate of C1 and the gate of MP5, the source of MP5 is connected to VDD, the drain of MP5 is connected to the source of MP6 and the drain of MN5, the gate of MP6 is connected to the bias circuit unit, and the drain of MP6 is connected to the bias circuit unit. The drain is connected to the source of MN5, the drain of MN6 and the source of MP7, the gate of MP7 is connected to the bias circuit unit, the drain of MP7 is connected to the source of MN6, the drain of MN7 and the source of MP8, the gate of MP8 is connected to VBP2, the drain of MP8 is connected to the source of MN7 and the drain of MN8, the gate of MN5 is connected to the bias circuit unit, the gate of MN6 is connected to the bias circuit unit, the gate of MN7 is connected to the bias circuit unit, the gate of MN8 is connected to the clock circuit unit, the source of MN8 is connected to the drain of MN9, the gate of MN9 is connected to the source of MN10 and the right plate of C2, the source of MN9 is connected to VSS, the gate of MN10 is connected to the clock circuit unit, and the drain of MN10 is connected The bias circuit unit, the left plate of C1 is connected to the output VOP1 of the first amplifier stage unit, the left plate of C2 is connected to the output VOP1 of the first amplifier stage unit, the gate of MP11 is connected to the clock circuit unit, the source of MP11 is connected to the bias circuit unit, the drain of MP11 is connected to the right plate of C3 and the gate of MP12, the source of MP12 is connected to VDD, the drain of MP12 is connected to the source of MP13 and the drain of MN13, the gate of MP13 is connected to the bias circuit unit, the drain of MP13 is connected to the source of MN13, the drain of MN14 and the source of MP14, the gate of MP14 is connected to the bias circuit unit, the drain of MP14 is connected to the source of MN14, the drain of MN15 and the drain of MP15 The sources of the two transistors MN17 and MN18 are connected, the gate of MP15 is connected to the bias circuit unit, the drain of MP15 is connected to the source of MN15 and the drain of MN16, the gate of MN13 is connected to the bias circuit unit, the gate of MN14 is connected to the bias circuit unit, the gate of MN15 is connected to the bias circuit unit, the gate of MN16 is connected to the clock circuit unit, the source of MN16 is connected to the drain of MN17, the gate of MN17 is connected to the source of MN18 and the right plate of C4, the source of MN17 is connected to VSS, the gate of MN18 is connected to the clock circuit unit, the drain of MN18 is connected to the bias circuit unit, the left plate of C3 is connected to the output VON1 of the first amplifier stage unit, and the left plate of C4 is connected to the output VON1 of the first amplifier stage unit.

[0017] Here, a MOS transistor biased in the linear region is used to act as a resistor for biasing. The MOS transistor changes with the change of PVT, making the fully differential ring amplifier more stable.

[0018] Preferably, the third amplifier stage unit includes MOS transistors MP9, MP10, MP16, MP17, MN11, MN12, MN19, and MN20, wherein the gate of MP9 is connected to the drain of MP5, the source of MP9 is connected to VDD, the drain of MP9 is connected to the source of MP10, the gate of MP10 is connected to the drain of MP6, the drain of MP10 is connected to the drain of MN11 and outputs a voltage VOUTP, the gate of MN11 is connected to the drain of MP7, the source of MN11 is connected to the drain of MN12, and MN The gate of MP12 is connected to the drain of MP8, the source of MN12 is connected to VSS, the gate of MP16 is connected to the drain of MP12, the source of MP16 is connected to VDD, the drain of MP16 is connected to the source of MP17, the gate of MP17 is connected to the drain of MP13, the drain of MP17 is connected to the drain of MN19 and outputs the voltage VOUTP, the gate of MN19 is connected to the drain of MP14, the source of MN19 is connected to the drain of MN20, the gate of MN20 is connected to the drain of MP15, and the source of MN20 is connected to VSS.

[0019] Here, a cascode structure is adopted in the third amplifier stage unit and an adaptive bias technology is adopted in the second amplifier stage unit to bias the MOS transistor in the cascode structure of the third amplifier stage unit, thereby improving the open-loop gain of the ring amplifier and further improving the overall accuracy of the ring amplifier.

[0020] Preferably, the clock circuit unit includes clock 1, clock 1B, and clock 2; the clock 1 includes MOS transistors MP18 and MN21, the gates of MP18 and MN21 are connected to CLK1, CLK1 is connected to the gates of MN10 and MN18 in the second amplifier stage unit, the source of MP18 is connected to VDD, the drain of MP18 and the drain of MN21 are connected to CLK1b, and CLK1b is connected to the gates of MP4 and MP11 in the second amplifier stage unit;

[0021] The clock 1B includes MOS transistors MP19 and MN22. The gates of MP19 and MN22 are connected to CLK1B, which is connected to the lower ends of the transmission gates P1 and P2 in the first amplifier stage unit. The source of MP19 is connected to VDD. The drain of MP19 and MN22 are connected to CLK1Bb, which is connected to the upper ends of the transmission gates P1 and P2 in the first amplifier stage unit.

[0022] The clock 2 includes MOS transistors MP20 and MN23. The gates of MP20 and MN23 are connected to CLK2. CLK2 is connected to the gates of MN8 and MN16 in the second amplifier stage unit. The source of MP20 is connected to VDD. The drains of MP20 and MN23 are connected to CLK2b. The source of MN23 is connected to VSS.

[0023] Preferably, the full circuit common mode feedback circuit unit includes transmission gates P3, P4, P5, P6, and P7, capacitors C5 and C6, wherein the left end of P3 is connected to VOUTP, the right end of P3 is connected to the right end of P4 and the upper plate of C5, the upper end of P3 is connected to CLK2b, the lower end of P3 is connected to CLK2, the left end of P4 is externally connected to the common mode voltage VCM, the upper end of P4 is connected to CLK1b, the lower end of P4 is connected to CLK1, the left end of P5 is connected to VOUTN, the right end of P5 is connected to the right end of P6 and the lower plate of C6, and the upper end of P5 is connected to CL K2b, the lower end of P5 is connected to CLK2, the left end of P6 is externally connected to the common mode voltage VCM, the upper end of P6 is connected to CLK1b, the lower end of P6 is connected to CLK1, the left end of P7 is connected to the lower plate of C5 and the upper plate of C6 at the second connection point b, the feedback voltage of the fourth connection point d is VFB, VFB is connected to the gate of MN3 of the first amplifier stage unit, the upper end of P7 is connected to CLK1b, the lower end of P7 is connected to CLK1, the feedback voltage output by the right end of P7 is VFB1, and VFB1 is connected to the third connection point c of the first amplifier stage unit.

[0024] Preferably, the bias circuit unit includes MOS transistors MP21, MP22, MP23, MP24, MP25, MN24, MN25, MN26, and MN27, and a current source I1. The gate of MP21 is connected to the drain of MP21, the gate of MP22 is connected to one end of the current source I1, and the bias voltage across the gate of MP21 and the drain of MP21 is VBP1. VBP1 is connected to the gate of MP1 in the first amplifier stage unit and the gate of the second amplifier stage unit. The source of MP4 is connected to each other, the source of MP21 is connected to VDD, the other end of the current source I1 is connected to VSS, the source of MP22 is connected to VDD, the drain of MP22 is connected to the drain of MN24, the gate of MN25 and the gate of MN24, the gate of MP23 is connected to the drain of MP23 and the source of MP24, the source of MP23 is connected to VDD, the gate of MP24 is connected to the drain of MP24 and the drain of MN25, and the gate of MP24 is connected to the drain of MP24. The bias voltage is VBP2, VBP2 is connected to the gate of MP6, MP7, MP8, MP13, MP14 and MP15 in the second amplifier stage unit, the gate of MP25 is connected to VBP1, the source of MP25 is connected to VDD, the drain of MP25 is connected to the gate of MN26 and the drain of MN26, the source of MN24 is connected to VSS, the bias voltage across the gate and drain of MN24 is VBN1, VBN1 is connected to the first The drain of MN10 and the drain of MN18 in the second amplifier stage unit are connected, the source of MN25 is connected to VSS, the source of MN26 is connected to the gate of MN27 and the drain of MN27, the bias voltage across the gate of MN26 and the drain of MN26 is VBN2, VBN2 is connected to the gate of MN5, the gate of MN6, the gate of MN7, the gate of MN13, the gate of MN14, and the gate of MN15 in the second amplifier stage unit, and the source of MN27 is connected to VSS.

[0025] Preferably, when operating in the reset phase, clock 1 is at a high level, clock 1B is at a high level, and clock 2 is at a low level. Transmission gates P1, P2, P4, P6, and P7 are turned on, and P3 and P5 are turned off. The first amplifier stage unit performs a zero adjustment operation. MOS tubes MP4, MN10, MP11, and MN18 are turned on. The right plate of capacitor C1 is connected to the bias voltage VBP1, the right plate of capacitor C2 is connected to the bias voltage VBN1, the right plate of capacitor C3 is connected to the bias voltage VBP1, and the right plate of capacitor C4 is connected to the bias voltage VBN1. MOS tubes MN8 and MN16 are turned off, and the second amplifier stage unit and the third amplifier stage unit are in a turned-off state, which is conducive to saving power consumption.

[0026] Preferably, when operating in the amplification phase, when clock 1 is at a low level, clock 1B is at a low level, and clock 2 is at a high level, transmission gates P3 and P5 are turned on, P1, P2, P4, P6, and P7 are turned off, the gates of MOS transistors MN5, MN6, MN7, MN13, MN14, and MN15 are connected to VBN2 and are biased in the linear region to act as resistors, the gates of MOS transistors MP6, MP7, MP8, MP13, MP14, and MP15 are connected to VBP2 and are biased in the linear region to act as resistors, MOS transistors MN8 and MN16 are turned on, and the second amplification stage unit and the third amplification stage unit enter the working state.

[0027] The present invention further provides a fully differential ring amplifier, which includes the aforementioned fully differential ring amplifier circuit structure.

[0028] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0029] The present invention provides a fully differential ring amplifier circuit and a fully differential ring amplifier thereof. In the first amplifying stage unit, common-mode feedback of a resistance detection type and an auto-zeroing technology are adopted, thereby increasing the bandwidth of the overall ring amplifier and better maintaining the static operating point in the amplifying region without generating offset. In the second amplifying stage unit, a MOS tube biased in the linear region is used as a resistor and an adaptive bias fusion technology is adopted, thereby improving the anti-PVT characteristics of the circuit and dynamically biasing the third amplifying stage unit. In the third amplifying stage unit, a cascode structure is adopted to increase the output resistance, thereby increasing the circuit gain and improving the precision of the fully differential ring amplifier. While ensuring the stability of the circuit, the overall precision and bandwidth of the fully differential ring amplifier are increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic structural diagram showing a first amplifying stage unit and a common-mode feedback unit of the first amplifying stage unit of the fully differential ring amplifier circuit proposed in Embodiment 1 of the present invention;

[0031] Figure 2 A schematic diagram showing the structures of the second amplifying stage unit and the third amplifying stage unit of the fully differential ring amplifier circuit proposed in Embodiment 1 of the present invention;

[0032] Figure 3 A schematic diagram showing the structure of a clock circuit unit of the fully differential ring amplifier circuit proposed in Example 1 of the present invention;

[0033] Figure 4 A schematic diagram showing the structure of a full-circuit common-mode feedback circuit unit of a fully differential ring amplifier circuit proposed in Example 1 of the present invention;

[0034] Figure 5A schematic diagram showing the structure of a bias circuit unit of the fully differential ring amplifier circuit proposed in Example 1 of the present invention;

[0035] Figure 6 FIG. 2 is a timing diagram showing the operation of the fully differential ring amplifier circuit proposed in Embodiment 2 of the present invention;

[0036] Figure 7 A diagram showing a comparison between the fully differential ring amplifier proposed in Example 3 of the present invention and a conventional structure at the TT corner;

[0037] Figure 8 A diagram showing a comparison between the fully differential ring amplifier proposed in Example 3 of the present invention and a conventional structure under the SS corner;

[0038] Figure 9 A comparison diagram showing the fully differential ring amplifier proposed in Example 3 of the present invention and the traditional structure at the FF corner. DETAILED DESCRIPTION

[0039] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0040] In order to better illustrate this embodiment, some parts of the drawings may be omitted, enlarged, or reduced, and do not represent the actual size;

[0041] It is understandable to those skilled in the art that descriptions of certain well-known contents may be omitted in the drawings.

[0042] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0043] The positional relationships described in the drawings are for illustrative purposes only and should not be construed as limiting this patent;

[0044] Example 1

[0045] like Figures 1 to 5 As shown, this embodiment provides a fully differential ring amplifier circuit, including: a first amplifying stage unit and a common-mode feedback unit of the first amplifying stage unit, a second amplifying stage unit, a third amplifying stage unit, a full-circuit common-mode feedback circuit unit, a clock circuit unit, and a bias circuit unit;

[0046] The first amplifier stage unit and the common-mode feedback unit of the first amplifier stage unit include four stacked MOS tubes, and use resistance detection common-mode feedback and self-zeroing technology to output voltages VON1 and VOP1;

[0047] The second amplifier stage unit is connected to the output voltages VON1 and VOP1 of the first amplifier stage unit, and uses a MOS tube biased in a linear region as a resistor;

[0048] The third amplifier stage unit adopts a cascode structure, the third amplifier stage unit is connected to the second amplifier stage unit, and the MOS tube in the third amplifier stage unit is biased in the linear region by the MOS tube in the second amplifier stage unit to bias the MOS tube, outputting voltages VOUTN and VOUTP;

[0049] The input end of the full-circuit common-mode feedback circuit unit is connected to the output voltages VOUTN and VOUTP of the third amplifier stage unit, and the output end is connected to the first amplifier stage unit to provide voltage feedback for the first amplifier stage unit;

[0050] The clock circuit unit is connected to the first amplification stage unit and the full-circuit common-mode feedback circuit unit to control the working process of the full-differential ring amplifier;

[0051] The bias circuit unit is connected to the first amplifying stage unit and the second amplifying stage unit to provide a bias voltage for the first amplifying stage unit and the second amplifying stage unit.

[0052] In this embodiment, if Figure 1 As shown, the first amplifier stage unit and the common-mode feedback unit of the first amplifier stage unit include MOS tubes MP1, MP2, MP3, MN1, MN2, MN3, MN4, transmission gates P1, P2, and resistors R1, R2; the gate of MP1 is connected to the bias circuit unit, the source of MP1 is connected to the operating voltage VDD, the drain of MP1 is connected to the source of MP2 and the source of MP3, the gate of MP2 is connected to the input VIN and the gate of MN1, the drain of MP2 is connected to the drain of MN1, the gate of MP3 is connected to the input VIP and the gate of MN2, the drain of MP3 is connected to the drain of MN2, the source of MN1 is connected to the source of MN2, the drain of MN4 and the drain of MN3, and the gate of MN3 is connected to the input VIN and the gate of MN1. The electrodes are connected to the full-circuit common-mode feedback circuit unit, the source of MN3 is connected to VSS, the gate of MN4 is connected to the full-circuit common-mode feedback circuit unit, the source of MN4 is connected to VSS, one end of the transmission gate P1 is connected to the input VIN, the other end of the transmission gate P1 and one end of the resistor R1 are connected to the first connection point a, the output voltage of the first connection point is VOP1, the upper and lower ends of P1 are respectively connected to the clock circuit unit, one end of the transmission gate P2 is connected to the input VIP, the other end of the transmission gate P2 and one end of the resistor R2 are connected to the second connection point b, the output voltage of the second connection point b is VON1, the upper and lower ends of P2 are respectively connected to the clock circuit unit, the other end of the resistor R1, the other end of the resistor R2 and the gate of MN4 are connected to the third connection point c.

[0053] In this embodiment, if Figure 2As shown, the second amplifier stage unit includes MOS tubes MP4, MP5, MP6, MP7, MP8, MP11, MP12, MP13, MP14, MP15, MN5, MN6, MN7, MN8, MN9, MN10, MN13, MN14, MN15, MN16, MN17, MN18, capacitors C1, C2, C3, C4, the gate of MP4 is connected to the clock circuit unit, the source of MP4 is connected to the bias circuit unit, the drain of MP4 is connected to the right plate of C1 and the gate of MP5, the source of MP5 is connected to VDD, the drain of MP5 is connected to the source of MP6 and the drain of MN5, the gate of MP6 is connected to the bias circuit unit, the drain of MP6 is connected to the source of MN5 The gate of MN5 is connected to the bias circuit unit, the drain of MN6 is connected to the source of MP7, the gate of MP7 is connected to the bias circuit unit, the drain of MP7 is connected to the source of MN6, the drain of MN7 and the source of MP8, the gate of MP8 is connected to VBP2, the drain of MP8 is connected to the source of MN7 and the drain of MN8, the gate of MN5 is connected to the bias circuit unit, the gate of MN6 is connected to the bias circuit unit, the gate of MN7 is connected to the bias circuit unit, the gate of MN8 is connected to the clock circuit unit, the source of MN8 is connected to the drain of MN9, the gate of MN9 is connected to the source of MN10 and the right plate of C2, the source of MN9 is connected to VSS, the gate of MN10 is connected to the clock circuit unit, the drain of MN10 is connected to the bias circuit unit, and the left plate of C1 is connected to the first The output VOP1 of the first amplifier stage unit, the left plate of C2 is connected to the output VOP1 of the first amplifier stage unit, the gate of MP11 is connected to the clock circuit unit, the source of MP11 is connected to the bias circuit unit, the drain of MP11 is connected to the right plate of C3 and the gate of MP12, the source of MP12 is connected to VDD, the drain of MP12 is connected to the source of MP13 and the drain of MN13, the gate of MP13 is connected to the bias circuit unit, the drain of MP13 is connected to the source of MN13, the drain of MN14 and the source of MP14, the gate of MP14 is connected to the bias circuit unit, the drain of MP14 is connected to the source of MN14, the drain of MN15 and the source of MP15, the gate of MP15 is connected to the bias circuit unit, The drain of P15 is connected to the source of MN15 and the drain of MN16, the gate of MN13 is connected to the bias circuit unit, the gate of MN14 is connected to the bias circuit unit, the gate of MN15 is connected to the bias circuit unit, the gate of MN16 is connected to the clock circuit unit, the source of MN16 is connected to the drain of MN17, the gate of MN17 is connected to the source of MN18 and the right plate of C4, the source of MN17 is connected to VSS, the gate of MN18 is connected to the clock circuit unit, the drain of MN18 is connected to the bias circuit unit, the left plate of C3 is connected to the output VON1 of the first amplifier stage unit, and the left plate of C4 is connected to the output VON1 of the first amplifier stage unit, which speeds up the first amplifier stage unit, thereby increasing the bandwidth of the overall ring amplifier.And in the static operating point, it is better to stay in the amplification area without offset. The MOS tube biased in the linear area is used as a resistor for biasing. The MOS tube changes with the change of PVT, making the fully differential ring amplifier more stable.

[0054] In this embodiment, if Figure 2 As shown, the third amplifier stage unit includes MOS tubes MP9, MP10, MP16, MP17, MN11, MN12, MN19, and MN20. The gate of MP9 is connected to the drain of MP5, the source of MP9 is connected to VDD, the drain of MP9 is connected to the source of MP10, the gate of MP10 is connected to the drain of MP6, the drain of MP10 is connected to the drain of MN11 and outputs the voltage VOUTP, the gate of MN11 is connected to the drain of MP7, the source of MN11 is connected to the drain of MN12, the gate of MN12 is connected to the drain of MP8, and the gate of MN11 is connected to the drain of MP7. The source of MP2 is connected to VSS, the gate of MP16 is connected to the drain of MP12, the source of MP16 is connected to VDD, the drain of MP16 is connected to the source of MP17, the gate of MP17 is connected to the drain of MP13, the drain of MP17 is connected to the drain of MN19 and outputs the voltage VOUTP, the gate of MN19 is connected to the drain of MP14, the source of MN19 is connected to the drain of MN20, the gate of MN20 is connected to the drain of MP15, and the source of MN20 is connected to VSS, thereby improving the open-loop gain of the ring amplifier circuit, thereby improving the overall accuracy of the ring amplifier circuit.

[0055] In this embodiment, if Figure 3 As shown, the clock circuit unit includes clock 1, clock 1B, and clock 2; the clock 1 includes MOS transistors MP18 and MN21, the gates of MP18 and MN21 are connected to CLK1, CLK1 is connected to the gates of MN10 and MN18 in the second amplifier stage unit, the source of MP18 is connected to VDD, the drain of MP18 and the drain of MN21 are connected to CLK1b, CLK1b is connected to the gates of MP4 and MP11 in the second amplifier stage unit;

[0056] The clock 1B includes MOS transistors MP19 and MN22. The gates of MP19 and MN22 are connected to CLK1B, which is connected to the lower ends of the transmission gates P1 and P2 in the first amplifier stage unit. The source of MP19 is connected to VDD. The drain of MP19 and MN22 are connected to CLK1Bb, which is connected to the upper ends of the transmission gates P1 and P2 in the first amplifier stage unit.

[0057] The clock 2 includes MOS transistors MP20 and MN23. The gates of MP20 and MN23 are connected to CLK2. CLK2 is connected to the gates of MN8 and MN16 in the second amplifier stage unit. The source of MP20 is connected to VDD. The drains of MP20 and MN23 are connected to CLK2b. The source of MN23 is connected to VSS.

[0058] In this embodiment, if Figure 4 As shown, the full circuit common-mode feedback circuit unit includes transmission gates P3, P4, P5, P6, and P7, capacitors C5 and C6, wherein the left end of P3 is connected to VOUTP, the right end of P3 is connected to the right end of P4 and the upper plate of C5, the upper end of P3 is connected to CLK2b, the lower end of P3 is connected to CLK2, the left end of P4 is externally connected to the common-mode voltage VCM, the upper end of P4 is connected to CLK1b, the lower end of P4 is connected to CLK1, the left end of P5 is connected to VOUTN, the right end of P5 is connected to the right end of P6 and the lower plate of C6, and the upper end of P5 is connected to CL K2b, the lower end of P5 is connected to CLK2, the left end of P6 is externally connected to the common mode voltage VCM, the upper end of P6 is connected to CLK1b, the lower end of P6 is connected to CLK1, the left end of P7 is connected to the lower plate of C5 and the upper plate of C6 at the second connection point b, the feedback voltage of the fourth connection point d is VFB, VFB is connected to the gate of MN3 of the first amplifier stage unit, the upper end of P7 is connected to CLK1b, the lower end of P7 is connected to CLK1, the feedback voltage output by the right end of P7 is VFB1, and VFB1 is connected to the third connection point c of the first amplifier stage unit.

[0059] In this embodiment, if Figure 5As shown, the bias circuit unit includes MOS transistors MP21, MP22, MP23, MP24, MP25, MN24, MN25, MN26, and MN27, and a current source I1. The gate of MP21 is connected to the drain of MP21, the gate of MP22 is connected to one end of the current source I1, and the bias voltage across the gate of MP21 and the drain of MP21 is VBP1. VBP1 is connected to the gate of MP1 in the first amplifier stage unit and the gate of MP22 in the second amplifier stage unit. The source of P4 is connected, the source of MP21 is connected to VDD, the other end of the current source I1 is connected to VSS, the source of MP22 is connected to VDD, the drain of MP22 is connected to the drain of MN24, the gate of MN25 and the gate of MN24, the gate of MP23 is connected to the drain of MP23 and the source of MP24, the source of MP23 is connected to VDD, the gate of MP24 is connected to the drain of MP24 and the drain of MN25, the gate of MP24 is connected to the drain of MP24 The bias voltage is VBP2, VBP2 is connected to the gate of MP6, MP7, MP8, MP13, MP14 and MP15 in the second amplifier stage unit, the gate of MP25 is connected to VBP1, the source of MP25 is connected to VDD, the drain of MP25 is connected to the gate of MN26 and the drain of MN26, the source of MN24 is connected to VSS, the bias voltage across the gate and drain of MN24 is VBN1, VBN1 is connected to the first The drain of MN10 and the drain of MN18 in the second amplifier stage unit are connected, the source of MN25 is connected to VSS, the source of MN26 is connected to the gate of MN27 and the drain of MN27, the bias voltage across the gate of MN26 and the drain of MN26 is VBN2, VBN2 is connected to the gate of MN5, the gate of MN6, the gate of MN7, the gate of MN13, the gate of MN14, and the gate of MN15 in the second amplifier stage unit, and the source of MN27 is connected to VSS.

[0060] Example 2

[0061] In this embodiment, when the fully differential ring amplifier circuit operates in the reset phase, clock 1 is at a high level, clock 1B is at a high level, and clock 2 is at a low level. Transmission gates P1, P2, P4, P6, and P7 are turned on, and P3 and P5 are turned off. The first amplifier stage unit performs a zero adjustment operation. MOS transistors MP4, MN10, MP11, and MN18 are turned on. The right plate of capacitor C1 is connected to bias voltage VBP1, the right plate of capacitor C2 is connected to bias voltage VBN1, the right plate of capacitor C3 is connected to bias voltage VBP1, and the right plate of capacitor C4 is connected to bias voltage VBN1. MOS transistors MN8 and MN16 are turned off, and the second and third amplifier stage units are in a turned-off state, thereby saving power consumption.

[0062] When the fully differential ring amplifier circuit operates in the amplification phase, see Figure 6When clock 1 is at a low level, clock 1B is at a low level, and clock 2 is at a high level, transmission gates P3 and P5 are turned on, P1, P2, P4, P6, and P7 are turned off, and the gates of MOS transistors MN5, MN6, MN7, MN13, MN14, and MN15 are connected to VBN2 and biased in the linear region to act as resistors. The gates of MOS transistors MP6, MP7, MP8, MP13, MP14, and MP15 are connected to VBP2 and biased in the linear region to act as resistors. MOS transistors MN8 and MN16 are turned on, and the second and third amplifier stage units enter the working state.

[0063] Example 3

[0064] The present invention further provides a fully differential ring amplifier, which includes the aforementioned fully differential ring amplifier circuit structure.

[0065] In this embodiment, based on TSMC 65nm, the input differential value is set to 10mV, and the closed-loop amplification factor is set to 32, that is, the output differential value is 320mV. Under the TT corner, the fully differential ring amplifier of this design outputs 320.165mV after 6ns of amplification, while the traditional fully differential ring amplifier outputs 314.162mV. Figure 7 As shown, the fully differential ring amplifier proposed in the present invention has higher accuracy at the TT corner than the traditional structure.

[0066] Under the SS corner, the output of the fully differential ring amplifier of this design is 321.87mV after 6ns of amplification, while the output of the traditional fully differential ring amplifier is 309.8746mV. Figure 8 As shown, the fully differential ring amplifier proposed in the present invention has higher accuracy in the SS corner compared with the traditional structure.

[0067] In the FF corner, the output of the fully differential ring amplifier of this design is 317.6506mV after 6ns of amplification, while the output of the traditional fully differential ring amplifier is 318.0165mV. Figure 9 As shown in FIG. 1 , the fully differential ring amplifier proposed in the present invention has similar accuracy to the traditional structure at the FF corner.

[0068] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A fully differential ring amplifier circuit, characterized in that: include: A first amplifying stage unit and a common-mode feedback unit of the first amplifying stage unit, a second amplifying stage unit, a third amplifying stage unit, a full-circuit common-mode feedback circuit unit, a clock circuit unit, and a bias circuit unit; The first amplifier stage unit and the common-mode feedback unit of the first amplifier stage unit include four stacked MOS tubes, and use resistance detection common-mode feedback and self-zeroing technology to output voltages VON1 and VOP1; The second amplifier stage unit is connected to the output voltages VON1 and VOP1 of the first amplifier stage unit, and uses a MOS tube biased in a linear region as a resistor; The third amplifier stage unit adopts a cascode structure, the third amplifier stage unit is connected to the second amplifier stage unit, and the MOS tube in the third amplifier stage unit is biased in the linear region by the MOS tube in the second amplifier stage unit to bias the MOS tube, outputting voltages VOUTN and VOUTP; The input end of the full-circuit common-mode feedback circuit unit is connected to the output voltages VOUTN and VOUTP of the third amplifier stage unit, and the output end is connected to the first amplifier stage unit to provide voltage feedback for the first amplifier stage unit; The clock circuit unit is connected to the first amplification stage unit and the full-circuit common-mode feedback circuit unit to control the working process of the full-differential ring amplifier; The bias circuit unit is connected to the first amplifying stage unit and the second amplifying stage unit to provide a bias voltage for the first amplifying stage unit and the second amplifying stage unit; The first amplifier stage unit and the common-mode feedback unit of the first amplifier stage unit include MOS tubes MP1, MP2, MP3, MN1, MN2, MN3, MN4, transmission gates P1 and P2, and resistors R1 and R2; the gate of MP1 is connected to the bias circuit unit, the source of MP1 is connected to the operating voltage VDD, the drain of MP1 is connected to the source of MP2 and the source of MP3, the gate of MP2 is connected to the input VIN and the gate of MN1, the drain of MP2 is connected to the drain of MN1, the gate of MP3 is connected to the input VIP and the gate of MN2, the drain of MP3 is connected to the drain of MN2, the source of MN1 is connected to the source of MN2, the drain of MN4 and the drain of MN3, and the gate of MN3 is connected. A full-circuit common-mode feedback circuit unit is connected, the source of MN3 is connected to VSS, the gate of MN4 is connected to the full-circuit common-mode feedback circuit unit, the source of MN4 is connected to VSS, one end of the transmission gate P1 is connected to the input VIN, the other end of the transmission gate P1 and one end of the resistor R1 are connected to the first connection point a, the output voltage of the first connection point is VOP1, the upper and lower ends of P1 are respectively connected to the clock circuit unit, one end of the transmission gate P2 is connected to the input VIP, the other end of the transmission gate P2 and one end of the resistor R2 are connected to the second connection point b, the output voltage of the second connection point b is VON1, the upper and lower ends of P2 are respectively connected to the clock circuit unit, the other end of the resistor R1, the other end of the resistor R2 and the gate of MN4 are connected to the third connection point c.

2. The fully differential ring amplifier circuit according to claim 1, wherein: The second amplifier stage unit includes MOS tubes MP4, MP5, MP6, MP7, MP8, MP11, MP12, MP13, MP14, MP15, MN5, MN6, MN7, MN8, MN9, MN10, MN13, MN14, MN15, MN16, MN17, MN18, capacitors C1, C2, C3, C4, the gate of MP4 is connected to the clock circuit unit, the source of MP4 is connected to the bias circuit unit, the drain of MP4 is connected to the right plate of C1 and the gate of MP5, the source of MP5 is connected to VDD, the drain of MP5 is connected to the source of MP6 and the drain of MN5, the gate of MP6 is connected to the bias circuit unit, the drain of MP6 is connected to The source of MN5, the drain of MN6 and the source of MP7 are connected, the gate of MP7 is connected to the bias circuit unit, the drain of MP7 is connected to the source of MN6, the drain of MN7 and the source of MP8, the gate of MP8 is connected to VBP2, the drain of MP8 is connected to the source of MN7 and the drain of MN8, the gate of MN5 is connected to the bias circuit unit, the gate of MN6 is connected to the bias circuit unit, the gate of MN7 is connected to the bias circuit unit, the gate of MN8 is connected to the clock circuit unit, the source of MN8 is connected to the drain of MN9, the gate of MN9 is connected to the source of MN10 and the right plate of C2, the source of MN9 is connected to VSS, the gate of MN10 is connected to the clock circuit unit, and the drain of MN10 is connected to the bias circuit unit. Circuit unit, the left plate of C1 is connected to the output VOP1 of the first amplifier stage unit, the left plate of C2 is connected to the output VOP1 of the first amplifier stage unit, the gate of MP11 is connected to the clock circuit unit, the source of MP11 is connected to the bias circuit unit, the drain of MP11 is connected to the right plate of C3 and the gate of MP12, the source of MP12 is connected to VDD, the drain of MP12 is connected to the source of MP13 and the drain of MN13, the gate of MP13 is connected to the bias circuit unit, the drain of MP13 is connected to the source of MN13, the drain of MN14 and the source of MP14, the gate of MP14 is connected to the bias circuit unit, the drain of MP14 is connected to the source of MN14, the drain of MN15 and the source of MP15 The gate of MP15 is connected to the bias circuit unit, the drain of MP15 is connected to the source of MN15 and the drain of MN16, the gate of MN13 is connected to the bias circuit unit, the gate of MN14 is connected to the bias circuit unit, the gate of MN15 is connected to the bias circuit unit, the gate of MN16 is connected to the clock circuit unit, the source of MN16 is connected to the drain of MN17, the gate of MN17 is connected to the source of MN18 and the right plate of C4, the source of MN17 is connected to VSS, the gate of MN18 is connected to the clock circuit unit, the drain of MN18 is connected to the bias circuit unit, the left plate of C3 is connected to the output VON1 of the first amplifying stage unit, and the left plate of C4 is connected to the output VON1 of the first amplifying stage unit.

3. The fully differential ring amplifier circuit according to claim 2, wherein: The third amplifier stage unit includes MOS tubes MP9, MP10, MP16, MP17, MN11, MN12, MN19, and MN20. The gate of MP9 is connected to the drain of MP5, the source of MP9 is connected to VDD, the drain of MP9 is connected to the source of MP10, the gate of MP10 is connected to the drain of MP6, the drain of MP10 is connected to the drain of MN11 and outputs a voltage VOUTP, the gate of MN11 is connected to the drain of MP7, the source of MN11 is connected to the drain of MN12, and MN12 is connected to the drain of MP6. The gate of MP16 is connected to the drain of MP12, the source of MP16 is connected to VDD, the drain of MP16 is connected to the source of MP17, the gate of MP17 is connected to the drain of MP13, the drain of MP17 is connected to the drain of MN19 and outputs the voltage VOUTP, the gate of MN19 is connected to the drain of MP14, the source of MN19 is connected to the drain of MN20, the gate of MN20 is connected to the drain of MP15, and the source of MN20 is connected to VSS.

4. The fully differential ring amplifier circuit according to claim 3, wherein: The clock circuit unit includes clock 1, clock 1B, and clock 2; the clock 1 includes MOS transistors MP18 and MN21, the gates of MP18 and MN21 are connected to CLK1, CLK1 is connected to the gates of MN10 and MN18 in the second amplifier stage unit, the source of MP18 is connected to VDD, the drain of MP18 and the drain of MN21 are connected to CLK1b, CLK1b is connected to the gates of MP4 and MP11 in the second amplifier stage unit; The clock 1B includes MOS transistors MP19 and MN22. The gates of MP19 and MN22 are connected to CLK1B, which is connected to the lower ends of the transmission gates P1 and P2 in the first amplifier stage unit. The source of MP19 is connected to VDD. The drain of MP19 and MN22 are connected to CLK1Bb, which is connected to the upper ends of the transmission gates P1 and P2 in the first amplifier stage unit. The clock 2 includes MOS transistors MP20 and MN23. The gates of MP20 and MN23 are connected to CLK2. CLK2 is connected to the gates of MN8 and MN16 in the second amplifier stage unit. The source of MP20 is connected to VDD. The drains of MP20 and MN23 are connected to CLK2b. The source of MN23 is connected to VSS.

5. The fully differential ring amplifier circuit according to claim 4, wherein: The full-circuit common-mode feedback circuit unit includes transmission gates P3, P4, P5, P6, and P7, and capacitors C5 and C6, wherein the left end of P3 is connected to VOUTP, the right end of P3 is connected to the right end of P4 and the upper plate of C5, the upper end of P3 is connected to CLK2b, the lower end of P3 is connected to CLK2, the left end of P4 is externally connected to the common-mode voltage VCM, the upper end of P4 is connected to CLK1b, the lower end of P4 is connected to CLK1, the left end of P5 is connected to VOUTN, the right end of P5 is connected to the right end of P6 and the lower plate of C6, and the upper end of P5 is connected to CLK2 b, the lower end of P5 is connected to CLK2, the left end of P6 is connected to the common mode voltage VCM, the upper end of P6 is connected to CLK1b, the lower end of P6 is connected to CLK1, the left end of P7 is connected to the lower plate of C5 and the upper plate of C6 at the second connection point b, the feedback voltage of the fourth connection point d is VFB, VFB is connected to the gate of MN3 of the first amplifier stage unit, the upper end of P7 is connected to CLK1b, the lower end of P7 is connected to CLK1, the feedback voltage output by the right end of P7 is VFB1, and VFB1 is connected to the third connection point c of the first amplifier stage unit.

6. The fully differential ring amplifier circuit according to claim 5, wherein: The bias circuit unit includes MOS tubes MP21, MP22, MP23, MP24, MP25, MN24, MN25, MN26, and MN27, and a current source I1. The gate of MP21 is connected to the drain of MP21, the gate of MP22 is connected to one end of the current source I1, and the bias voltage between the gate of MP21 and the drain of MP21 is VBP1. VBP1 is connected to the gate of MP1 in the first amplifier unit and the gate of MP4 in the second amplifier unit. The source of MP21 is connected to VDD, the other end of the current source I1 is connected to VSS, the source of MP22 is connected to VDD, the drain of MP22 is connected to the drain of MN24, the gate of MN25 and the gate of MN24, the gate of MP23 is connected to the drain of MP23 and the source of MP24, the source of MP23 is connected to VDD, the gate of MP24 is connected to the drain of MP24 and the drain of MN25, and the gate of MP24 is connected to the bias of both ends of the drain of MP24 The voltage is VBP2, VBP2 is connected to the gate of MP6, MP7, MP8, MP13, MP14 and MP15 in the second amplifier stage unit, the gate of MP25 is connected to VBP1, the source of MP25 is connected to VDD, the drain of MP25 is connected to the gate of MN26 and the drain of MN26, the source of MN24 is connected to VSS, the bias voltage across the gate and drain of MN24 is VBN1, VBN1 is connected to the second The drain of MN10 and the drain of MN18 in the amplifier stage unit are connected, the source of MN25 is connected to VSS, the source of MN26 is connected to the gate of MN27 and the drain of MN27, the bias voltage across the gate of MN26 and the drain of MN26 is VBN2, VBN2 is connected to the gate of MN5, the gate of MN6, the gate of MN7, the gate of MN13, the gate of MN14, and the gate of MN15 in the second amplifier stage unit, and the source of MN27 is connected to VSS.

7. The fully differential ring amplifier circuit according to claim 6, wherein: When working in the reset phase, clock 1 is high, clock 1B is high, and clock 2 is low. Transmission gates P1, P2, P4, P6, and P7 are turned on, and P3 and P5 are turned off. The first amplifier stage unit performs a zero adjustment operation. MOS tubes MP4, MN10, MP11, and MN18 are turned on. The right plate of capacitor C1 is connected to bias voltage VBP1, the right plate of capacitor C2 is connected to bias voltage VBN1, the right plate of capacitor C3 is connected to bias voltage VBP1, and the right plate of capacitor C4 is connected to bias voltage VBN1. MOS tubes MN8 and MN16 are turned off, and the second and third amplifier stage units are in the off state.

8. The fully differential ring amplifier circuit according to claim 6, wherein: When working in the amplification phase, when clock 1 is low, clock 1B is low, and clock 2 is high, transmission gates P3 and P5 are turned on, P1, P2, P4, P6, and P7 are turned off, the gates of MOS transistors MN5, MN6, MN7, MN13, MN14, and MN15 are connected to VBN2 and are biased in the linear region to act as resistors, the gates of MOS transistors MP6, MP7, MP8, MP13, MP14, and MP15 are connected to VBP2 and are biased in the linear region to act as resistors, MOS transistors MN8 and MN16 are turned on, and the second amplification stage unit and the third amplification stage unit enter the working state.

9. A fully differential ring amplifier, characterized in that: The fully differential ring amplifier includes the structure of the fully differential ring amplifier circuit according to any one of claims 1 to 8.

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