A gate voltage bootstrap switch circuit based on PMOS transistor

Abstract

The application provides a gate voltage bootstrap switch circuit based on a PMOS tube, wherein: the control end of a sampling switch tube is connected with the output end of a gate voltage bootstrap loop; the output end of a charge pump is connected with the input end of the gate voltage bootstrap loop; the sampling switch tube adopts a PMOS tube; the gate voltage bootstrap loop applies a constant voltage difference to a first capacitor in the gate voltage bootstrap loop in a holding stage according to a clock signal and a voltage signal provided by the charge pump, so that the sampling switch tube is in an off state; the sampling switch tube is controlled to be in an on state in a sampling stage, and the gate-source voltage of the sampling switch tube is kept as a preset value; that is, when the sampling switch tube is on, the gate electrode of the sampling switch tube can effectively follow the change of an input voltage, so that the on resistance of the switch does not change with the input voltage, the function of the gate voltage bootstrap is realized, and the influence of the sampling switch offset effect is suppressed; meanwhile, the circuit does not use an NMOS tube with an independent substrate end, so that the design can be applied to a standard N-well CMOS process.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and more specifically, relates to a gate voltage bootstrap switching circuit based on a PMOS transistor. Background Technology

[0002] With the continuous development of very large-scale integrated circuits (VLSI), signal processing using digital systems has become the mainstream technology in the field of signal processing. Signals generated in the real world, such as light, sound, temperature, and pressure, are all analog signals. Therefore, they need to be converted into digital signals before they can be transmitted to a digital system for signal processing. The ADC (Analog-to-Digital Converter) serves as a bridge connecting the real world and the digital world and is an indispensable key circuit module in modern electronic systems. As an important component of the ADC, the sampling switch's non-ideal factors directly affect the ADC's performance parameters.

[0003] The basic idea of ​​a gate-driven bootstrap switch is to charge the bootstrap capacitor with a constant voltage during the hold phase, and then connect the bootstrap capacitor across the gate and source of the switch during the sampling phase, so that the gate-source voltage of the switch does not change with the input voltage during the sampling phase. In standard N-well CMOS technology, PMOS transistors are located in their own independent N-wells and have independent substrate terminals; NMOS transistors share the P-substrate, therefore, NMOS transistors with independent substrate terminals are not provided in standard process libraries.

[0004] However, when using an NMOS transistor as the gate voltage bootstrap switch, the voltage difference between the input terminal and the substrate terminal of the NMOS transistor causes the substrate bias effect of the NMOS transistor to cause its threshold voltage to change with the input voltage, resulting in the on-resistance of the switch changing with the input voltage. This will produce a certain degree of nonlinearity. In other words, the NMOS transistor in the standard N-well CMOS process does not have an independent substrate terminal, and the above circuit cannot be guaranteed to achieve the gate voltage bootstrap function. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a gate-voltage bootstrap switching circuit based on a PMOS transistor, which performs gate-voltage bootstrap function and suppresses the substrate bias effect caused by using an NMOS transistor as a switching transistor. At the same time, it does not use an NMOS transistor with an independent substrate end, so that the design can be applied to standard N-well CMOS process.

[0006] This application discloses a gate voltage bootstrap switching circuit based on a PMOS transistor, including: a sampling switch transistor, a gate voltage bootstrap circuit, and a charge pump;

[0007] The control terminal of the sampling switch is connected to the output terminal of the gate voltage bootstrap circuit;

[0008] The input terminal of the sampling switch is connected to the input terminal of the gate voltage bootstrap switch circuit;

[0009] The output terminal of the sampling switch is connected to the output terminal of the gate voltage bootstrap switch circuit; wherein, the sampling switch is a PMOS transistor;

[0010] The output terminal of the charge pump is connected to the input terminal of the gate voltage bootstrap circuit;

[0011] Both the gate voltage bootstrap circuit and the charge pump are powered by a power source and receive a clock signal.

[0012] The charge pump provides a voltage signal to the gate voltage bootstrap circuit according to the clock signal, so that the gate voltage bootstrap circuit applies a constant voltage difference to the first capacitor in the gate voltage bootstrap circuit during the holding phase, so that the sampling switch is in the off state; and controls the sampling switch to be in the on state during the sampling phase, and the gate-source voltage of the sampling switch is maintained at a preset value.

[0013] Optionally, the gate voltage bootstrap circuit includes: a first capacitor, a first switch, a second switch, and a fourth switch;

[0014] The first terminal of the first switching transistor is connected to the input terminal of the gate voltage bootstrap switching circuit;

[0015] The control terminal of the first switch transistor serves as the first input terminal of the gate voltage bootstrap circuit and is connected to the first output terminal of the charge pump.

[0016] The second end of the first switching transistor is connected to the substrate of the first switching transistor, the first end of the second switching transistor, and the lower electrode of the first capacitor, respectively.

[0017] The control terminal of the second switch is connected to the second terminal of the fourth switch, the substrate of the fourth switch, and the power supply, respectively.

[0018] The first terminal of the fourth switching transistor is connected to the upper plate of the first capacitor.

[0019] The control terminal of the fourth switch receives the clock signal;

[0020] The upper plate of the first capacitor serves as the output terminal of the gate voltage bootstrap circuit;

[0021] The second terminal of the second switch transistor serves as the second input terminal of the gate voltage bootstrap circuit and is connected to the second output terminal of the charge pump.

[0022] The substrate of the second switch is connected to the second terminal of the second switch.

[0023] Optionally, the gate voltage bootstrap circuit further includes: a third switching transistor;

[0024] The first terminal of the third switching transistor is connected to the upper plate of the first capacitor;

[0025] The second end of the third switch is connected to the first end of the fourth switch;

[0026] The control terminal of the third switch is grounded.

[0027] Optionally, the charge pump includes: a second capacitor, a first inverter, a seventh switch, an eighth switch, a tenth switch, and an eleventh switch;

[0028] The first terminal of the seventh switch and the substrate of the seventh switch are both connected to the power supply;

[0029] The control terminal of the seventh switch is connected to the first terminal of the eighth switch and the first terminal of the eleventh switch, respectively, and the connection point serves as the first output terminal of the charge pump.

[0030] The second terminal of the seventh switch is connected to the second terminal of the eighth switch, the substrate of the eighth switch, and the upper plate of the second capacitor, respectively, and the connection point serves as the second output terminal of the charge pump.

[0031] The lower plate of the second capacitor is connected to the first terminal of the first inverter, and the connection point receives the clock signal.

[0032] The power supply terminal of the first inverter is connected to the power supply, and the ground terminal of the first inverter is grounded.

[0033] The second terminal of the first inverter is connected to the control terminal of the eleventh switch and the control terminal of the eighth switch, respectively.

[0034] The second terminal of the eleventh switch is grounded.

[0035] Optionally, the charge pump further includes: a twelfth switching transistor;

[0036] The first terminal of the twelfth switch is connected to the control terminal of the seventh switch and the first terminal of the eighth switch, respectively, and the connection point serves as the first output terminal of the charge pump.

[0037] The control terminal of the twelfth switching transistor is connected to the power supply.

[0038] The second terminal of the twelfth switch is connected to the first terminal of the eleventh switch.

[0039] Optionally, the first inverter includes: a sixth switch and a tenth switch;

[0040] The first end of the sixth switch is connected to the substrate of the sixth switch, and the connection point serves as the power supply terminal of the first inverter.

[0041] The control terminal of the sixth switch is connected to the control terminal of the tenth switch, and the connection point serves as the first terminal of the first inverter.

[0042] The second end of the sixth switch is connected to the first end of the tenth switch, and the connection point serves as the second end of the first inverter.

[0043] The second terminal of the tenth switch is used as the ground terminal of the first inverter.

[0044] Optionally, the number of inverters in the charge pump is greater than 1.

[0045] Optionally, the charge pump further includes: a second inverter;

[0046] The second inverter is disposed between the first inverter and the clock signal;

[0047] The first terminal of the second inverter receives the clock signal;

[0048] The second terminal of the second inverter is connected to the first terminal of the first inverter and the lower plate of the second capacitor, respectively.

[0049] The ground terminal of the second inverter is grounded;

[0050] The power supply terminal of the second inverter is connected to a power source.

[0051] Optionally, the second inverter includes a fifth switch and a ninth switch;

[0052] The control terminal of the fifth switch is connected to the control terminal of the ninth switch, and the connection point serves as the first terminal of the second inverter.

[0053] The first end of the fifth switch is connected to the substrate of the fifth switch, and the connection point serves as the power supply terminal of the second inverter.

[0054] The second end of the fifth switch is connected to the first end of the ninth switch, and the connection point serves as the second end of the second inverter.

[0055] The second terminal of the ninth switch is used as the ground terminal of the inverter.

[0056] Optionally, the sampling switch, the first switch to the eighth switch are all PMOS transistors; the ninth switch to the twelfth switch are all NMOS transistors.

[0057] As can be seen from the above technical solution, the present invention provides a gate voltage bootstrap switching circuit based on a PMOS transistor, wherein: the control terminal of the sampling switch is connected to the output terminal of the gate voltage bootstrap circuit; the input and output terminals of the sampling switch are connected to the input and output terminals of the gate voltage bootstrap switching circuit; the output terminal of the charge pump is connected to the input terminal of the gate voltage bootstrap circuit; both the gate voltage bootstrap circuit and the charge pump are powered by a power supply and receive a clock signal; wherein, the sampling switch is a PMOS transistor; the charge pump is used to provide a voltage signal to the gate voltage bootstrap circuit according to the clock signal, so that the gate voltage bootstrap circuit can realize the control of the gate voltage bootstrap circuit during the holding phase according to the voltage signal and the clock signal. In the gate voltage bootstrap circuit, a constant voltage difference is applied to the first capacitor to keep the sampling switch in the off state; and during the sampling phase, the sampling switch is controlled to be in the on state, and the gate-source voltage of the sampling switch is kept at a preset value; that is, when the sampling switch is on, its gate can effectively follow the change of the input voltage, so that the on-resistance of the switch does not change with the input voltage, and the gate-source voltage is kept at a preset value, thus realizing the gate voltage bootstrap function and suppressing the substrate bias effect brought by the NMOS transistor as the switch. At the same time, this circuit does not use an NMOS transistor with an independent substrate end, so that the design can be applied to the standard N-well CMOS process. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of a PMOS transistor gate voltage bootstrap switching circuit provided by existing technology;

[0060] Figure 2 This is a schematic diagram of a gate voltage bootstrap switching circuit based on a PMOS transistor provided in an embodiment of the present invention;

[0061] Figure 3 This is a schematic diagram of another gate voltage bootstrap switching circuit based on a PMOS transistor provided in an embodiment of the present invention;

[0062] Figure 4 This is a schematic diagram of another gate voltage bootstrap switching circuit based on a PMOS transistor provided in an embodiment of the present invention;

[0063] Figure 5 This is another PMOS transistor-based gate voltage bootstrap switching circuit provided in this embodiment of the invention, showing the input and output sampling and holding waveform in a 180nm N-well CMOS process;

[0064] Figure 6This invention provides another gate-source voltage waveform sampling method based on a PMOS transistor in a 180nm N-well CMOS process.

[0065] Figure 7 This is a schematic diagram of the redundant switching transistors involved in a gate voltage bootstrap switching circuit based on a PMOS transistor provided by the present invention. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0068] The gate voltage bootstrap switching circuit based on PMOS transistors consists of a sampling switch transistor SW and a gate voltage bootstrap circuit. Figure 1 The diagram shows a gate-voltage bootstrap switch circuit using PMOS transistors as switches. The gate-voltage bootstrap circuit consists of a bootstrap capacitor C1 and the other PMOS transistors except for the sampling switch SW. During the hold phase, the clock signal CLK is low, switches MP2, MP3, and MN2 are turned on, switches MN1 and MP1 are turned off, and the sampling switch SW is turned off. Switches MN2 and MP2 charge the bootstrap capacitor C1 to VDD, storing the charge. During the sampling phase, the clock signal CLK is high, switches MN1 and MP1 are turned on, switches MP2, MP3, and MN2 are turned off, and the sampling switch SW is closed. Since the amount of charge stored in the bootstrap capacitor C1 remains constant, the gate voltage of the sampling switch SW is VIN-VDD through the circuit composed of switches MN1, MP1, and the bootstrap capacitor C1. The gate-source voltage of the sampling switch SW remains at -VDD, thus achieving the gate-voltage bootstrap function.

[0069] However, a drawback of this gate-voltage bootstrap switching circuit is that the NMOS transistors in the gate-voltage bootstrap loop must have independent substrate terminals to ensure the circuit functions correctly. During the sampling phase, the voltage across the upper plate of bootstrap capacitor C1 is VIN-VDD. If MN1 and MN2 do not have independent substrates and their substrates are both connected to ground, then when the input voltage is too low, the PN junction formed by the source and substrate of MN1 will be forward biased, and the PN junction formed by the drain and substrate of MN2 will also be forward biased. This will cause the voltage across the upper plate of bootstrap capacitor C1 to be fixed at -Vth during the sampling phase, resulting in the gate voltage of the sampling switch SW being fixed at -Vth. The gate-source voltage of the sampling switch SW will change with VIN, causing the on-resistance of the switch to change with the input voltage during the sampling phase, thus failing to achieve the gate-voltage bootstrap function. Therefore, the above circuit is not suitable for standard N-well CMOS technology, as the NMOS transistors in this technology do not have independent substrate terminals, making it impossible to guarantee the gate-voltage bootstrap function of the above circuit.

[0070] Based on this, this application provides a gate voltage bootstrap switch circuit based on a PMOS transistor to solve the problem in the prior art where an NMOS transistor is used as the switch transistor for gate voltage bootstrap switching. Due to the voltage difference between the input terminal and the substrate terminal of the NMOS transistor, the substrate bias effect of the NMOS transistor causes its threshold voltage to change with the input voltage, resulting in the on-resistance of the switch changing with the input voltage, which will produce a certain degree of nonlinearity. That is, the NMOS transistor under the standard N-well CMOS process does not have an independent substrate terminal, and the above circuit cannot guarantee the gate voltage bootstrap function.

[0071] This PMOS-based gate bootstrap switch circuit is suitable for use in standard N-well CMOS processes and suppresses the influence of substrate bias effect of the sampling switch.

[0072] See Figure 2 The gate-voltage bootstrap switching circuit based on PMOS transistors includes: a sampling switch transistor SW, a gate-voltage bootstrap circuit 20, and a charge pump 10.

[0073] The control terminal of the sampling switch SW is connected to the output terminal of the gate voltage bootstrap circuit 20.

[0074] In other words, the gate voltage bootstrap circuit 20 can control the on / off state of the sampling switch SW. If the gate voltage bootstrap circuit 20 outputs a first signal, the sampling switch SW is in the on state; if the gate voltage bootstrap circuit 20 outputs a second signal, the sampling switch SW is in the off state.

[0075] The specific forms of the first and second signals will not be elaborated here, but will be determined according to the actual situation, and are all within the scope of protection of this application.

[0076] The input terminal of the sampling switch SW is connected to the input terminal VIN of the gate voltage bootstrap switch circuit.

[0077] Specifically, the sampling switch SW receives input signals, such as input voltage.

[0078] The output terminal of the sampling switch SW is connected to the output terminal VOUT of the gate voltage bootstrap switch circuit.

[0079] The output signal of the sampling switch SW is used as the output signal of the gate voltage bootstrap switch circuit.

[0080] The sampling switch SW is a PMOS transistor.

[0081] In practical applications, redundant transistors can be added to either the signal input terminal VIN or the signal output terminal VOUT, such as... Figure 7 As shown, the sampling switch transistor is on the left (e.g., Figure 7 P0 is shown, and the right side is a redundant transistor (such as P0). Figure 7 P shown 0d The drain and source of the redundant transistor are shorted. The conduction state of the redundant transistor is opposite to that of the sampling switch SW, that is, the redundant transistor is cut off when the sampling switch SW is on, and the redundant transistor is on when the sampling switch SW is off. In this way, the redundant transistor can absorb the channel charge leaked when the sampling switch SW is off. Adding the redundant transistor does not change the function of the sampling switch SW.

[0082] Among them, g and g d These are the control signals received by the corresponding switching transistors, with Vin being the input voltage and Vout being the output voltage.

[0083] Figure 7 The example of adding a redundant transistor at the signal output terminal is used for demonstration. The same principle applies to adding a redundant transistor at the signal input terminal. It will not be elaborated here. It can be determined according to the actual situation. All of them are within the protection scope of this application.

[0084] The output terminal of charge pump 10 is connected to the input terminal of gate voltage bootstrap circuit 20.

[0085] In other words, the charge pump 10 outputs a voltage signal to the gate voltage bootstrap circuit 20.

[0086] Both the gate voltage bootstrap circuit 20 and the charge pump 10 are powered by the power supply VDD and receive the clock signal CKL.

[0087] Specifically, the power supply terminal of the gate voltage bootstrap circuit 20 is connected to the power supply VDD; the power supply terminal of the charge pump 10 is connected to the power supply VDD.

[0088] The signal terminal of the gate voltage bootstrap circuit 20 receives the clock signal CKL; the signal terminal of the charge pump 10 receives the clock signal CKL.

[0089] The charge pump 10 provides a voltage signal to the gate voltage bootstrap circuit 20 according to the clock signal CKL, so that the gate voltage bootstrap circuit applies a constant voltage difference to the first capacitor C1 in the gate voltage bootstrap circuit 20 during the holding phase, so that the sampling switch SW is in the off state; and during the sampling phase, it controls the sampling switch SW to be in the on state, and the gate-source voltage of the sampling switch SW is maintained at a preset value.

[0090] In other words, the gate voltage bootstrap circuit 20 is used to control the conduction state of the sampling switch SW and the charging and discharging of the first capacitor C1. Specifically, during the holding phase, a constant voltage difference is applied to the first capacitor C1, where the voltage of the upper plate of the first capacitor C1 is VDD and the voltage of the lower plate of the first capacitor C1 is 2*VDD, and the sampling switch SW is turned off; during the sampling phase, the sampling switch SW is turned on and its gate-source voltage does not change with the input voltage, thus realizing the gate voltage bootstrap function.

[0091] The charge pump 10 is used to control the charging and discharging of the second capacitor C2, and to control the conduction state of the first switch MP1 in the gate voltage bootstrap circuit 20, and to provide the 2*VDD voltage signal required by the gate voltage bootstrap circuit 20. During the sampling phase, a constant voltage difference is applied to the second capacitor C2, wherein the voltage of the upper plate of the second capacitor C2 is VDD and the voltage of the lower plate of the second capacitor C2 is ground voltage VSS, so that the first switch MP1 is turned on; during the holding phase, the voltage of the upper plate of the second capacitor C2 is made to 2*VDD through charge redistribution, and the first switch MP1 is turned off.

[0092] In practical applications, when the clock signal CKL is low, the gate voltage bootstrap switch circuit is in the hold phase. When the clock signal CKL is high, the gate voltage bootstrap switch circuit is in the sampling phase.

[0093] In this embodiment, the control terminal of the sampling switch SW is connected to the output terminal of the gate bootstrap circuit 20; the input and output terminals of the sampling switch SW are connected to the input and output terminals of the gate bootstrap switching circuit; the output terminal of the charge pump 10 is connected to the input terminal of the gate bootstrap circuit 20; both the gate bootstrap circuit 20 and the charge pump 10 are powered by the power supply VDD and receive the clock signal CKL; wherein, the sampling switch is a PMOS transistor; the charge pump 10 is used to provide a voltage signal to the gate bootstrap circuit 20 according to the clock signal CKL, so that the gate bootstrap circuit can realize the gate bootstrap circuit 20 in the holding phase according to the voltage signal and the clock signal CKL. A constant voltage difference is applied to the first capacitor C1 in step 0, keeping the sampling switch SW in the off state; and during the sampling phase, the sampling switch SW is controlled to be in the on state, and the gate-source voltage of the sampling switch SW is kept at a preset value; that is, when the sampling switch SW is on, its gate can effectively follow the change of the input voltage, so that the on-resistance of the switch does not change with the input voltage, and the gate-source voltage is kept at a preset value, realizing the gate voltage bootstrap function and suppressing the substrate bias effect brought by the NMOS transistor as a switch. At the same time, this circuit does not use an NMOS transistor with an independent substrate end, making the design applicable to standard N-well CMOS process.

[0094] In practical applications, such as Figure 3 As shown, the gate voltage bootstrap circuit 20 includes: a first capacitor C1, a first switch MP1, a second switch MP2, and a fourth switch MP4.

[0095] The first terminal of the first switching transistor MP1 is connected to the input terminal VIN of the gate voltage bootstrap switching circuit.

[0096] Specifically, the first terminal of the first switching transistor MP1 receives input signals, such as input voltage.

[0097] The control terminal of the first switching transistor MP1 serves as the first input terminal of the gate voltage bootstrap circuit 20 and is connected to the first output terminal of the charge pump 10.

[0098] Specifically, the control terminal of the first switch MP1 is connected to the control terminal of the seventh switch MP7, the first terminal of the eighth switch MP8, and the first terminal of the twelfth switch MN4.

[0099] The second terminal of the first switching transistor MP1 is connected to the substrate of the first switching transistor MP1, the first terminal of the second switching transistor MP2, and the lower plate of the first capacitor C1.

[0100] The control terminal of the second switch MP2 is connected to the second terminal of the fourth switch MP4, the substrate of the fourth switch MP4, and the power supply VDD, respectively.

[0101] The first terminal of the fourth switching transistor MP4 is connected to the upper plate of the first capacitor C1.

[0102] The control terminal of the fourth switching transistor MP4 receives the clock signal CKL.

[0103] Specifically, the switching on and off of the fourth switch MP4 is controlled by the clock signal CKL. If the clock signal CKL is high, the fourth switch MP4 is turned on; if the clock signal CKL is low, the fourth switch MP4 is turned off.

[0104] The upper plate of the first capacitor C1 serves as the output terminal of the gate voltage bootstrap circuit 20 and is connected to the control terminal of the sampling switch SW.

[0105] The second terminal of the second switch MP2 serves as the second input terminal of the gate voltage bootstrap circuit 20 and is connected to the second output terminal of the charge pump 10.

[0106] Specifically, the second terminal of the second switch MP2 is connected to the second terminal of the seventh switch MP7, the second terminal of the eighth switch MP8, and the substrate, respectively.

[0107] The substrate of the second switch MP2 is connected to the second terminal of the second switch MP2.

[0108] In practical applications, see Figure 2 The gate voltage bootstrap circuit 20 also includes a third switching transistor MP3.

[0109] The first terminal of the third switch MP3 is connected to the upper plate of the first capacitor C1; the second terminal of the third switch MP3 is connected to the first terminal of the fourth switch MP4; the control terminal of the third switch MP3 is grounded.

[0110] In other words, the gate voltage bootstrap circuit 20 includes: a first capacitor C1, a first switch MP1, a second switch MP2, a third switch MP3, and a fourth switch MP4.

[0111] The first terminal of the first switching transistor MP1 is connected to the input terminal VIN of the gate voltage bootstrap switching circuit.

[0112] In other words, the first terminal of the first switching transistor MP1 and the input terminal of the sampling switching transistor SW are both connected to the input terminal VIN of the gate voltage bootstrap switching circuit.

[0113] The control terminal of the first switching transistor MP1 serves as the first input terminal of the gate voltage bootstrap circuit 20 and is connected to the first output terminal of the charge pump 10.

[0114] Specifically, the control terminal of the first switch MP1 is connected to the control terminal of the seventh switch MP7, the first terminal of the eighth switch MP8, and the first terminal of the twelfth switch MN4.

[0115] The second terminal of the first switching transistor MP1 is connected to the substrate of the first switching transistor MP1, the first terminal of the second switching transistor MP2, and the lower plate of the first capacitor C1.

[0116] The control terminal of the second switch MP2 is connected to the substrate of the third switch MP3 and the power supply VDD, respectively.

[0117] The second terminal of the second switch MP2 serves as the second input terminal of the gate voltage bootstrap circuit 20 and is connected to the second output terminal of the charge pump 10.

[0118] Specifically, the second terminal of the second switch MP2 is connected to the second terminal of the seventh switch MP7, the second terminal of the eighth switch MP8, and the substrate, respectively.

[0119] The substrate of the second switch MP2 is connected to the second terminal of the second switch MP2.

[0120] The control terminal of the second switch MP2 and the control terminal of the third switch MP3 are grounded to VSS.

[0121] The first terminal of the third switching transistor MP3 is connected to the upper plate of the first capacitor C1.

[0122] The second terminal of the third switch MP3 is connected to the first terminal of the fourth switch MP4.

[0123] The control terminal of the fourth switching transistor MP4 receives the clock signal CKL.

[0124] The substrate of the fourth switching transistor MP4 is connected to the second terminal of the fourth switching transistor MP4, and the connection point is connected to the power supply VDD.

[0125] The upper plate of the first capacitor C1 serves as the output of the gate voltage bootstrap circuit 20.

[0126] Specifically, the upper plate of the first capacitor C1 is connected to the control terminal of the sampling switch transistor SW.

[0127] It should be noted that the third switch, MP3, is normally on, so it can be omitted. The function of the third switch, MP3, is to protect the fourth switch, MP4, from damage caused by excessive drain-source voltage during operation. If a high-voltage process is used, the third switch, MP3, can be omitted.

[0128] Specifically, the gate voltage bootstrap circuit 20 is used to control the conduction state of the sampling switch SW and the charging and discharging of the first capacitor C1. The following explains the high and low levels of the clock signal CKL:

[0129] (1) When the clock signal CKL is low, the third switch MP3 and the fourth switch MP4 are turned on. The gate of the sampling switch SW is connected to the power supply VDD through the third switch MP3 and the fourth switch MP4, causing the sampling switch SW to be turned off. The gate voltage bootstrap switch circuit is in the holding phase. At the same time, the upper plate of the first capacitor C1 is connected to the power supply VDD through the third switch MP3 and the fourth switch MP4. The voltage of the upper plate of the second capacitor C2 in the charge pump 10 is raised to 2*VDD. The upper plate of the second capacitor C2 is connected to the drain of the second switch MP2, causing the second switch MP2 to turn on. When the circuit is open, the upper plate of the second capacitor C2 is connected to the lower plate of the first capacitor C1 through the second switch MP2, and charge redistribution occurs. Since the total charge stored in the first capacitor C1 and the second capacitor C2 is VDD*(C1+C2), the voltage of the lower plate of the second capacitor C2 is VDD, and the voltage of the upper plate of the first capacitor C1 is VDD, after charge redistribution, the voltage of the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 are both 2*VDD. A voltage difference of VDD is formed between the lower plate and the upper plate of the first capacitor C1, and the first capacitor C1 stores a charge of VDD*C1.

[0130] It should be noted that the control terminal of the sampling switch SW and the first to eighth switches MP1 are all gates, the first terminal of each switch is the source, and the second terminal of each switch is the drain. The control terminal of the ninth to twelfth switches MN4 are all gates, the second terminal of each switch is the source, and the first terminal of each switch is the drain.

[0131] That is, when the clock signal CKL is low, the fourth switch MP4 is turned on, the fifth switch MP5 and the tenth switch MN2 are turned on, and the gate of the eighth switch MP8 is grounded to VSS, thus turning on the eighth switch MP8. The lower plate of the second capacitor C2 is connected to the working voltage VDD. Since the charge stored in the second capacitor C2 is VDD*C2, the voltage on the upper plate of the second capacitor C2 is raised to 2*VDD, thus turning off the first switch MP1 and the seventh switch MP7. The upper plate of the second capacitor C2 is simultaneously connected to the drain of the second switch MP2, turning on the second switch MP2. Thus, the upper plate of the second capacitor C2 is connected to the first capacitor C through the second switch MP2. The lower plate of capacitor C1 undergoes charge redistribution. Since the total charge stored in the first capacitor C1 and the second capacitor C2 is VDD*(C1+C2), the voltage of the lower plate of the second capacitor C2 is VDD, and the voltage of the upper plate of the first capacitor C1 is VDD, after charge redistribution, the voltage of the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 are both 2*VDD. Thus, a voltage difference of VDD is formed between the lower and upper plates of the first capacitor C1, and the first capacitor C1 stores a charge of VDD*C1. The gate of the sampling switch SW is connected to VDD through the third switch MP3 and the fourth switch MP4, thereby turning off the sampling switch SW and putting the gate voltage bootstrap switching circuit in the holding phase.

[0132] (2) When the clock signal CKL is high, the second switch MP2 is off, the fourth switch MP4 is off, and the eleventh switch MN3 and the twelfth switch MN4 are on. The gate of the first switch MP1 is grounded to VSS through the eleventh switch MN3 and the twelfth switch MN4, thus turning on the first switch MP1. The lower plate of the first capacitor C1 is connected to the input voltage VIN through the first switch MP1. The charge stored in the first capacitor C1 is VDD*C1. According to the principle of charge conservation, the voltage of the upper plate of the first capacitor C1 is VIN-VDD. It is also connected to the gate of the sampling switch SW. The sampling switch SW is on, and its gate-source voltage is -VDD. The gate voltage bootstrap switching circuit is in the sampling stage. The gate-source voltage of the sampling switch SW is kept at -VDD, realizing the gate voltage bootstrap function.

[0133] That is, when the clock signal CKL is high, the fourth switch MP4 is off, the ninth switch MN1, the eleventh switch MN3 and the sixth switch MP6 are on, the gate of the eighth switch MP8 is connected to VDD, thus turning off the eighth switch MP8. The gates of the first switch MP1 and the seventh switch MP7 are grounded to VSS through the eleventh switch MN3 and the twelfth switch MN4, thus turning on the first switch MP1 and the seventh switch MP7. The upper plate of the second capacitor C2 is connected to VDD through the seventh switch MP7. The drain of transistor MP2 is connected to the upper plate of the second capacitor C2, thus turning off the second switch MP2. A voltage difference of VDD is formed between the upper and lower plates of the second capacitor C2, storing a charge of VDD*C2. Since the first switch MP1 is on and the first capacitor C1 stores a charge of VDD*C1, the voltage at the upper plate of the first capacitor C1 is VIN-VDD. Simultaneously, the gate of the sampling switch SW is connected, turning on the sampling switch SW. Its gate-source voltage is -VDD, and the gate voltage bootstrap switching circuit is in the sampling phase. The gate-source voltage of the sampling switch SW remains at -VDD, realizing the gate voltage bootstrap function. Furthermore, the substrates of the NMOS transistors used in this design are all connected to ground, therefore this circuit is suitable for standard N-well CMOS technology.

[0134] In practical applications, see Figure 4 The charge pump 10 includes: a second capacitor C2, a first inverter, a seventh switch MP7, an eighth switch MP8, a tenth switch MN2, and an eleventh switch MN3.

[0135] The first terminal of the seventh switch MP7 and the substrate of the seventh switch MP7 are both connected to the power supply VDD.

[0136] The control terminal of the seventh switch MP7 is connected to the first terminal of the eighth switch MP8 and the first terminal of the eleventh switch MN3, respectively, and the connection point serves as the first output terminal of the charge pump 10.

[0137] The second terminal of the seventh switch MP7 is connected to the second terminal of the eighth switch MP8, the substrate of the eighth switch MP8, and the upper plate of the second capacitor C2, respectively. The connection point serves as the second output terminal of the charge pump 10.

[0138] The lower plate of the second capacitor C2 is connected to the first terminal of the first inverter, and the connection point receives the clock signal CKL.

[0139] The power supply terminal of the first inverter is connected to the power supply VDD, and the ground terminal of the first inverter is grounded to VSS.

[0140] The second terminal of the first inverter is connected to the control terminal of the eleventh switch MN3 and the control terminal of the eighth switch MP8, respectively.

[0141] The second terminal of the eleventh switch MN3 is grounded to VSS.

[0142] In practical applications, the charge pump 10 also includes a twelfth switching transistor MN4.

[0143] The first terminal of the twelfth switch MN4 is connected to the control terminal of the seventh switch MP7 and the first terminal of the eighth switch MP8, respectively, and the connection point serves as the first output terminal of the charge pump 10; the control terminal of the twelfth switch MN4 is connected to the power supply; the second terminal of the twelfth switch MN4 is connected to the first terminal of the eleventh switch MN3.

[0144] That is, the charge pump 10 includes: a second capacitor C2, a first inverter, a seventh switch MP7, an eighth switch MP8, a tenth switch MN2, an eleventh switch MN3, and a twelfth switch MN4.

[0145] The first terminal of the seventh switch MP7 and the substrate of the seventh switch MP7 are both connected to the power supply VDD.

[0146] The control terminal of the seventh switch MP7 is connected to the first terminal of the eighth switch MP8 and the first terminal of the twelfth switch MN4, respectively, and the connection point serves as the first output terminal of the charge pump 10.

[0147] The second terminal of the seventh switch MP7 is connected to the second terminal of the eighth switch MP8, the substrate of the eighth switch MP8, and the upper plate of the second capacitor C2, respectively. The connection point serves as the third terminal of the charge pump 10.

[0148] The lower plate of the second capacitor C2 is connected to the first terminal of the first inverter, and the connection point receives the clock signal CKL.

[0149] The power supply terminal of the first inverter is connected to the power supply VDD, and the ground terminal of the first inverter is grounded to VSS.

[0150] The second terminal of the first inverter is connected to the control terminal of the eleventh switch MN3 and the control terminal of the eighth switch MP8, respectively.

[0151] The control terminal of the twelfth switching transistor MN4 is connected to the power supply VDD.

[0152] The second terminal of the twelfth switch MN4 is connected to the first terminal of the eleventh switch MN3.

[0153] The second terminal of the eleventh switch MN3 is grounded to VSS.

[0154] The twelfth switch MN4 is always on. The function of the twelfth switch MN4 is to protect the eleventh switch MN3 and prevent the eleventh switch MN3 from being damaged due to excessive source-drain voltage during operation.

[0155] If a high-voltage process is used, the twelfth switching transistor MN4 can be omitted.

[0156] In practical applications, the first inverter includes: the sixth switch MP6 and the tenth switch MN2.

[0157] The first terminal of the sixth switch MP6 is connected to the substrate of the sixth switch MP6, and the connection point serves as the power supply terminal of the first inverter.

[0158] The control terminal of the sixth switch transistor MP6 is connected to the control terminal of the tenth switch transistor MN2, and the connection point serves as the first terminal of the first inverter.

[0159] The second terminal of the sixth switch MP6 is connected to the first terminal of the tenth switch MN2, and the connection point serves as the second terminal of the first inverter.

[0160] The second terminal of the tenth switch MN2 serves as the ground VSS terminal of the first inverter.

[0161] It should be noted that when the charge pump 10 only includes the first inverter, the charge pump receives the inverted clock signal CKL.

[0162] In practical applications, the number of inverters in charge pump 10 is greater than 1.

[0163] In practical applications, see Figure 2 The charge pump 10 also includes a second inverter.

[0164] The second inverter is positioned between the first inverter and the clock signal CKL.

[0165] The first terminal of the second inverter receives the clock signal CKL.

[0166] The second terminal of the second inverter is connected to the first terminal of the first inverter and the lower plate of the second capacitor C2.

[0167] The grounding terminal VSS of the second inverter is grounded.

[0168] The power supply terminal of the second inverter is connected to the power supply VDD.

[0169] In practical applications, the second inverter includes: the fifth switch MP5 and the ninth switch MN1.

[0170] The control terminal of the fifth switch MP5 is connected to the control terminal of the ninth switch MN1, and the connection point serves as the first terminal of the second inverter.

[0171] The first terminal of the fifth switch MP5 is connected to the substrate of the fifth switch MP5, and the connection point serves as the power supply terminal of the second inverter.

[0172] The second terminal of the fifth switch MP5 is connected to the first terminal of the ninth switch MN1, and the connection point serves as the second terminal of the second inverter.

[0173] The second terminal of the ninth switch MN1 serves as the ground VSS terminal of the inverter.

[0174] When the charge pump 10 includes two stages of inverters, the clock signal CKL received by the charge pump.

[0175] Specifically, the number of inverter stages is added or removed at the clock input CLK, so there must be at least one inverter. In this application, the fifth switch MP5 and the ninth switch MN1 constitute the first-stage inverter, and the sixth switch MP6 and the tenth switch MN2 constitute the second-stage inverter. The output of the first-stage inverter, composed of the fifth switch and the ninth switch MN1, is connected to the lower plate of the second capacitor C2 and to the input of the second-stage inverter, composed of the sixth switch MP6 and the tenth switch MN2. The output of the second-stage inverter is inverted compared to the output of the first-stage inverter, and the output of the second-stage inverter is connected to the control terminals of the eighth switch MP8 and the eleventh switch MN3 to control the on / off state of the eighth switch MP8 and the eleventh switch MN3.

[0176] Adding or removing the number of inverter stages at the clock input CLK changes the clock phase without altering the phase relationship and connection relationship of the outputs of the two inverter stages, thus not changing the essential function of the charge pump 10. The first-stage inverter of the charge pump 10 is omitted and an inverted clock signal CKL is applied, without changing the essential function of the charge pump 10.

[0177] Charge pump 10 is used to control the charging and discharging of the second capacitor C2, control the conduction state of the first switch MP1 in the gate voltage bootstrap circuit 20, and provide the 2*VDD voltage signal required by the gate voltage bootstrap circuit 20. When the clock signal CKL is high, the ninth switch MN1, the eleventh switch MN3 and the sixth switch MP6 are turned on, the gate of the eighth switch MP8 is connected to VDD, thereby turning off the eighth switch MP8, the gate of the seventh switch MP7 is grounded to VSS through the eleventh switch MN3 and the twelfth switch MN4, thereby turning on the seventh switch MP7, the upper plate of the second capacitor C2 is connected to VDD through the seventh switch MP7, and the lower plate of the second capacitor C2 is grounded to VSS through the ninth switch MN1. Then, a voltage difference of VDD is formed between the upper plate and the lower plate of the second capacitor C2, the second capacitor C2 stores the charge of VDD*C2, and the second capacitor C2 will... The gate of the first switching transistor MP1 is grounded to VSS through the eleventh switching transistor MN3 and the twelfth switching transistor MN4, thus turning on the first switching transistor MP1. When the clock signal CKL is low, the fifth switching transistor MP5 and the tenth switching transistor MN2 are turned on, and the gate of the eighth switching transistor MP8 is grounded to VSS, thus turning on the eighth switching transistor MP8. The lower plate of the second capacitor C2 is connected to the working voltage VDD. Since the charge stored in the second capacitor C2 is VDD*C2, the voltage of the upper plate of the second capacitor C2 is raised to 2*VDD. The gate of the first PMOS transistor MP1 is connected to the upper plate of the second capacitor C2 through the eighth switching transistor MP8, thus turning off the first switching transistor MP1.

[0178] In practical applications, the first switch MP1 to the eighth switch MP8 are all PMOS transistors. The ninth switch MN1 to the twelfth switch MN4 are all NMOS transistors.

[0179] In this embodiment, a PMOS transistor is used as the sampling switch SW. Utilizing the independent substrate terminal of the PMOS transistor in the aforementioned process, the substrate of the sampling switch SW is connected to the input terminal, suppressing the substrate bias effect when the sampling switch SW is turned on, thus improving the linearity and accuracy of the gate voltage bootstrap switch. Based on the charging and discharging of the first capacitor C1 and the second capacitor C2 by the PMOS transistor, through the charge redistribution between the first capacitor C1 and the second capacitor C2, the gate of the switch can effectively follow the changes in the input voltage when the switch is turned on, ensuring that the on-resistance of the switch does not change with the input voltage. This solves the bootstrap failure problem that currently exists in gate voltage bootstrap switch circuits using PMOS transistors in standard N-well CMOS processes.

[0180] In other words, by charging and discharging the two bootstrap capacitors through the PMOS transistor and redistributing the charge between the two bootstrap capacitors, the gate of the PMOS switch can effectively follow the changes in the input voltage when it is turned on, thus realizing the gate voltage bootstrap function and suppressing the substrate bias effect caused by the NMOS transistor as a switch. At the same time, without using an NMOS transistor with an independent substrate end, this design can be applied to standard N-well CMOS process.

[0181] The following example illustrates the connection relationship between specific devices in the gate voltage bootstrap circuit 20 and the charge pump 10:

[0182] The gate of the first PMOS transistor MP1 is connected to the gate of the seventh PMOS transistor MP7. The source of the first PMOS transistor MP1 is connected to the input voltage VIN. The drain and substrate of the first PMOS transistor MP1 are both connected to the lower plate of the first capacitor C1.

[0183] The gate of the second PMOS transistor MP2 is connected to the operating voltage VDD, the source of the second PMOS transistor MP2 is connected to the lower plate of the first capacitor C1, and the drain and substrate of the second PMOS transistor MP2 are both connected to the drain of the eighth PMOS transistor MP8.

[0184] The gate of the third PMOS transistor MP3 is connected to ground voltage VSS, the source of the third PMOS transistor MP3 is connected to the upper plate of the first capacitor C1, the drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4, and the substrate of the third PMOS transistor MP3 is connected to the operating voltage VDD.

[0185] The gate of the fourth PMOS transistor MP4 is connected to the clock signal CKL, and the drain and substrate of the fourth PMOS transistor MP4 are both connected to the operating voltage VDD.

[0186] The gate of the fifth PMOS transistor MP5 is connected to the clock signal CKL, the source and substrate of the fifth PMOS transistor MP5 are both connected to the operating voltage VDD, and the drain of the fifth PMOS transistor MP5 is connected to the drain of the first NMOS transistor MN1.

[0187] The gate of the sixth PMOS transistor MP6 is connected to the lower plate of the second capacitor C2. The source and substrate of the sixth PMOS transistor MP6 are both connected to the working voltage VDD. The drain of the sixth PMOS transistor MP6 is connected to the drain of the second NMOS transistor MN2.

[0188] The gate of the seventh PMOS transistor MP7 is connected to the source of the eighth PMOS transistor MP8. The source and substrate of the seventh PMOS transistor MP7 are both connected to the operating voltage VDD. The drain of the seventh PMOS transistor MP7 is connected to the upper plate of the second capacitor C2.

[0189] The source of the eighth PMOS transistor MP8 is connected to the drain of the fourth NMOS transistor MN4, the drain of the eighth PMOS transistor MP8 is connected to the drain of the seventh PMOS transistor MP7, and the substrate of the eighth PMOS transistor MP8 is connected to the drain of the eighth PMOS transistor MP8.

[0190] The gate of the sampling switch SW is connected to the upper plate of the first capacitor C1, the source and substrate of the sampling switch SW are connected to the input voltage VIN, and the drain of the sampling switch SW is connected to the output voltage VOUT.

[0191] The gate of the first NMOS transistor MN1 is connected to the clock signal CKL, the source of the first NMOS transistor MN1 is connected to the ground voltage VSS, and the drain of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2.

[0192] The gate of the second NMOS transistor MN2 is connected to the gate of the sixth PMOS transistor MP6, the source of the second NMOS transistor MN2 is connected to ground voltage VSS, and the drain of the second NMOS transistor MN2 is connected to the gate of the third NMOS transistor MN3.

[0193] The gate of the third NMOS transistor MN3 is connected to the gate of the eighth PMOS transistor MP8, the source of the third NMOS transistor MN3 is connected to ground voltage VSS, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, and the gate of the fourth NMOS transistor MN4 is connected to the operating voltage VDD.

[0194] Specifically, the substrates of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all connected to the ground voltage VSS.

[0195] The upper plate of the first capacitor C1 is connected to the gate of the sampling switch SW and the source of the third PMOS transistor MP3. The lower plate of the first capacitor C1 is connected to the drain of the first PMOS transistor MP1 and the substrate, and the source of the second PMOS transistor.

[0196] The upper plate of the second capacitor C2 is connected to the drain of the seventh PMOS transistor MP7, the drain of the eighth PMOS transistor MP8 and the substrate, the drain of the second PMOS transistor MP2 and the substrate. The lower plate of the second capacitor C2 is connected to the drain of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2, the drain of the fifth PMOS transistor MP5 and the gate of the sixth PMOS transistor MP6.

[0197] The effectiveness of this circuit is explained below:

[0198] This design uses 180nm N-well CMOS technology and is simulated on the Cadence platform. The effectiveness of the gate voltage bootstrap switching circuit is verified by sample and hold, that is, whether the input signal can be sampled and held, and the gate-source voltage of the switch SW does not change with the input voltage during the sampling phase. Figure 5 This is the input and output sampling and holding waveform of the gate voltage bootstrap switching circuit of the present invention. Figure 6 This is the operating waveform of the gate-source voltage of the sampling switch SW in the circuit of this invention. With a clock frequency of 6kHz, a power supply VDD voltage of 1.8V, and a load of 1pF, the gate-source voltage of the circuit remains at -1.69V during the sampling phase, realizing the gate voltage bootstrap function and sampling and holding of the input signal. For different clock frequencies, power supply VDD voltages, and loads, the aspect ratio of the transistor can be adjusted to meet the application requirements under different conditions.

[0199] The features described in the various embodiments of this specification can be substituted for or combined with each other. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0200] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0201] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gate-voltage bootstrap switching circuit based on a PMOS transistor, characterized in that, include: Sampling switch transistor, gate voltage bootstrap circuit, and charge pump; The control terminal of the sampling switch is connected to the output terminal of the gate voltage bootstrap circuit; The input terminal of the sampling switch is connected to the input terminal of the gate voltage bootstrap switch circuit; The output terminal of the sampling switch is connected to the output terminal of the gate voltage bootstrap switch circuit; wherein, the sampling switch is a PMOS transistor; The output terminal of the charge pump is connected to the input terminal of the gate voltage bootstrap circuit; Both the gate voltage bootstrap circuit and the charge pump are powered by a power source and receive a clock signal. The charge pump provides a voltage signal to the gate voltage bootstrap circuit according to the clock signal, so that the gate voltage bootstrap circuit applies a constant voltage difference to the first capacitor in the gate voltage bootstrap circuit during the holding phase, so that the sampling switch is in the off state; and during the sampling phase, the sampling switch is controlled to be in the on state, and the gate-source voltage of the sampling switch is maintained at a preset value. The gate voltage bootstrap circuit includes: a first capacitor, a first switch, a second switch, and a fourth switch; the first switch, the second switch, and the fourth switch are all PMOS transistors. The first terminal of the first switching transistor is connected to the input terminal of the gate voltage bootstrap switching circuit; The control terminal of the first switch transistor serves as the first input terminal of the gate voltage bootstrap circuit and is connected to the first output terminal of the charge pump. The second end of the first switching transistor is connected to the substrate of the first switching transistor, the first end of the second switching transistor, and the lower electrode of the first capacitor, respectively. The control terminal of the second switch is connected to the second terminal of the fourth switch, the substrate of the fourth switch, and the power supply, respectively. The first terminal of the fourth switching transistor is connected to the upper plate of the first capacitor. The control terminal of the fourth switch receives the clock signal; The upper plate of the first capacitor serves as the output terminal of the gate voltage bootstrap circuit; The second terminal of the second switch transistor serves as the second input terminal of the gate voltage bootstrap circuit and is connected to the second output terminal of the charge pump. The substrate of the second switch is connected to the second terminal of the second switch.

2. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 1, characterized in that, The gate voltage bootstrap circuit further includes: a third switch; the third switch is a PMOS transistor; The first terminal of the third switching transistor is connected to the upper plate of the first capacitor; The second end of the third switch is connected to the first end of the fourth switch; The control terminal of the third switch is grounded.

3. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 1, characterized in that, The charge pump includes: a second capacitor, a first inverter, a seventh switch, an eighth switch, a tenth switch, and an eleventh switch; the seventh and eighth switches are both PMOS transistors; the tenth and eleventh switches are both NMOS transistors. The first terminal of the seventh switch and the substrate of the seventh switch are both connected to the power supply; The control terminal of the seventh switch is connected to the first terminal of the eighth switch and the first terminal of the eleventh switch, respectively, and the connection point serves as the first output terminal of the charge pump. The second terminal of the seventh switch is connected to the second terminal of the eighth switch, the substrate of the eighth switch, and the upper plate of the second capacitor, respectively, and the connection point serves as the second output terminal of the charge pump. The lower plate of the second capacitor is connected to the first terminal of the first inverter, and the connection point receives the clock signal. The power supply terminal of the first inverter is connected to the power supply, and the ground terminal of the first inverter is grounded. The second terminal of the first inverter is connected to the control terminal of the eleventh switch and the control terminal of the eighth switch, respectively. The second terminal of the eleventh switch is grounded.

4. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 3, characterized in that, The charge pump further includes: a twelfth switching transistor; the twelfth switching transistor is an NMOS transistor; The first terminal of the twelfth switch is connected to the control terminal of the seventh switch and the first terminal of the eighth switch, respectively, and the connection point serves as the first output terminal of the charge pump. The control terminal of the twelfth switching transistor is connected to the power supply. The second terminal of the twelfth switch is connected to the first terminal of the eleventh switch.

5. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 3, characterized in that, The first inverter includes a sixth switch and a tenth switch; the sixth switch is a PMOS transistor and the tenth switch is an NMOS transistor. The first end of the sixth switch is connected to the substrate of the sixth switch, and the connection point serves as the power supply terminal of the first inverter. The control terminal of the sixth switch is connected to the control terminal of the tenth switch, and the connection point serves as the first terminal of the first inverter. The second end of the sixth switch is connected to the first end of the tenth switch, and the connection point serves as the second end of the first inverter. The second terminal of the tenth switch is used as the ground terminal of the first inverter.

6. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 3, characterized in that, The charge pump contains more than one inverter.

7. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 3, characterized in that, The charge pump further includes: a second inverter; The second inverter is disposed between the first inverter and the clock signal; The first terminal of the second inverter receives the clock signal; The second terminal of the second inverter is connected to the first terminal of the first inverter and the lower plate of the second capacitor, respectively. The ground terminal of the second inverter is grounded; The power supply terminal of the second inverter is connected to a power source.

8. The gate voltage bootstrap switching circuit based on a PMOS transistor according to claim 7, characterized in that, The second inverter includes a fifth switch and a ninth switch; the fifth switch is a PMOS transistor, and the ninth switch is an NMOS transistor. The control terminal of the fifth switch is connected to the control terminal of the ninth switch, and the connection point serves as the first terminal of the second inverter. The first end of the fifth switch is connected to the substrate of the fifth switch, and the connection point serves as the power supply terminal of the second inverter. The second end of the fifth switch is connected to the first end of the ninth switch, and the connection point serves as the second end of the second inverter. The second terminal of the ninth switch is used as the ground terminal of the inverter.

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