Analog-to-digital converter circuits in microcontrollers and their operation methods

Abstract

An analog-to-digital converter (ADC) circuit in a microcontroller and its operation method are disclosed. The ADC circuit includes a modulator, a filter, a synchronizer, and a processor. The modulator receives an analog signal and converts it into a first digital signal. The filter, coupled to the modulator, filters out noise outside the bandwidth of the first digital signal to generate a second digital signal. The synchronizer, coupled to the filter, frequency-modulates the second digital signal to generate a third digital signal. The processor, coupled to the synchronizer, performs digital signal processing on the third digital signal according to a cutoff frequency to generate a final digital signal. After receiving the second digital signal, the synchronizer sends an interrupt signal to the processor, which then performs digital signal processing based on the interrupt signal.

Description

Technical Field

[0001] This invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter circuit in a microcontroller and its operation method. Background Technology

[0002] With the increasing prevalence of sensors, the application of microcontrollers (MCUs) to convert analog signals into digital signals for processing has been increasing year by year. In some solutions requiring high-resolution signal conversion, the delta-Sigma (ΔΣ) analog-to-digital converter (ADC) is the preferred choice for high-resolution ADCs. The front-end circuit of the ΔΣ ADC converts the analog signal into a digital signal, shifts quantization noise to higher frequencies, and leaves the truly needed signal at lower frequencies. Then, the back-end circuit (filter) of the ΔΣ ADC filters out the high-frequency quantization noise, leaving the low-frequency signal.

[0003] However, the resolution of a ΔΣ ADC is directly proportional to the filter order, and the filter order is also directly proportional to the manufacturing cost of the ΔΣ ADC. Therefore, manufacturing a high-resolution ΔΣ ADC requires a considerable amount of circuit area (cost). Accordingly, how to design a ΔΣ ADC that saves circuit area while possessing high resolution and flexibility is one of the research topics for those skilled in the art. Summary of the Invention

[0004] This invention provides an analog-to-digital converter circuit and its operation method in a microcontroller, which can replace part of the filter to achieve the filtering effect by utilizing the built-in digital signal processing (DSP) function of the processor. This can save circuit area, improve resolution, and enhance the flexibility of the ADC circuit for various applications.

[0005] The analog-to-digital converter circuit in the microcontroller of this invention includes a modulator, a filter, a synchronizer, and a processor. The modulator receives an analog signal and converts it into a first digital signal. The filter, coupled to the modulator, filters out noise outside the bandwidth of the first digital signal to generate a second digital signal. The synchronizer, coupled to the filter, frequency-modulates the second digital signal to generate a third digital signal. The processor, coupled to the synchronizer, performs digital signal processing on the third digital signal according to a cutoff frequency to generate a final digital signal. After receiving the second digital signal, the synchronizer sends an interrupt signal to the processor, which then performs digital signal processing based on the interrupt signal.

[0006] The operation method of the analog-to-digital converter circuit in the microcontroller of the present invention includes: receiving an analog signal by a modulator and converting the analog signal into a first digital signal; filtering out noise outside the bandwidth of the first digital signal by a filter to generate a second digital signal; frequency-modulating the second digital signal by a synchronizer to generate a third digital signal; and performing digital signal processing on the third digital signal according to a cutoff frequency by a processor to generate a final digital signal. After the synchronizer receives the second digital signal, the synchronizer sends an interrupt signal to the processor, and the processor performs digital signal processing according to the interrupt signal.

[0007] Based on the above, the analog-to-digital converter circuit and its operation method in the microcontroller provided by the embodiments of the present invention can filter out a portion of the high-frequency noise in the digital signal after the modulator converts the analog signal into a digital signal. Then, the synchronizer synchronizes the filtered digital signal to the processor. Finally, the processor uses its built-in DSP function to further filter the synchronized digital signal according to the cutoff frequency. In this way, the embodiments of the present invention use the processor's built-in DSP function to replace part of the filter in existing embodiments, which saves the circuit area of ​​the ADC circuit. Furthermore, since the DSP function can be programmed in software, the cutoff frequency can be adjusted according to the main frequency of the analog signal, which improves the flexibility of the ADC circuit for various applications and allows harmonics to be filtered out more flexibly, resulting in better Effective Number of Bits (ENOB) performance evaluation parameters to improve the resolution of the ADC circuit.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a block diagram of a ΔΣADC circuit drawn according to an existing embodiment.

[0010] Figure 2 This is a block diagram of a ΔΣADC circuit according to an embodiment of the present invention.

[0011] Figure 3 This is a flowchart illustrating the operation method of a ΔΣADC circuit according to an embodiment of the present invention. Detailed Implementation

[0012] Figure 1 This is a block diagram of a ΔΣADC circuit according to an existing embodiment. Please refer to... Figure 1The ΔΣADC circuit 100 includes a ΔΣ modulator 120 and a digital signal processing module 140. The digital signal processing module 140 is typically a digital filter composed of a comb filter 142 and two stages of finite impulse response (FIR) filters 144 and 146. This combination is highly feasible and economical in circuit implementation.

[0013] In the existing embodiment, the ΔΣ modulator 120 has noise shaping characteristics. The analog signal AS is pushed to a higher frequency by the quantization noise through the ΔΣ modulator 120, and in this process, the analog signal has been converted into a digital signal by the quantizer. Then, the digital signal DS1 output by the ΔΣ modulator 120 is filtered out of the high-frequency quantization noise by the digital signal processing module 140 to leave the desired signal (low frequency), and the final digital signal DSF is output.

[0014] Generally, the resolution of a delta-satellite ADC circuit is directly proportional to the filter order. Higher resolution requires a higher filter order, and a higher filter order also increases manufacturing cost. Therefore, to perfectly separate noise from the desired signal (high resolution), the existing delta-satellite ADC circuit 100 requires a very high-order FIR filter, resulting in a significantly larger circuit area and higher manufacturing cost. Furthermore, if the customer using this MCU does not require an ADC circuit, the filter area is wasted, and unnecessary leakage current is generated. Additionally, under the current hardware architecture, customers cannot adjust the cutoff frequency based on the frequency of the analog signal received by different sensors to ensure high resolution for all received analog signals.

[0015] The following embodiments of the present invention can replace existing FIR filters using the processor's built-in DSP functionality. In this way, the following embodiments can save the area of ​​the ΔΣADC circuit, improve the resolution of the ΔΣADC circuit, and enhance the flexibility of the ΔΣADC circuit for various applications.

[0016] Figure 2 This is a block diagram of a ΔΣADC circuit according to an embodiment of the present invention. Please refer to... Figure 2 The ΔΣADC circuit 200 includes a modulator 220 and a digital signal processing module 240. The digital signal processing module 240 includes a filter 242, a synchronizer 244, and a processor 246, with the filter 242 coupled to the modulator 220 and the synchronizer 244, and the synchronizer 244 coupled to the processor 246.

[0017] The modulator 220 in this embodiment can be a ΔΣ modulator, but this is not a limitation of the embodiments of the present invention. Specifically, the modulator 220 is composed of a differentiator and an integrator. The function of the modulator 220 is to push the quantization noise to a higher frequency to produce a noise shaping effect. In one embodiment, the number of integrators determines the order of the modulator 220. The higher the order of the modulator 220, the more significant the noise shaping effect will be.

[0018] The filter 242 in this embodiment is, for example, a comb filter, a low-pass filter, a median filter, an FIR filter, or a combination thereof, and the embodiments of the present invention are not limited thereto. In detail, the function of filter 242 is to filter out invalid signals while retaining valid signals.

[0019] The synchronizer 244 in this embodiment can be of various types, and the embodiments of the present invention are not limited to this. Specifically, the function of the synchronizer 244 is to perform frequency modulation and conversion on the signal.

[0020] The processor 246 in this embodiment is, for example, a Central Processing Unit (CPU), a Microprocessor, an MCU, a Digital Signal Processor (DSP), a Programmable Logic Controller (PLC), an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar devices (or combinations thereof). Specifically, the processor 246 performs signal filtering using its built-in DSP functionality.

[0021] Figure 3 This is a flowchart illustrating the operation method of a ΔΣADC circuit according to an embodiment of the present invention. Please refer to... Figure 3 The method 300 in this embodiment is applicable to Figure 2 The following describes the detailed steps of the operation method of this embodiment in conjunction with the various components of the ΔΣADC circuit 200.

[0022] Please refer to the following at the same time Figure 2 and Figure 3In step S320, modulator 220 receives analog signal AS and converts it into digital signal DS1. Specifically, modulator 220 has noise shaping characteristics, pushing the quantization noise of analog signal AS to a higher frequency and leaving the truly needed signal at a lower frequency. During this process, the analog signal has been converted into a digital signal by the quantizer, and the digital signal DS1 is output to filter 242.

[0023] In step S340, filter 242 receives digital signal DS1 from modulator 220, filters out noise outside the bandwidth of digital signal DS1 to generate digital signal DS2, and outputs digital signal DS2 to synchronizer 244. In one embodiment, the bandwidth may be 1 kHz or 2 kHz, but is not limited thereto. In one embodiment, filter 242 is a comb filter that filters out some noise in digital signal DS1.

[0024] In step S360, synchronizer 244 receives digital signal DS2 from filter 242, modulates the frequency of digital signal DS2 to generate digital signal DS3, and outputs digital signal DS3 to processor 246. Specifically, after receiving digital signal DS2, synchronizer 244 sends interrupt signal IS to processor 246. In one embodiment, synchronizer 244 modulates the frequency of digital signal DS2 according to the clock domain of processor 246 to generate digital signal DS3. Specifically, when synchronizer 244 receives digital signal DS2, synchronizer 244 sends interrupt signal IS to processor 246, and simultaneously modulates the frequency of digital signal DS2 according to the clock domain of processor 246 to generate digital signal DS3, and outputs digital signal DS3 to processor 246. During this process, synchronizer 244 synchronizes the received digital signal DS2 to the clock domain of processor 246.

[0025] In step S380, the processor 246 receives the interrupt signal IS and the digital signal DS3 from the synchronizer 244, and performs digital signal processing on the digital signal DS3 according to the cutoff frequency CF to generate the final digital signal DSF. Specifically, the processor performs digital signal processing based on the interrupt signal IS (i.e., performs digital signal processing on the digital signal DS3 according to the cutoff frequency CF to generate the final digital signal DSF). In one embodiment, the cutoff frequency CF is, for example, 1 kHz or 2 kHz, but is not limited thereto. In one embodiment, the processor 246 calculates the cutoff frequency CF based on the main frequency of the analog signal AS. In one embodiment, the cutoff frequency CF is a multiple of the main frequency of the analog signal AS. For example, if the main frequency of the analog signal AS is 20 kHz, the cutoff frequency CF can be twice the main frequency of the analog signal AS (i.e., 40 kHz).

[0026] It is worth noting that, in one embodiment, the processor 246 executes a digital signal processing program stored in memory to perform digital signal processing on the digital signal DS3. In one embodiment, the cutoff frequency CF is input to the digital signal processing program by the user. In another embodiment, the cutoff frequency CF may be pre-stored in memory and directly selected by the processor 246 or the user. In yet another embodiment, the cutoff frequency CF can be changed by programming.

[0027] In one embodiment, processor 246 stores the final digital signal DSF in a memory or register for access by other circuitry. In another embodiment, processor 246 corrects modulator 220 based on the final digital signal DSF.

[0028] Here, since the digital signal output from filter 242 (e.g., a comb filter) has been down-frequencyed to an extremely low frequency, which is hundreds to thousands of times lower than the frequency of processor 246, processor 246 only needs to expend some resources to handle the filtering operation. After completing this filtering operation, processor 246 stores the final digital signal DSF in static random access memory (SRAM) or a specific register for later access by the required circuitry.

[0029] Existing ΔΣADC circuits use FIR filters with fixed cutoff frequencies to filter digital signals. However, the ΔΣADC circuit of this invention uses the processor's built-in DSP function to filter digital signals. In this way, the ΔΣADC circuit can dynamically adjust the cutoff frequency or modify the DSP program settings according to different customer needs. It is also worth mentioning that if a customer using this MCU does not require the ΔΣADC circuit, they only need to remove the DSP program.

[0030] It is worth noting that the specific order and / or hierarchy of steps in the methods of the embodiments of the present invention are merely exemplary approaches. Based on design preferences, the specific order or hierarchy of steps in the disclosed methods or processes may be rearranged while remaining within the scope of the embodiments of the present invention. Therefore, those skilled in the art will understand that the methods and techniques of the embodiments of the present invention present various steps or actions in a sample order, and that the embodiments of the present invention are not limited to the presented specific order or hierarchy, unless otherwise expressly stated.

[0031] In summary, the analog-to-digital converter circuit and its operation method in the microcontroller provided by the embodiments of the present invention can filter out a portion of the high-frequency noise in the digital signal after the modulator converts the analog signal into a digital signal. Next, the synchronizer synchronizes the filtered digital signal to the processor. Finally, the processor uses its built-in DSP function to further filter the synchronized digital signal according to the cutoff frequency. In this way, the embodiments of the present invention use the processor's built-in DSP function to replace part of the filter in existing embodiments, which saves circuit area in the ADC circuit. Furthermore, since the DSP function can be programmed in software, the cutoff frequency can be adjusted according to the main frequency of the analog signal, which improves the flexibility of the ADC circuit for various applications and allows harmonics to be filtered out more flexibly, resulting in better ENOB performance evaluation parameters and improved resolution of the ADC circuit.

[0032] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An analog-to-digital converter circuit in a microcontroller, characterized in that, include: A modulator for receiving analog signals and converting the analog signals into a first digital signal; A filter, coupled to the modulator, is used to filter out noise outside the bandwidth of the first digital signal to generate a second digital signal; A synchronizer, coupled to the filter, is used to frequency modulate the second digital signal to generate a third digital signal; as well as A processor, coupled to the synchronizer, performs digital signal processing on the third digital signal according to a cutoff frequency to generate a final digital signal. After the synchronizer receives the second digital signal, the synchronizer sends an interrupt signal to the processor, and the processor performs digital signal processing based on the interrupt signal.

2. The analog-to-digital converter circuit according to claim 1, characterized in that, The processor executes a digital signal processing program stored in the memory to perform digital signal processing on the third digital signal.

3. The analog-to-digital converter circuit according to claim 1, characterized in that, The processor calculates the cutoff frequency based on the main frequency of the analog signal.

4. The analog-to-digital converter circuit according to claim 3, characterized in that, The cutoff frequency is a multiple of the dominant frequency of the analog signal.

5. The analog-to-digital converter circuit according to claim 1, characterized in that, The processor stores the final digital signal in a memory or register for access by other circuits.

6. The analog-to-digital converter circuit according to claim 1, characterized in that, The processor further corrects the modulator based on the final digital signal.

7. A method for operating an analog-to-digital converter circuit in a microcontroller, characterized in that, include: The modulator receives the analog signal and converts the analog signal into a first digital signal; The first digital signal is filtered out of noise outside the bandwidth to generate the second digital signal; The second digital signal is frequency-modulated by a synchronizer to generate a third digital signal; as well as The processor performs digital signal processing on the third digital signal according to the cutoff frequency to generate the final digital signal. After the synchronizer receives the second digital signal, the synchronizer sends an interrupt signal to the processor, and the processor performs digital signal processing based on the interrupt signal.

8. The operating method according to claim 7, characterized in that, The processor executes a digital signal processing program stored in the memory to perform digital signal processing on the third digital signal.

9. The operating method according to claim 7, characterized in that, Including: The processor calculates the cutoff frequency based on the main frequency of the analog signal.

10. The operating method according to claim 9, characterized in that, The cutoff frequency is a multiple of the dominant frequency of the analog signal.

11. The operating method according to claim 7, characterized in that, The processor stores the final digital signal in a memory or register for access by other circuits.

12. The operating method according to claim 7, characterized in that, Including: The processor corrects the modulator based on the final digital signal.

Images