Semiconductor structure and method for forming the same

Abstract

An embodiment of the present application provides a semiconductor structure and a method for forming the same, including: providing a substrate; forming spaced-apart bit line contact holes, bit line contacts partially in contact with the bit line contact holes, and a bit line structure on the substrate, wherein the bit line structure includes at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer; a first insulating layer is formed in the bit line contact hole to fill the bit line contact hole; and an insulating structure having an air interlayer is formed on both side walls of the bit line structure, wherein the height of the air interlayer is greater than the height of the conductive layer in the bit line structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to, but not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), consist of multiple memory cells, word lines (WLs), and bit lines (BLs). Each memory cell typically includes a transistor and a capacitor. The transistor's gate is connected to the WL, the transistor's drain or source is connected to the BL, and the transistor's source or drain is connected to the capacitor. Applying a voltage signal to the WL controls the transistor's on or off state, allowing the BL to read data stored in the capacitor or write data to the capacitor for storage.

[0003] Semiconductor devices may also include storage node contacts (NCs) and bit line contacts (BLCs). NCs electrically connect the source / drain regions to other parts of the semiconductor structure, while BLCs electrically connect the active area to the bit line (BL). With the increasing integration of semiconductor memory devices, the distance between the BL and NCs becomes shorter, increasing the parasitic capacitance between the BL and NCs, which in turn reduces the memory's sensing margin and read speed. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming spaced-apart bit line contact holes, bit line contacts partially in contact with the bit line contact holes, and a bit line structure on the substrate, wherein the bit line structure comprises at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer; a first insulating layer is formed in the bit line contact hole to fill the bit line contact hole; and an insulating structure having an air interlayer is formed on both side walls of the bit line structure, wherein the height of the air interlayer is greater than the height of the conductive layer in the bit line structure.

[0006] In a second aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; bit line contact holes arranged at intervals on the substrate, bit line contacts partially in contact with the bit line contact holes, and a bit line structure, wherein the bit line structure comprises at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer; a first insulating layer filling the bit line contact holes is located in the bit line contact holes; an insulating structure having an air interlayer located on both side walls of the bit line structure, wherein the height of the air interlayer is greater than the height of the conductive layer in the bit line structure.

[0007] In an embodiment of the present application, a method for forming a sidewall of a bitline structure, i.e., an insulating structure with an air layer, is provided by forming spaced-apart bitline contact holes, a bitline contact partially contacting the bitline contact holes, and a bitline structure on a substrate; forming a first insulating layer within the bitline contact holes to fill the bitline contact holes; and forming an insulating structure with an air layer on both sidewalls of the bitline structure, wherein the height of the air layer is greater than the height of the conductive layer in the bitline structure. Because the insulating structure with the air layer is located between the BL and the NC, and the dielectric constant of the air layer is lower than that of the insulating layer in the insulating structure without the air layer, the parasitic capacitance between the NC and the BL is reduced, thereby improving the read capacity of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1a A schematic flow chart of a method for forming a semiconductor structure provided in an embodiment of the present application;

[0009] Figures 1b to 2c A schematic diagram of a process of forming a semiconductor structure provided in an embodiment of the present application;

[0010] Figure 3a A schematic flow chart of another method for forming a semiconductor structure provided in an embodiment of the present application;

[0011] Figures 3b to 3d A schematic diagram of another method for forming a semiconductor structure according to an embodiment of the present application;

[0012] Figures 4a to 4g A schematic diagram of another method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0014] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without at least one of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0015] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0016] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0017] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0018] The present invention provides a method for forming a semiconductor structure. Figure 1a As shown, the method includes the following steps:

[0019] Step S101: providing a substrate.

[0020] Here, the substrate may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display, and may also include multiple layers, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] Shallow trench isolation (STI) can also be formed within the substrate to isolate several active areas. STI can be formed by forming trenches within the substrate and then filling them with an isolation material layer. The STI filler material can include silicon nitride or silicon oxide, which can be formed by thermal oxidation. STI can isolate several active areas in an array or other distribution pattern within the substrate.

[0022] In some embodiments, a buffer layer may be formed in the substrate above the shallow trench isolation and the active area. The buffer layer may include at least one insulating layer. The material of the buffer layer may include silicon oxide, silicon nitride, or silicon oxynitride.

[0023] Step S101 can refer to Figure 1b The provided substrate 101 includes an active area 1012 , a shallow trench isolation 1011 and a buffer layer 1013 , wherein the shallow trench isolation 1011 and the active area 1012 are arranged at intervals, and the buffer layer 1013 is located above the shallow trench isolation 1011 and the active area 1012 .

[0024] Step S102, forming spaced-apart bit line contact holes, bit line contacts partially contacting the bit line contact holes, and a bit line structure on the substrate;

[0025] The material used for the bitline contact may include, but is not limited to, conductive materials such as polysilicon, for example, polysilicon doped with impurities or polysilicon undoped with impurities. The bitline structure includes at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer.

[0026] like Figure 1cAs shown, bitline contact holes 102 arranged at intervals, bitline contacts 103 partially contacting the bitline contact holes 102, and a bitline structure 104 are formed on a substrate 101. The bitline contact holes 102 partially penetrate the substrate 101, and the bitline contacts 103 are located within the bitline contact holes 102. There is space within the bitline contact holes 102 that is not occupied by the bitline contacts 103. A portion of the bitline structure 104 is located above the bitline contacts 103 and connected to the active area 1012 via the bitline contacts 103. The remaining portion of the bitline structure 104 is located above the substrate 101. The bitline structure 104 includes at least a conductive layer 1042 and an insulating cap layer 1041 located on the conductive layer 1042.

[0027] In practical applications, the conductive layer may be made of one or more of polysilicon, metal silicide, conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.), and metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.). In practical applications, the insulating cap layer may be made of at least one of oxide, silicon nitride, and silicon oxynitride. The insulating cap layer may be formed using a chemical vapor deposition process.

[0028] In other embodiments, the bitline structure may further include a diffusion barrier layer located between the bitline contact and the conductive layer. The diffusion barrier layer insulates the conductive layer from the active region and prevents metal ions in the conductive layer from entering the active region. The diffusion barrier layer may comprise a single layer, such as a titanium layer, or a multilayer structure, such as a titanium layer and a titanium nitride layer.

[0029] Step S103, forming a first insulating layer in the bit line contact hole to fill the bit line contact hole;

[0030] Combine Figure 1c and Figure 1d , a first insulating layer 105 (such as Figure 1d ). The surface of the first insulating layer 105 is flush with the surface of the bit line contact hole 102. Here, the first insulating layer can be used to protect the BLC from damage in subsequent processes.

[0031] The material used for the first insulating layer can be a nitride, which can include but is not limited to silicon nitride, silicon oxynitride, etc. In some embodiments, to facilitate control of the thickness of the first insulating layer, the first insulating layer can be formed by an atomic layer deposition process. In other embodiments, the first insulating layer can also be formed by other processes, such as physical vapor deposition, chemical vapor deposition, low-pressure chemical vapor deposition, molecular layer deposition, plasma-enhanced vapor deposition, etc.

[0032] In some embodiments, step S103 may be implemented by first depositing an initial first insulating layer on the upper surface of the substrate and the surface of the bit line contact hole, and then removing the initial first insulating layer above the upper surface of the substrate by etching to form a first insulating layer filling the bit line contact hole.

[0033] Step S104 : forming an insulating structure having an air layer on both side walls of the bit line structure, wherein the height of the air layer is greater than the height of the conductive layer in the bit line structure.

[0034] Here, the insulation structure can be in the form of two insulating layers on either side with an air layer in the middle. That is, the insulation structure from left to right is an insulating layer, an air layer, and an insulating layer. The insulating layer can be made of silicon oxide, aluminum oxide, etc. In practice, the two insulating layers can be made of the same or different materials.

[0035] In some embodiments, in order to facilitate the control of the thickness of the insulating layer in the insulating structure, the insulating layer in the insulating structure can be formed by an atomic layer deposition process. In other embodiments, the insulating layer in the insulating structure can also be formed by other processes, such as physical vapor deposition, chemical vapor deposition, low-pressure chemical vapor deposition, molecular layer deposition, plasma-enhanced vapor deposition, etc.

[0036] In some embodiments, step S104 can be implemented by sequentially depositing a first insulating layer, a sacrificial layer, and a second insulating layer on the surface of the bit line structure, and then dry-etching the middle sacrificial layer to form an air interlayer. Thereafter, an insulating layer of the same material is deposited on the surface of the second insulating layer, the air interlayer, and the first insulating layer to cover the gaps exposed on the surface of the air interlayer, thereby forming an insulating structure with an air interlayer.

[0037] Step S104 can refer to Figure 1e An insulating structure 106 having an air interlayer 1061 is formed on both side walls of the bit line structure 104 , wherein both sides of the air interlayer 1061 are insulating layers 1062 , and the height of the air interlayer 1061 is greater than the height of the conductive layer 1042 in the bit line structure 104 .

[0038] Here, since the height of the air layer is greater than the height of the conductive layer in the bit line structure, and the NC is located between two adjacent BLs, the dielectric layer between the NC and the BL is changed from a single insulating layer to an insulating layer plus an air layer. Since the dielectric constant of the air layer is smaller than that of the insulating layer, the parasitic capacitance between the NC and the BL can be reduced.

[0039] In an embodiment of the present application, a method for forming a sidewall of a bitline structure, i.e., an insulating structure with an air layer, is provided by forming spaced-apart bitline contact holes, a bitline contact partially contacting the bitline contact holes, and a bitline structure on a substrate; forming a first insulating layer within the bitline contact holes to fill the bitline contact holes; and forming an insulating structure with an air layer on both sidewalls of the bitline structure, wherein the height of the air layer is greater than the height of the conductive layer in the bitline structure. Because the insulating structure with the air layer is located between the BL and the NC, and the dielectric constant of the air layer is lower than that of the insulating layer in the insulating structure without the air layer, the parasitic capacitance between the NC and the BL is reduced, thereby improving the read capacity of the memory.

[0040] based on Figure 1a A method for forming a semiconductor structure is shown in FIG. , and an embodiment of the present application provides a semiconductor structure, such as Figure 1e As shown, the structure includes:

[0041] Base 101;

[0042] Bit line contact holes (holes where the first insulating layer 105 is located) arranged at intervals on the substrate 101, bit line contacts 103 partially contacting the bit line contact holes, and a bit line structure 104, wherein the bit line structure 104 includes at least a conductive layer 1042 and an insulating cap layer 1041; the insulating cap layer 1041 is located on the conductive layer 1042;

[0043] A first insulating layer 105 located in the bit line contact hole and filling the bit line contact hole;

[0044] The insulating structure 106 having air interlayers 1061 located on both sidewalls of the bit line structure 104 , wherein the height of the air interlayers 1061 is greater than the height of the conductive layer 1042 in the bit line structure 104 .

[0045] In some embodiments, the implementation of step S102 may include:

[0046] Step S1021: forming a bit line contact hole on the substrate;

[0047] Here, step S1021 may be implemented by forming a first photoresist layer on the substrate, patterning the first photoresist layer to form a first mask pattern having a bit line contact hole pattern, and etching the substrate using the first mask pattern as a mask to form the bit line contact hole.

[0048] Photoresist, also known as photoresist, refers to a thin film material that changes its solubility when exposed to ultraviolet light, electron beams, ion beams, X-rays, or other radiation. Photoresist is light-sensitive and consists of a photosensitive resin, a sensitizer, and a solvent. It is used as a corrosion-resistant coating during the photolithography process.

[0049] Step S1022: depositing a first initial bit line contact in the bit line contact hole to fill the bit line contact hole;

[0050] Here, step S1022 may be implemented by using a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma enhanced vapor deposition process, etc. to deposit in the bit line contact hole to form a first initial bit line contact that fills the bit line contact hole.

[0051] In some embodiments, a first initial bit line contact may be deposited to fill the bit line contact hole, and a second initial bit line contact may be deposited on the surface of the bit line contact hole and the substrate, and then chemical mechanical polishing may be used to remove the second initial bit line contact located above the upper surface of the substrate to form the first initial bit line contact.

[0052] Step S1023: depositing an initial conductive layer, an initial insulating cap layer, and a second photoresist layer in sequence on the upper surface of the substrate;

[0053] Here, the implementation of step S1023 can adopt physical vapor deposition process, chemical vapor deposition process, low pressure chemical vapor deposition process, molecular layer deposition process, plasma enhanced vapor deposition process, etc. to sequentially deposit an initial conductive layer, an initial insulating cap layer and a second photoresist layer on the upper surface of the substrate.

[0054] Step S1024: patterning the second photoresist layer to form a second mask pattern having a bit line structure pattern;

[0055] Here, patterning the second photoresist layer may include exposing and developing the second photoresist layer to dissolve away a portion of the second photoresist layer, and forming a second mask pattern on an undissolved portion of the second photoresist layer.

[0056] Step S1025: using the second mask pattern as a mask, etching the initial conductive layer and the initial insulating cap layer to form the conductive layer and the insulating cap layer;

[0057] Here, step S1025 may be implemented by etching the initial conductive layer and the initial insulating cap layer using a dry etching process (eg, reactive ion etching technology, plasma etching technology, etc.) to form a conductive layer and an insulating cap layer.

[0058] Step S1026: removing the second photoresist layer;

[0059] Here, step S1026 may be implemented by using a wet or dry etching process to remove the second photoresist layer.

[0060] Step S1027: using the conductive layer and the insulating cap layer as masks, etching the first initial bit line contact in the bit line contact hole to form the bit line contact, wherein the bit line contact is in partial contact with the bit line contact hole.

[0061] Here, step S1027 may be implemented by using a wet or dry etching process to etch the first initial bit line contact in the bit line contact hole to form a bit line contact.

[0062] In some embodiments, the implementation of step S104 of “forming an insulating structure having an air interlayer on both side walls of the bit line structure” may include:

[0063] Step S1041: forming a second insulating layer, a sacrificial layer, and a third insulating layer in sequence on both side walls of the bit line structure, exposing a portion of the surface of the sacrificial layer;

[0064] Figure 2a Shows Figure 1e The formation process of the insulating structure on both side walls of a bit line structure, such as Figure 2a As shown in FIG. 1 , a second insulating layer 203 , a sacrificial layer 202 and a third insulating layer 201 are sequentially formed on both side walls of the bit line structure 104 , exposing a portion of the surface of the sacrificial layer 202 , i.e., the top of the sacrificial layer 202 , wherein the upper surfaces of the second insulating layer 203 , the sacrificial layer 202 and the third insulating layer 201 are flush.

[0065] In some embodiments, step S1041 can be implemented by sequentially depositing an initial second insulating layer, an initial sacrificial layer, and an initial third insulating layer on both side walls of the bit line structure, and then etching the initial second insulating layer, the initial sacrificial layer, and the initial third insulating layer located above the upper surface of the bit line structure to form the second insulating layer, the sacrificial layer, and the third insulating layer, exposing a portion of the surface of the sacrificial layer.

[0066] Step S1042: etching the sacrificial layer along a first direction to form the air layer, wherein the first direction is a direction perpendicular to the substrate;

[0067] Combine Figure 2a As shown in Figures (1) and (2), the sacrificial layer 202 is etched along the first direction (the direction indicated by the arrow) to form Figure 2a The air interlayer 1061 shown in Figure (2) in FIG. 1 , wherein the first direction is perpendicular to the substrate, combined with Figure 1e It can be seen that the first direction is Figure 2a The direction indicated by the arrow.

[0068] In some embodiments, step S1042 may be implemented by etching the sacrificial layer along the first direction to form an air interlayer using a dry etching process, such as reactive ion etching technology, plasma etching technology, etc.

[0069] In the embodiment of the present application, a dry etching process is adopted and the anisotropy of dry etching is utilized to etch the sacrificial layer, thereby facilitating the formation of an air interlayer.

[0070] Step S1043: forming a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer, to obtain an insulating structure having air interlayers on both side walls of the bit line structure, wherein the insulating structure includes the second insulating layer, the air interlayer, the third insulating layer and the fourth insulating layer stacked in sequence.

[0071] Here, the implementation of step S1043 can adopt a deposition process to form a fourth insulating layer on the upper surface of the bit line structure, the surface of the second insulating layer, the air interlayer and the third insulating layer, such as a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma-enhanced vapor deposition process, an atomic layer deposition process, etc.

[0072] The fourth insulating layer may be made of oxide, such as silicon oxide, aluminum oxide, etc. The material of the fourth insulating layer may be at least the same as that of the second insulating layer or the third insulating layer, so that the fourth insulating layer can cover the gaps on the surface of the air layer.

[0073] like Figure 2a As shown in FIG. 3 , a fourth insulating layer 205 covering the third insulating layer 201, the air interlayer 1061 and the second insulating layer 203 is formed, that is, the fourth insulating layer 205 covers the surfaces of the third insulating layer, the air interlayer 1061 and the second insulating layer 203, thereby obtaining an insulating structure 106 having the air interlayer 1061 on both side walls of the bit line structure 104, wherein the insulating structure 106 includes the second insulating layer 203, the air interlayer 1061, the third insulating layer 201 and the fourth insulating layer 205 stacked in sequence.

[0074] In some embodiments, the implementation of step S1043 may include:

[0075] Step S1431: forming an initial fourth insulating layer on the upper surface of the bit line structure, on the surfaces of the second insulating layer, the air interlayer, and the third insulating layer;

[0076] Here, the material used for the initial fourth insulating layer may be at least the same as the material used for the second insulating layer or the third insulating layer, so that the initial fourth insulating layer can cover the gaps on the surface of the air layer.

[0077] like Figure 2b As shown in FIG. 1 , an initial fourth insulating layer 209 is formed on the upper surface of the bit line structure 104 , the second insulating layer 203 , the air interlayer 1061 and the surface of the third insulating layer 201 .

[0078] Step S1432: etching the initial fourth insulating layer located above the top of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.

[0079] Here, step S1432 may be implemented by etching the initial fourth insulating layer located above the top of the bit line structure using a dry etching process, such as reactive ion etching technology, plasma etching technology, etc.

[0080] Combine Figure 2b In Figures (1) and (2), the initial fourth insulating layer 209 located above the top of the bit line structure 104 is etched to form a Figure 2b FIG. 2 shows a fourth insulating layer 205 covering the third insulating layer 201 , the air interlayer 1061 and the second insulating layer 203 .

[0081] In an embodiment of the present application, a second insulating layer, a sacrificial layer and a third insulating layer are sequentially deposited on the surface of the bit line structure, and then the middle sacrificial layer is etched to form an air interlayer. Thereafter, a fourth insulating layer is deposited on the surface of the second insulating layer, the air interlayer and the third insulating layer to cover the exposed gaps at the top of the air interlayer, thereby forming an insulating structure with an air interlayer.

[0082] In some embodiments, the implementation of step S1041 may include:

[0083] Step S1411: forming an initial second insulating layer and an initial sacrificial layer in sequence on the surface of the bit line structure;

[0084] like Figure 2c As shown in FIG. 1 , an initial second insulating layer 206 and an initial sacrificial layer 207 are sequentially formed on the surface of the bit line structure 104 .

[0085] Here, the implementation of step S1411 can adopt a deposition process to sequentially form an initial second insulating layer and an initial sacrificial layer on the surface of the bit line structure, such as a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma-enhanced vapor deposition process, an atomic layer deposition process, etc.

[0086] The material used for the initial second insulating layer may be an oxide, such as silicon oxide, aluminum oxide, etc. The material used for the initial sacrificial layer may include polysilicon.

[0087] Step S1412: etching the initial sacrificial layer located above the top of the bit line structure to form the sacrificial layer;

[0088] Combine Figure 2c In Figures (1) and (2), the initial sacrificial layer 207 located above the top of the bit line structure 104 is etched to form a Figure 2c The sacrificial layer 202 is shown in FIG. 2 .

[0089] Here, step S1412 may be implemented by etching the initial sacrificial layer located above the top of the bit line structure using a dry etching process, such as reactive ion etching technology, plasma etching technology, etc.

[0090] Step S1413: forming an initial third insulating layer on a surface of the initial second insulating layer and a surface of the sacrificial layer;

[0091] like Figure 2c As shown in FIG. 3 , an initial third insulating layer 208 is formed on the surface of the initial second insulating layer 206 and the surface of the sacrificial layer 202 .

[0092] Here, the implementation of step S1413 can adopt a deposition process to form an initial third insulating layer on the surface of the initial second insulating layer and the surface of the sacrificial layer, such as a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma-enhanced vapor deposition process, an atomic layer deposition process, etc.

[0093] The material used for the initial third insulating layer may include oxide, such as silicon oxide, aluminum oxide, etc. The material used for the initial third insulating layer may be the same as or different from the material used for the initial second insulating layer.

[0094] Step S1414: Etching the initial third insulating layer and the initial second insulating layer located above the top of the bit line structure to expose a portion of the surface of the sacrificial layer, thereby forming a second insulating layer, a sacrificial layer and a third insulating layer sequentially formed on both side walls of the bit line structure.

[0095] Combine Figure 2c As shown in Figures (3) and (4), the initial third insulating layer 208 and the initial second insulating layer 206 located above the top of the bit line structure 104 are etched to expose a portion of the surface of the sacrificial layer 202, thereby forming a second insulating layer 203, a sacrificial layer 202 and a third insulating layer 201 formed in sequence on both side walls of the bit line structure 104.

[0096] Here, step S1414 may be implemented by etching the initial third insulating layer and the initial second insulating layer located above the top of the bit line structure using a dry etching process, such as reactive ion etching technology, plasma etching technology, etc.

[0097] The present application also provides a method for forming a semiconductor structure. Figure 3a As shown, the method includes:

[0098] Steps S201 to S203 may refer to steps S101 to S103.

[0099] Step S204: forming an initial second insulating layer and an initial sacrificial layer in sequence on the surface of the bit line structure;

[0100] Step S205: etching the initial sacrificial layer located above the top of the bit line structure to form the sacrificial layer;

[0101] Step S206: forming an initial third insulating layer on the surface of the initial second insulating layer and the surface of the sacrificial layer;

[0102] Step S207: Etching the initial third insulating layer and the initial second insulating layer located above the top of the bit line structure to expose a portion of the surface of the sacrificial layer, thereby forming a second insulating layer, a sacrificial layer and a third insulating layer sequentially formed on both side walls of the bit line structure.

[0103] Here, steps S204 to S207 may refer to steps S1411 to S1414.

[0104] Step S208: etching the sacrificial layer along a first direction to form the air layer, wherein the first direction is a direction perpendicular to the substrate;

[0105] Here, step S208 may refer to step S1042.

[0106] Step S209: forming an initial fourth insulating layer on the upper surface of the bit line structure, on the surfaces of the second insulating layer, the air interlayer, and the third insulating layer;

[0107] Step S210a: etching the initial fourth insulating layer located above the top of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.

[0108] Here, step S209 and step S210a refer to step S1431 and step S1432 respectively.

[0109] Step S211a: forming storage node contacts between adjacent fourth insulating layers.

[0110] Here, the storage node contact may include polysilicon doped with impurities or polysilicon not doped with impurities.

[0111] like Figure 3b As shown, a storage node contact 301 is formed between adjacent fourth insulating layers 205 .

[0112] In some other embodiments, after step S209, steps S210b to S212b are further included:

[0113] Step S210b: forming a fifth insulating layer on the surface of the initial fourth insulating layer;

[0114] Here, the material used for the fifth insulating layer may include oxide, such as silicon oxide, aluminum oxide, etc. The material of the fifth insulating layer may be the same as that of the fourth insulating layer, or may be different from that of the fourth insulating layer.

[0115] like Figure 3c As shown, a fifth insulating layer 302 is formed on the surface of the initial fourth insulating layer 209. The structure of the initial fourth insulating layer 209 can be seen in FIG. Figure 2b Figure (1) in .

[0116] Step S211b: etching the fifth insulating layer, the initial fourth insulating layer on the surface of the substrate, and a portion of the substrate to expose the substrate;

[0117] like Figure 3d As shown, the fifth insulating layer 302, the initial fourth insulating layer 209 on the surface of the substrate 101 and a portion of the substrate 101 are etched by a dry etching process to expose the substrate 101, that is, Figure 3d A blank area 303 on the middle substrate.

[0118] Step S212b: etching the initial fourth insulating layer and the fifth insulating layer located above the upper surface of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.

[0119] Step S213b: forming storage node contacts between adjacent fourth insulating layers.

[0120] In an embodiment of the present application, a fifth insulating layer is formed on the surface of the initial fourth insulating layer, and then the fifth insulating layer, the initial fourth insulating layer on the surface of the substrate, and a portion of the substrate are etched. The fifth insulating layer is used to protect the fourth insulating layer, thereby reducing the risk of etching the fourth insulating layer on the surface of the bit line structure during the etching process, thereby protecting the insulating structure.

[0121] The present embodiment further provides a method for forming a semiconductor structure. After step S211a or step S213b, the method includes:

[0122] Step S301: forming a metal layer on a surface of the insulating structure, a surface where the storage node contacts, and a surface of the bit line structure;

[0123] Here, the metal layer can be made of a conductive material, such as tungsten (W). Plasma-enhanced chemical vapor deposition (PECVD) is used to deposit the conductive material to avoid voids during filling. In some embodiments, the conductive material can also be deposited using a suitable process, such as chemical vapor deposition, low-pressure chemical vapor deposition, or atomic layer deposition.

[0124] Step S301 can refer to Figure 4a A metal layer 401 is formed on the surface of the insulating structure 106 , the surface of the storage node contact 301 , and the upper surface of the bit line structure 104 .

[0125] Step S302: etching a portion of the metal layer to form a first opening to expose a portion of the surface of the insulating structure located on the first sidewall of the bit line structure;

[0126] The metal layer remaining after etching forms a landing pad electrically connected to the storage node, and the landing pad covers the surface of the storage node contact, the surface of the insulating structure of the second side wall of the bit line structure and the upper surface of the bit line structure.

[0127] Here, a dry etching process or a wet etching process may be used to selectively etch the metal layer, and the etching gas may be HBr / Cl 2 . The landing pad functions to electrically connect the storage node contact to the capacitor.

[0128] Step S302 can refer to Figure 4b and 4a ,like Figure 4a , etching part of the metal layer 401 to form Figure 4b The first opening 402 shown exposes a portion of the surface of the insulation structure 106 located on the first sidewall B of the bit line structure 104 .

[0129] The remaining metal layer after etching forms a landing pad 403 connected to the storage node contact 301 . The landing pad 403 covers the surface of the storage node contact 301 , the surface of the insulating structure 106 of the second sidewall A of the bit line structure, and the upper surface of the bit line structure 104 .

[0130] Step S303a: forming an isolation structure between adjacent landing pads and on the surface of the landing pads.

[0131] Here, the material of the isolation structure may be silicon oxide, silicon nitride (eg, silicon nitride (Si 3 N 4 )), or silicon oxynitride, etc.

[0132] Step S303a can refer to Figure 4cAn isolation structure 404 is formed between adjacent landing pads 403 and on the surface of the landing pads 403.

[0133] In some embodiments, the isolation structure includes a first filling layer and a second filling layer. Accordingly, the implementation of step S303a of "forming an isolation structure between adjacent landing pads and on the surface of the landing pads" includes step S33a1 and step S33a2, wherein:

[0134] Step S33a1: depositing a first filling layer on the surface of the insulating structure on the first sidewall of the bit line structure and the landing pad;

[0135] Here, step S33a1 can refer to Figure 4d A first filling layer 4042 is deposited on the surface of the insulating structure 106 and the landing pad 403 on the first sidewall B of the bit line structure 104 .

[0136] In some embodiments, the material used for the first filling layer may be the same as or different from the material used for at least one of the second insulating layer, the third insulating layer, or the fourth insulating layer in the insulating structure.

[0137] Step S33a2: depositing a second filling layer on the surface of the first filling layer.

[0138] Here, step S33a2 can refer to Figure 4d A second filling layer 4041 is deposited on the surface of the first filling layer 4042 . The material of the second filling layer can be the same as or different from that of the first filling layer.

[0139] In an embodiment of the present application, a metal layer is formed on the surface of the insulating structure, the surface contacting the storage node, and the surface of the bit line structure, and then a portion of the metal layer is etched to form a first opening, exposing a portion of the surface of the insulating structure located on the first side wall of the bit line structure to form a landing pad, and then an isolation structure is formed between adjacent landing pads and on the surface of the landing pads to form mutually isolated landing pads, so that when the insulating structure has an air interlayer, the NC is connected to other parts of the semiconductor structure through the mutually isolated landing pads.

[0140] The present application provides a semiconductor structure, such as Figure 4d As shown, the structure includes:

[0141] Base 101;

[0142] Bit line contact holes (holes where the first insulating layer 105 is located) arranged at intervals on the substrate 101, bit line contacts 103 partially contacting the bit line contact holes, and a bit line structure 104, wherein the bit line structure 104 includes at least a conductive layer 1042 and an insulating cap layer 1041; the insulating cap layer 1041 is located on the conductive layer 1042;

[0143] A first insulating layer 105 located in the bit line contact hole and filling the bit line contact hole;

[0144] An insulating structure 106 having an air interlayer 1061 is located on both side walls of the bit line structure 104, wherein the height of the air interlayer 1061 is greater than the height of the conductive layer 1042 in the bit line structure 104. The insulating structure 106 includes a second insulating layer 203, an air interlayer 1061, a third insulating layer, and a fourth insulating layer 205 stacked in sequence, wherein the fourth insulating layer 205 covers the third insulating layer, the air interlayer 1061, and the second insulating layer 203. Here, the insulating structure 106 can be referred to as Figure 2b Please refer to Figure (2) in the figure to understand.

[0145] a storage node contact 301 located between adjacent fourth insulating layers 205;

[0146] A landing pad 403 covers the storage node contact 301 , the insulating structure 106 of the second sidewall A, and the upper surface of the bit line structure 104 . The landing pad 403 is electrically connected to the storage node contact 301 .

[0147] An isolation structure 404 is located between adjacent landing pads 403 and on the surface of the landing pad 403 .

[0148] In some embodiments, the isolation structure 404 includes a first filling layer 4042 and a second filling layer 4041 . The first filling layer 4042 is located on the surface of the insulating structure 106 and the landing pad 403 on the first sidewall B of the bit line structure 104 , and the second filling layer 4041 is located on the surface of the first filling layer 4042 .

[0149] The embodiment of the present application further provides a method for forming a semiconductor structure. After step S302, the method further includes:

[0150] Step S303b: Continue etching the first opening along the first direction, and the height of the etching stop position is higher than the height of the conductive layer in the bit line structure to form a second opening; wherein, the air interlayer close to the first side wall is a first air interlayer with a first height, and the air interlayer close to the second side wall is a second air interlayer with a second height, and the first height is less than the second height.

[0151] Step S303b can refer to Figure 4e and Figure 4b ,like Figure 4b As shown, the first direction is perpendicular to the substrate 101, that is, the direction indicated by the arrow in the figure, and the first opening 402 is continuously etched along the first direction. The height of the etching stop position is higher than the height of the conductive layer 1042 in the bit line structure 104, forming Figure 4e The second opening 405 is shown; wherein the air interlayer near the first side wall B is a first air interlayer 407 having a first height h1, the air interlayer near the second side wall A is a second air interlayer 406 having a second height h2, and the first side wall B is Figure 4e The right side wall of all bit line structures 104, the second side wall A is Figure 4e The air interlayer on the left side wall of all the bit line structures 104, that is, the air interlayer close to the right side wall of the bit line structure 104 is a first air interlayer 407 with a first height h1, and the air interlayer close to the left side wall of the bit line structure 104 is a second air interlayer 406 with a second height h2, and the first height h1 is smaller than the second height h2.

[0152] Step S304b: forming an isolation structure between adjacent landing pads and on the surface of the landing pads.

[0153] Step S304b can refer to Figure 4f An isolation structure 404 is formed between adjacent landing pads 403 and on the surface of the landing pads 403.

[0154] In some embodiments, the isolation structure includes a first filling layer and a second filling layer. Accordingly, the implementation of step S304b of "forming an isolation structure between adjacent landing pads and on the surface of the landing pads" includes steps S34b1 and S34b2, wherein:

[0155] Step S34b1: depositing a first filling layer on the surface of the insulating structure on the first sidewall of the bit line structure and the landing pad;

[0156] Here, step S34b1 can refer to Figure 4g A first filling layer 4042 is deposited on the surface of the insulating structure 106 and the landing pad 403 on the first sidewall B of the bit line structure 104 .

[0157] In some embodiments, the material used for the first filling layer can be the same as the material used for at least one of the second insulating layer, the third insulating layer or the fourth insulating layer in the insulating structure 106 to close the opening of the first air interlayer 407 to form a sealed first air interlayer 407.

[0158] Step S34b2: depositing a second filling layer on the surface of the first filling layer.

[0159] Here, step S34b2 can refer to Figure 4gA second filling layer 4041 is deposited on the surface of the first filling layer 4042 . The material of the second filling layer can be the same as or different from that of the first filling layer.

[0160] The isolation structure in the embodiment of the present application includes a first filling layer and a second filling layer. The first filling layer in the isolation structure is used to seal the opening of the first air interlayer to form a closed first air interlayer, and then the second filling layer is deposited on the surface of the first filling layer to form an isolation structure, thereby obtaining a first air interlayer and a second air interlayer of different heights. Since the height of the first air interlayer is higher than the height of the conductive layer in the bit line structure, it plays a role in reducing the parasitic capacitance between NC and BL; at the same time, since the height of the first air interlayer is lower than the height of the second air interlayer, compared with the case where the first air interlayer and the second air interlayer have the same height, a part of the space is reserved for the landing pad, so that the thickness of the landing pad is larger, thereby reducing the resistance of the landing pad and enhancing the conductivity of the landing pad.

[0161] The present application provides a semiconductor structure, such as Figure 4g As shown, the structure includes:

[0162] Base 101;

[0163] Bit line contact holes (holes where the first insulating layer 105 is located) arranged at intervals on the substrate 101, bit line contacts 103 partially contacting the bit line contact holes, and a bit line structure 104, wherein the bit line structure 104 includes at least a conductive layer 1042 and an insulating cap layer 1041; the insulating cap layer 1041 is located on the conductive layer 1042;

[0164] A first insulating layer 105 located in the bit line contact hole and filling the bit line contact hole;

[0165] An insulating structure 106 having an air interlayer 1061 is located on both side walls of the bit line structure 104, wherein the height of the air interlayer 1061 is greater than the height of the conductive layer 1042 in the bit line structure 104. The insulating structure 106 includes a second insulating layer 203, an air interlayer 1061, a third insulating layer, and a fourth insulating layer 205 stacked in sequence, wherein the fourth insulating layer 205 covers the third insulating layer, the air interlayer 1061, and the second insulating layer 203. Here, the insulating structure 106 can be referred to as Figure 2b Please refer to Figure (2) in the figure to understand.

[0166] In some embodiments, the air interlayer includes a first air interlayer 407 having a first height h1 and a second air interlayer 406 having a second height h2, wherein the first air interlayer 406 is close to the first sidewall B of the bit line structure 104, the second air interlayer 406 is close to the second sidewall A of the bit line structure 104, and the first height h1 is less than the second height h2.

[0167] a storage node contact 301 located between adjacent fourth insulating layers 205;

[0168] A landing pad 403 covers the storage node contact 301 , the insulating structure 106 of the second sidewall A, and the upper surface of the bit line structure 104 . The landing pad 403 is electrically connected to the storage node contact 301 .

[0169] An isolation structure 404 is located between adjacent landing pads 403 and on the surface of the landing pad 403 .

[0170] In some embodiments, the isolation structure 404 includes a first filling layer 4042 and a second filling layer 4041 . The first filling layer 4042 is located on the surface of the insulating structure 106 and the landing pad 403 on the first sidewall B of the bit line structure 104 , and the second filling layer 4041 is located on the surface of the first filling layer 4042 .

[0171] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0172] The description of the semiconductor structure embodiment above is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the semiconductor structure embodiment of this application, please refer to the description of the method embodiment of this application for understanding.

[0173] The above description is merely an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming, on the substrate, spaced-apart bit line contact holes, bit line contacts partially contacting the bit line contact holes, and a bit line structure, wherein the bit line structure comprises at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer; forming a first insulating layer in the bit line contact hole so as to fill the bit line contact hole; forming a second insulating layer, a sacrificial layer, and a third insulating layer in sequence on both side walls of the bit line structure, exposing a portion of the surface of the sacrificial layer; Etching the sacrificial layer along a first direction to form an air layer, wherein the first direction is a direction perpendicular to the substrate, and a height of the air layer is greater than a height of the conductive layer in the bit line structure; An initial fourth insulating layer is formed on the upper surface of the bit line structure, on the surfaces of the second insulating layer, the air interlayer and the third insulating layer; Etching the initial fourth insulating layer located above the top of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer, and the second insulating layer, thereby obtaining an insulating structure having air interlayers on both side walls of the bit line structure, wherein the insulating structure includes the second insulating layer, the air interlayer, the third insulating layer, and the fourth insulating layer stacked in sequence; forming a storage node contact between adjacent fourth insulating layers; forming a metal layer on a surface of the insulating structure, a surface of the storage node contact, and an upper surface of the bit line structure; etching a portion of the metal layer to form a first opening to expose a portion of the surface of the insulating structure located on the first sidewall of the bit line structure; The metal layer remaining after etching forms a landing pad electrically connected to the storage node, and the landing pad covers the surface of the storage node contact, the surface of the insulating structure of the second sidewall of the bit line structure, and the upper surface of the bit line structure; Continue etching the first opening along the first direction, and the height of the etching stop position is higher than the height of the conductive layer in the bit line structure to form a second opening; wherein the air interlayer close to the first side wall is a first air interlayer with a first height, and the air interlayer close to the second side wall is a second air interlayer with a second height, and the first height is less than the second height.

2. The method according to claim 1, characterized in that The etching of the sacrificial layer along the first direction to form the air interlayer comprises: The sacrificial layer is etched along a first direction using a dry etching process to form the air interlayer.

3. The method according to claim 1, characterized in that The step of sequentially forming a second insulating layer, a sacrificial layer, and a third insulating layer on both side walls of the bit line structure, and exposing a portion of the surface of the sacrificial layer, comprises: forming an initial second insulating layer and an initial sacrificial layer in sequence on the surface of the bit line structure; Etching the initial sacrificial layer above the top of the bit line structure to form the sacrificial layer; forming an initial third insulating layer on a surface of the initial second insulating layer and a surface of the sacrificial layer; The initial third insulating layer and the initial second insulating layer located above the top of the bit line structure are etched to expose a portion of the surface of the sacrificial layer, thereby forming a second insulating layer, a sacrificial layer and a third insulating layer sequentially formed on both side walls of the bit line structure.

4. The method according to claim 1, wherein Also includes: An isolation structure is formed between adjacent landing pads and on surfaces of the landing pads.

5. The method according to claim 4, characterized in that The isolation structure includes a first filling layer and a second filling layer, and the isolation structure formed between adjacent landing pads and on the surface of the landing pad includes: Depositing a first filling layer on the surface of the insulating structure on the first sidewall of the bit line structure and the landing pad; A second filling layer is deposited on the surface of the first filling layer.

6. The method according to claim 1, characterized in that Before forming storage node contacts between adjacent fourth insulating layers, the method further includes: forming a fifth insulating layer on the surface of the initial fourth insulating layer; Etching the fifth insulating layer, the initial fourth insulating layer on the surface of the substrate, and a portion of the substrate to expose the substrate; Correspondingly, etching the initial fourth insulating layer located above the top of the bit line structure to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer includes: The initial fourth insulating layer and the fifth insulating layer located above the upper surface of the bit line structure are etched to form a fourth insulating layer covering the third insulating layer, the air interlayer and the second insulating layer.

7. The method according to any one of claims 2 to 6, characterized in that The material of the first insulating layer includes nitride; Materials of the second insulating layer, the third insulating layer, and the fourth insulating layer include oxide.

8. The method according to any one of claims 2 to 6, characterized in that The material of the sacrificial layer includes silicon.

9. A semiconductor structure formed by the method according to any one of claims 1 to 8, characterized in that: include: substrate; Bit line contact holes arranged at intervals on the substrate, bit line contacts partially contacting the bit line contact holes, and a bit line structure, wherein the bit line structure comprises at least a conductive layer and an insulating cap layer; the insulating cap layer is located on the conductive layer; a first insulating layer located in the bit line contact hole and filling the bit line contact hole; An insulating structure having an air interlayer located on both side walls of the bit line structure, wherein the height of the air interlayer is greater than the height of the conductive layer in the bit line structure.

10. The structure according to claim 9, characterized in that The insulating structure includes a second insulating layer, an air interlayer, a third insulating layer, and a fourth insulating layer stacked in sequence, wherein the fourth insulating layer covers the third insulating layer, the air interlayer, and the second insulating layer.

11. The structure according to claim 10, characterized in that The air interlayer includes a first air interlayer having a first height and a second air interlayer having a second height, wherein the first air interlayer is close to the first sidewall of the bit line structure, the second air interlayer is close to the second sidewall of the bit line structure, and the first height is smaller than the second height.

12. The structure according to claim 11, characterized in that Also includes: a storage node contact located between adjacent fourth insulating layers; A landing pad covers the storage node contact, the insulating structure of the second sidewall, and the upper surface of the bit line structure, and the landing pad is electrically connected to the storage node contact.

13. The structure according to claim 12, characterized in that The structure further comprises: An isolation structure is located between adjacent landing pads and on the surface of the landing pads.

14. The structure according to claim 13, characterized in that The isolation structure includes a first filling layer and a second filling layer. The first filling layer is located on the surface of the insulating structure on the first sidewall of the bit line structure and the landing pad, and the second filling layer is located on the surface of the first filling layer.

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