Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device, the array substrate comprises a display area, the display area comprises a plurality of pixel areas; a substrate, pixel driving circuits and scanning signal lines, at least part of the pixel driving circuits and the scanning signal lines are located on the same side of the substrate, and the scanning signal lines extend along a first direction; at least part of the pixel driving circuits are located in the pixel areas and comprise thin film transistors; the thin film transistor comprises a gate and a channel layer, and the gate is a part of the scanning signal line overlapping with the channel layer; the array substrate further comprises an auxiliary signal line, the auxiliary signal line is located in the display area and extends along the first direction; the resistance of the auxiliary signal line is smaller than that of the scanning signal line, the auxiliary signal line is in a layer different from that of the scanning signal line, and the auxiliary signal line is electrically connected to the scanning signal line through a line changing via. The application provides an array substrate, a display panel and a display device, reduces the transmission voltage drop of the scanning signal, and improves the display performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the continuous development of science and technology, more and more display devices, such as mobile phones, tablet computers, notebook computers and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable important tool for people today. The main component of the display device to realize the display function is the display panel.

[0003] In the display panel, the pixel driving circuit provides the driving current required for the display of the light emitting element of the display panel, and controls whether the light emitting element enters the light emitting stage, thus becoming an indispensable element in most self-luminous display panels. SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device, which reduces the transmission voltage drop of the scanning signal and improves the display performance.

[0005] In a first aspect, an array substrate is provided, comprising a display area, wherein the display area comprises a plurality of pixel areas;

[0006] A substrate, a pixel driving circuit and a scanning signal line, at least part of the pixel driving circuit and the scanning signal line are located on the same side of the substrate, and the scanning signal line extends along a first direction;

[0007] At least part of the pixel driving circuit is located in the pixel area and comprises a thin film transistor; the thin film transistor comprises a gate and a channel layer, and the gate is a part of the scanning signal line overlapping with the channel layer;

[0008] The array substrate further comprises an auxiliary signal line, the auxiliary signal line is located in the display area and extends along the first direction; the resistance of the auxiliary signal line is smaller than the resistance of the scanning signal line, the auxiliary signal line is in a different layer from the scanning signal line, and the auxiliary signal line is electrically connected to the scanning signal line through a wire changing via.

[0009] In a second aspect, a display panel is provided, comprising the array substrate of the first aspect, and a plurality of light emitting elements;

[0010] The light emitting elements are electrically connected to the pixel driving circuit and are configured to emit light under the driving of the pixel driving circuit.

[0011] In a third aspect, a display device is provided, comprising the display panel of the second aspect.

[0012] The array substrate provided by the embodiment of the present application comprises a gate control signal line, which comprises a scanning signal line and an auxiliary signal line. The auxiliary signal line is arranged for the scanning signal line, the resistance of the auxiliary signal line is smaller than that of the scanning signal line, and the auxiliary signal line is electrically connected with the scanning signal line through a line-changing via. Therefore, when transmitting the scanning signal, the scanning signal can be transmitted not only on the scanning signal line with large resistance but also on the auxiliary signal line with small resistance, the resistance of the gate control signal line is reduced, the transmission voltage drop of the scanning signal is reduced, and the display performance is improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 The top view structural schematic diagram of the array substrate provided by the embodiment of the present application is shown in FIG. 1;

[0014] Figure 2 The circuit structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 2;

[0015] Figure 3 The top view structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 3;

[0016] Figure 4 The sectional view structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 4;

[0017] Figure 5 The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 5; Figure 3

[0018] The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6; Figure 6

[0019] The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 7; Figure 7

[0020] The schematic diagram of the pixel driving circuit forming an array provided by the embodiment of the present application is shown in FIG. 8; Figure 8 Figure 3 The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 9;

[0021] Figure 9 Figure 8 The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 10;

[0022] Figure 10 The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 11;

[0023] Figure 11 The partial structural schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 12;

[0024] Figure 12 ​​A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0025] Figure 13 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6; Figure 12 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0026] Figure 14 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0027] Figure 15 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0028] Figure 16 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6; Figure 15 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0029] Figure 17 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0030] Figure 18 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0031] Figure 19 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0032] Figure 20 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0033] Figure 21 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0034] Figure 22 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6; Figure 3 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0035] Figure 23 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0036] Figure 24 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0037] Figure 25 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6; Figure 3 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0038] Figure 26 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6;

[0039] Figure 27 FIG. 2 shows a partial structure schematic diagram of another pixel driving circuit according to an embodiment of the present application;

[0040] Figure 28 FIG. 2 shows a partial structure schematic diagram of another pixel driving circuit according to an embodiment of the present application;

[0041] Figure 29 FIG. 3 shows a cross-sectional structure schematic diagram of a display panel according to an embodiment of the present application;

[0042] Figure 30 FIG. 4 shows a schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The present application will be further described below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are intended to serve only as an example of the present application and are not intended to limit the present application in any way. In addition, it should be noted that, for the purpose of description, only the parts related to the present application are shown in the drawings rather than all the parts.

[0044] Figure 1 FIG. 1 shows a top view structure schematic diagram of an array substrate according to an embodiment of the present application, Figure 2 FIG. 2 shows a circuit structure schematic diagram of a pixel driving circuit according to an embodiment of the present application, Figure 3 FIG. 2 shows a top view structure schematic diagram of a pixel driving circuit according to an embodiment of the present application, Figure 4 FIG. 2 shows a cross-sectional structure schematic diagram of a pixel driving circuit according to an embodiment of the present application, Figure 5 FIG. 2 shows a cross-sectional structure schematic diagram of a pixel driving circuit according to an embodiment of the present application, Figure 3 FIG. 2 shows a cross-sectional structure schematic diagram of a pixel driving circuit according to an embodiment of the present application, Figures 1-5 The array substrate includes a display area 101, and the display area 101 includes a plurality of pixel areas P. In the display area 101, the plurality of pixel areas P are arranged in a first direction X and a second direction Y. The present application does not limit the arrangement manner of the pixel areas P.

[0045] The array substrate includes a substrate 10, a pixel driving circuit 20, and a gate control signal line 30. The gate control signal line 30 is configured to provide a scanning signal to the pixel driving circuit 20, for controlling the thin film transistor of the pixel driving circuit 20 to be turned on or turned off.

[0046] In the known technology, the gate control signal line 30 is a scanning signal line 31, and the film layer where the scanning signal line 31 is located has a large resistance.

[0047] In the present application, the gate control signal line 30 includes a scan signal line 31 and an auxiliary signal line 32. At least part of the pixel drive circuit 20 and the scan signal line 31 are located in the display area 101. The scan signal line 31 can be located in the display area 101, or the scan signal line 31 can extend from inside the display area 101 to outside the display area 101. The pixel drive circuit 20 and the scan signal line 31 are located on the same side of the substrate 10. The scan signal line 31 extends along the first direction X. At least part of the pixel drive circuit 20 is located in the pixel area P, and the pixel drive circuit 20 includes a thin film transistor 21. The thin film transistor 21 includes a gate 201 and a channel layer 202, and the gate 201 is a portion of the scan signal line 31 that overlaps the channel layer 202. The auxiliary signal line 32 is located in the display area 101, and the auxiliary signal line 32 extends along the first direction X. The resistance of the auxiliary signal line 32 is less than the resistance of the scan signal line 31, the auxiliary signal line 32 is in a different layer from the scan signal line 31, and the auxiliary signal line 32 is electrically connected to the scan signal line 31 through the wire-changing via 51.

[0048] The array substrate provided by the embodiment of the present application includes a gate control signal line 30 including a scan signal line 31 and an auxiliary signal line 32. The auxiliary signal line 32 is provided for the scan signal line 31, the resistance of the auxiliary signal line 32 is less than the resistance of the scan signal line 31, the auxiliary signal line 32 is electrically connected to the scan signal line 31 through the wire-changing via 51, so that when transmitting the scan signal, the scan signal can be transmitted not only on the scan signal line 31 with relatively large resistance, but also on the auxiliary signal line 32 with relatively small resistance, the resistance of the gate control signal line 30 is reduced, the transmission voltage drop of the scan signal is reduced, and the display performance is improved.

[0049] Exemplarily, reference is made to Figure 2The pixel driving circuit 20 comprises a power supply writing transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a first reset transistor T5, a light-emitting control transistor T6, a second reset transistor T7, an adjusting transistor T8 and a storage capacitor C. The first electrode of the power supply writing transistor T1 is electrically connected with the first power supply line VDD, the second electrode of the power supply writing transistor T1 is electrically connected with the second node N2, and the gate electrode of the power supply writing transistor T1 is electrically connected with the light-emitting control signal line EM. The first electrode of the data writing transistor T2 is electrically connected with the data line VDATA, the second electrode of the data writing transistor T2 is electrically connected with the second node N2, and the gate electrode of the data writing transistor T2 is electrically connected with the data control signal line SCP1. The first electrode of the driving transistor T3 is electrically connected with the second node N2, the second electrode of the driving transistor T3 is electrically connected with the third node N3, and the gate electrode of the driving transistor T3 is electrically connected with the first node N1. The first electrode of the compensation transistor T4 is electrically connected with the first node N1, the second electrode of the compensation transistor T4 is electrically connected with the third node N3, and the gate electrode of the compensation transistor T4 is electrically connected with the second scanning line SN2. The first electrode of the first reset transistor T5 is electrically connected with the first reset signal transmission line VREF1, the second electrode of the first reset transistor T5 is electrically connected with the first node N1, and the gate electrode of the first reset transistor T5 is electrically connected with the first scanning line SN1. The first electrode of the light-emitting control transistor T6 is electrically connected with the third node N3, the second electrode of the light-emitting control transistor T6 is electrically connected with the fourth node N4, and the gate electrode of the light-emitting control transistor T6 is electrically connected with the light-emitting control signal line EM. The first electrode of the second reset transistor T7 is electrically connected with the second reset signal transmission line VREF2, the second electrode of the second reset transistor T7 is electrically connected with the fourth node N4, and the gate electrode of the second reset transistor T7 is electrically connected with the anode reset control signal line SCP2. The first electrode of the adjusting transistor T8 is electrically connected with the adjusting signal transmission line DVH, the second electrode of the adjusting transistor T8 is electrically connected with the second node N2, and the gate electrode of the adjusting transistor T8 is electrically connected with the adjusting control signal line SCP3. The first plate C1 of the storage capacitor C is electrically connected with the first node N1, and the second plate C2 of the storage capacitor C is electrically connected with the first power supply line VDD.

[0050] The first node N1, the second node N2, the third node N3 and the fourth node N4 can be virtual connection nodes or actual connection nodes.

[0051] It should be noted that the circuit diagram shown in Figure 2 is only an example, and the pixel driving circuit 20 can also have other circuit structures in other embodiments.

[0052] For example, referring to Figure 2The gate control signal line 30 includes a scan signal line 31, the scan signal line 31 including an emission control signal line EM, a first scan line SN1, a second scan line SN2, a data control signal line SCP1, an anode reset control signal line SCP2, and an adjustment control signal line SCP3.

[0053] Exemplarily, referring to Figure 4 The array substrate includes a silicon semiconductor layer POLY, a first metal layer M1, a first sub-gate metal layer MC, an oxide semiconductor layer IGZO, a second sub-gate metal layer MG, a second metal layer M2, and a third metal layer M3, which are sequentially stacked. The silicon semiconductor layer POLY is located between the substrate 10 and the first metal layer M1. The silicon semiconductor layer POLY includes silicon. The oxide semiconductor layer IGZO includes an oxide semiconductor material.

[0054] The plurality of thin film transistors 21 include a silicon transistor 211 and an oxide transistor 212. The silicon transistor 211 includes a gate 201, a channel layer 202, a source 203, and a drain 204. The gate 201 of the silicon transistor 211 is located in the first metal layer M1, the channel layer 202 of the silicon transistor 211 is located in the silicon semiconductor layer POLY, and the source 203 and the drain 204 of the silicon transistor 211 are both located in the second metal layer M2. The scan signal line 31 electrically connected to the gate 201 of the silicon transistor 211 is located in the first metal layer M1. The oxide transistor 212 includes a gate 201, a channel layer 202, a source 203, and a drain 204. The gate 201 of the oxide transistor 212 includes a first sub-gate 2011 and a second sub-gate 2012. In a direction perpendicular to the substrate 10, the first sub-gate 2011 is located between the channel layer 202 and the substrate 10, and the second sub-gate 2012 is located on a side of the channel layer 202 away from the substrate 10. The channel layer 202 of the oxide transistor 212 is located in the oxide semiconductor layer IGZO. The source 203 and the drain 204 of the oxide transistor 212 are both located in the second metal layer M2. The scan signal line 31 electrically connected to the gate 201 of the oxide transistor 212 is located in the first sub-gate metal layer MC or the second sub-gate metal layer MG.

[0055] Exemplarily, referring to Figures 2-4 The power write transistor T1, the data write transistor T2, the drive transistor T3, the emission control transistor T6, the second reset transistor T7, and the adjustment transistor T8 are silicon transistors 211. The compensation transistor T4 and the first reset transistor T5 are oxide transistors 212. Since the compensation transistor T4 and the first reset transistor T5 are both connected to the first node N1, setting the compensation transistor T4 and the first reset transistor T5 as oxide transistors 212 can reduce the leakage current to the first node N1.

[0056] Exemplarily, referring to Figures 2-4The first scan line SN1 includes a first sub-scan line SN11 and a second sub-scan line SN12. The second scan line SN2 includes a third sub-scan line SN21 and a fourth sub-scan line SN22. The data control signal line SCP1, the light-emitting control signal line EM, the anode reset control signal line SCP2, and the adjusting control signal line SCP3 are all located on the first metal layer M1. The first sub-scan line SN11 and the third sub-scan line SN21 are both located on the first sub-gate metal layer MC. The second sub-scan line SN12 and the fourth sub-scan line SN22 are both located on the second sub-gate metal layer MG.

[0057] Optionally, referring to Figures 3-5 The film layer where the auxiliary signal line 32 is located is located on the side of the film layer where the scan signal line 31 is located away from the substrate 10. The auxiliary signal line 32 can be made by using the original metal layer on the side of the second sub-gate metal layer MG away from the substrate 10, so that an additional metal layer does not need to be additionally arranged.

[0058] Optionally, referring to Figures 3-5 The thin film transistor 21 includes a source electrode 203 and a drain electrode 204. The auxiliary signal line 31, the source electrode 203, and the drain electrode 204 are in the same layer. Therefore, the auxiliary signal line 31, the source electrode 203, and the drain electrode 204 can be formed by using the same material and in the same process, thereby saving the process.

[0059] Optionally, referring to Figures 3-5 In the first direction, the length of the scan signal line 31 is less than the length of the auxiliary signal line 32. The resistance of the scan signal line 31 is greater, and the resistance of the auxiliary signal line 32 is smaller. Therefore, a greater length is arranged for the auxiliary signal line 32 with smaller resistance, and a smaller length is arranged for the scan signal line 31 with greater resistance, which is beneficial to reducing the resistance of the gate control signal line 30 formed by the electrical connection between the scan signal line 31 and the auxiliary signal line 32, and reducing the transmission voltage drop of the scan signal.

[0060] Optionally, referring to Figures 3-5 In the direction perpendicular to the substrate 10, the scan signal line 31 and the auxiliary signal line 32 overlap in the area outside the area where the line-changing via 51 is located. In the direction perpendicular to the substrate 10, the scan signal line 31 and the auxiliary signal line 32 overlap, and the overlap between the scan signal line 31 and the auxiliary signal line 32 overlaps the line-changing via 51. Therefore, the light-blocking area of the scan signal line 31 overlaps the light-blocking area of the auxiliary signal line 32, thereby reducing the common light-blocking area of the scan signal line 31 and the auxiliary signal line 32 and increasing the light transmittance.

[0061] Exemplarily, referring to Figures 3-5 The thin film transistor 21 (for example Figure 5In the region where the second reset transistor T7 and the adjusting transistor T8 are located, the scanning signal line 31 and the auxiliary signal line 32 overlap in the direction perpendicular to the substrate 10. If the scanning signal line 31 and the auxiliary signal line 32 are misaligned in the region where the thin film transistor 21 is located, a slope is formed at the edge of the scanning signal line 31 after the scanning signal line 31 is formed (it can be understood that the film layer thickness at the position where the scanning signal line 31 is formed is greater than the film layer thickness at the position where the scanning signal line 31 is not formed). When the auxiliary signal line 32 is formed, the second metal layer M2 where the auxiliary signal line 32 is located is not flat. Therefore, the overlap of the scanning signal line 31 and the auxiliary signal line 32 can also increase the flatness of the second metal layer M2 where the auxiliary signal line 32 is located.

[0062] Optionally, referring to Figure 1 , Figure 3 and Figure 5 , the plurality of scanning signal lines 31 that are in the same line are electrically connected to the same auxiliary signal line 32. The plurality of scanning signal lines 31 that are in the same line are arranged along the first direction X and are electrically connected to the same auxiliary signal line 32 through the line changing via 51. The auxiliary signal line 32 is a straight line segment as a whole, and the length of the auxiliary signal line 32 is relatively large. The relatively large length of the auxiliary signal line 32 with relatively small resistance reduces the transmission voltage drop of the scanning signal.

[0063] Exemplarily, along the first direction X, the plurality of scanning signal lines 31 are in the same line as the auxiliary signal line 32.

[0064] Figure 6 Another partial structure schematic diagram of a pixel driving circuit provided by an embodiment of the present application is provided, referring to Figure 6 , the end of the scanning signal line 31 is electrically connected to the end of the auxiliary signal line 32. Along the first direction X, the scanning signal lines 31 and the auxiliary signal lines 32 are arranged in one-to-one intervals, and one auxiliary signal line 32 is arranged between two adjacent scanning signal lines 31. The two adjacent scanning signal lines 31 are electrically connected through the auxiliary signal line 32 therebetween.

[0065] Exemplarily, along the first direction X, the plurality of scanning signal lines 31 are in the same line as the plurality of auxiliary signal lines 32. One scanning signal line 31 is arranged between two adjacent auxiliary signal lines 32.

[0066] Optionally, continuing to refer to Figure 3 and Figure 5 , the plurality of scanning signal lines 31 that are in the same line include a first scanning signal line 311 and a second scanning signal line 312 that are arranged at intervals and are located in the same pixel region P. In an embodiment of the present application, the two scanning signal lines 31 that are in the same line are arranged at a certain distance in the same pixel region P, and the two scanning signal lines 31 that are in the same line are arranged separately, independently and discontinuously.

[0067] Optionally, with reference to Figure 2 , Figure 3 and Figure 5 continuously, the thin film transistor 21 comprises a drive transistor T3 for providing a drive current for the light emitting element LD. The first scan signal line 311 is configured to control the thin film transistor 21 (specifically, the second reset transistor T7) to transmit a reset signal to the anode of the light emitting element LD. The second scan signal line 312 is configured to control the thin film transistor 21 (specifically, the adjusting transistor T8) to transmit an adjusting signal to the first electrode of the drive transistor T3. In the embodiment of the present application, the first scan signal line 311 comprises an anode reset control signal line SCP2, the second scan signal line 312 comprises an adjusting control signal line SCP3, the first scan signal line 311 and the second scan signal line 312 are in the same line, and are electrically connected with the same auxiliary signal line 32. Therefore, the anode reset control signal line SCP2 is multiplexed as the adjusting control signal line SCP3. The second reset transistor T7 and the adjusting transistor T8 share the same gate control signal line 30.

[0068] Exemplarily, with reference to Figures 3-5 , the first scan signal line 311 comprises the anode reset control signal line SCP2, and the position where the anode reset control signal line SCP2 overlaps with the channel layer 202 forms the gate of the second reset transistor T7. The second scan signal line 312 comprises the adjusting control signal line SCP3, and the position where the adjusting control signal line SCP3 overlaps with the channel layer 202 forms the gate of the adjusting transistor T8. The gate of the second reset transistor T7 and the gate of the adjusting transistor T8 are in the same layer, the gate of the second reset transistor T7 and the gate of the adjusting transistor T8 are in the same line, and the gate of the second reset transistor T7 and the gate of the adjusting transistor T8 are disconnected, i.e., the gate of the second reset transistor T7 and the gate of the adjusting transistor T8 are not connected together by the metal in the same layer.

[0069] Figure 7 Another partial structure schematic diagram of a pixel driving circuit provided by the embodiment of the present application is shown in Figure 4 and Figure 7 . The scan signal line 31 comprises a first signal line segment 331 and a second signal line segment 332 connected with each other. The first signal line segment 331 and the second signal line segment 332 are located in the same pixel region P. The first signal line segment 331 and the second signal line segment 332 respectively comprise a gate 201. In the embodiment of the present application, in the same pixel region P, the first signal line segment 331 and the second signal line segment 332 are different parts of the same scan signal line 31, and the same scan signal line 31 overlaps with at least two channel layers 202 to form at least two gates 201.

[0070] Exemplarily, with reference to Figure 3 ,Figure 4 and Figure 7 The scan signal line 31 includes a first signal line segment 331 and a second signal line segment 332, which are different parts of the same scan signal line 31. The first signal line segment 331 includes an anode reset control signal line SCP2, and the position where the anode reset control signal line SCP2 overlaps the channel layer 202 forms the gate of the second reset transistor T7. The second signal line segment 332 includes an adjustment control signal line SCP3, and the position where the adjustment control signal line SCP3 overlaps the channel layer 202 forms the gate of the adjustment transistor T8. The gate of the second reset transistor T7 and the gate of the adjustment transistor T8 are in the same layer, and the gate of the second reset transistor T7 and the gate of the adjustment transistor T8 are connected together, i.e., the gate of the second reset transistor T7 and the gate of the adjustment transistor T8 are connected together by the metal in the same layer.

[0071] Figure 8 As shown in FIG. 1, Figure 3 is a schematic diagram of an array formed by the pixel driving circuit shown in FIG. 1, Figure 9 is a partial structure schematic diagram of the pixel driving circuit shown in FIG. 1, and Figure 8 is a partial structure schematic diagram of the pixel driving circuit shown in FIG. 1, and Figure 8 and Figure 9 The plurality of pixel regions P include a first pixel region P1 and a second pixel region P2 arranged adjacent to each other along the first direction X. The plurality of scan signal lines 31 in a same line include a third scan signal line 313 and a fourth scan signal line 314 arranged at intervals. The third scan signal line 313 is located in the first pixel region P1, and the fourth scan signal line 314 is located in the second pixel region P2. In the embodiment of the present application, the third scan signal line 313 in the first pixel region P1 and the fourth scan signal line 314 in the second pixel region P2 are in the same line, and the third scan signal line 313 in the first pixel region P1 and the fourth scan signal line 314 in the second pixel region P2 are arranged at intervals. The scan signal lines 31 in the adjacent pixel regions P are arranged separately, independently, and disconnected.

[0072] Exemplarily, referring to Figure 8 and Figure 9 The third scan signal line 313 and the fourth scan signal line 314 each include an adjustment control signal line SCP3, and the position where the adjustment control signal line SCP3 overlaps the channel layer 202 forms the gate of the adjustment transistor T8. The gate of the adjustment transistor T8 in the first pixel region P1 and the gate of the adjustment transistor T8 in the second pixel region P2 are arranged disconnected.

[0073] Exemplarily, referring to Figure 9In the first pixel region P1, the gate of the second reset transistor T7 is connected to the gate of the adjusting transistor T8. In the second pixel region P2, the gate of the second reset transistor T7 is connected to the gate of the adjusting transistor T8. The gate of the adjusting transistor T8 in the first pixel region P1 is disconnected from the gate of the adjusting transistor T8 in the second pixel region P2.

[0074] Figure 10 Another partial structure schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the pixel driving circuit includes a plurality of pixel regions P, a plurality of adjusting control signal lines SCP3, a plurality of adjusting transistors T8, a plurality of reset transistors T7, a plurality of scan signal lines 31, a plurality of data signal lines 32, and a plurality of light emitting diodes D. Figure 10 In the first pixel region P1, the gate of the second reset transistor T7 is connected to the gate of the adjusting transistor T8. In the second pixel region P2, the gate of the second reset transistor T7 is connected to the gate of the adjusting transistor T8. The gate of the adjusting transistor T8 in the first pixel region P1 is disconnected from the gate of the adjusting transistor T8 in the second pixel region P2.

[0075] Figure 11 Another partial structure schematic diagram of the pixel driving circuit provided by the embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the pixel driving circuit includes a plurality of pixel regions P, a plurality of adjusting control signal lines SCP3, a plurality of adjusting transistors T8, a plurality of reset transistors T7, a plurality of scan signal lines 31, a plurality of data signal lines 32, and a plurality of light emitting diodes D. Figure 11 The plurality of pixel regions P include a first pixel region P1 and a second pixel region P2 arranged adjacently along the first direction X. The scan signal line 31 includes a third signal line segment 333 and a fourth signal line segment 334 connected together. The third signal line segment 333 is located in the first pixel region P1, and the third signal line segment 333 includes the gate 201. The fourth signal line segment 334 is located in the second pixel region P2, and the fourth signal line segment 334 includes the gate 201. In the embodiment of the present application, the third signal line segment 333 and the fourth signal line segment 334 are different parts of the same scan signal line 31, and the scan signal line 31 is located in the first pixel region P1 and the second pixel region P2, and overlaps with at least two channel layers 202 in the first pixel region P1 and the second pixel region P2 to form at least two gates 201.

[0076] Exemplarily, referring to FIG. 6, the scan signal line 31 includes the third signal line segment 333 and the fourth signal line segment 334 connected together. The third signal line segment 333 includes the adjusting control signal line SCP3, and the position where the third signal line segment 333 overlaps with the channel layer 202 in the first pixel region P1 forms the gate 201 of the adjusting transistor T8 in the first pixel region P1. The fourth signal line segment 334 includes the adjusting control signal line SCP3, and the position where the fourth signal line segment 334 overlaps with the channel layer 202 in the second pixel region P2 forms the gate 201 of the adjusting transistor T8 in the second pixel region P2. The gate 201 of the adjusting transistor T8 in the first pixel region P1 is connected to the gate 201 of the adjusting transistor T8 in the second pixel region P2. Figure 11

[0077] ​It needs to be further explained that if the gate 201 of the adjusting transistor T8 in the first pixel region P1 is disconnected with the gate 201 of the adjusting transistor T8 in the second pixel region P2, the distance between the channel layer 202 in the first pixel region P1 and the second pixel region P2 is relatively small, and the scanning signal line 31 formed on the silicon semiconductor layer POLY (specifically, the channel layer 202) needs to be completely overlapped with the channel layer 202, that is, the edge of the scanning signal line 31 cannot be overlapped with the silicon semiconductor layer POLY, but needs to exceed the channel layer 202 by a certain distance in the first direction X, and this margin design is used to prevent the offset of the scanning signal line 31 relative to the channel layer 202 caused by process fluctuation. If the gate 201 of the adjusting transistor T8 in the first pixel region P1 is connected with the gate 201 of the adjusting transistor T8 in the second pixel region P2, there is no need to reserve a certain space for process fluctuation, which reduces the process difficulty and can reduce the space occupied by a single pixel region P, thereby improving the pixel density.

[0078] Figure 12 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 13 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 12 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 12 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 13 The plurality of auxiliary signal lines 32 include a first auxiliary signal line 321 and a second auxiliary signal line 322 arranged along a second direction Y, and the second direction Y is perpendicular to the first direction X. The thin film transistor 21 includes a driving transistor T3 for providing a driving current for the light emitting element LD. The plurality of scanning signal lines 31 include a first scanning signal line 311 and a second scanning signal line 312, the first scanning signal line 311 is configured to control the thin film transistor 21 (specifically, the second reset transistor T7) to transmit a reset signal to the anode of the light emitting element LD, and the second scanning signal line 312 is configured to control the thin film transistor 21 (specifically, the adjusting transistor T8) to transmit an adjusting signal to the first pole of the driving transistor T3. The first scanning signal line 311 is electrically connected with the first auxiliary signal line 321, and the second scanning signal line 312 is electrically connected with the second auxiliary signal line 322. In the embodiment of the present application, the first scanning signal line 311 and the second scanning signal line 312 are not collinear, and the first scanning signal line 311 and the second scanning signal line 312 are arranged along the second direction Y. Therefore, the second reset transistor T7 and the adjusting transistor T8 are respectively connected to two different gate control signal lines 30.

[0079] Figure 14 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 14The end of the scanning signal line 31 is electrically connected with the end of the auxiliary signal line 32. The gate of the second reset transistor T7 in the first pixel region P1 is arranged to be disconnected with the gate of the second reset transistor T7 in the second pixel region P2. The end of the first scanning signal line 311 in the first pixel region P1 is electrically connected with the first end of the first auxiliary signal line 321, and the end of the first scanning signal line 311 in the second pixel region P2 is electrically connected with the second end of the first auxiliary signal line 321. The gate of the adjusting transistor T8 in the first pixel region P1 is arranged to be disconnected with the gate of the adjusting transistor T8 in the second pixel region P2. The end of the second scanning signal line 312 in the first pixel region P1 is electrically connected with the first end of the second auxiliary signal line 322, and the end of the second scanning signal line 312 in the second pixel region P2 is electrically connected with the second end of the second auxiliary signal line 322.

[0080] Optionally, referring to Figures 3-5 , the pixel driving circuit 20 further comprises a storage capacitor C. The vertical projection of the auxiliary signal line 32 on the substrate 10 is arranged along the second direction Y with the vertical projection of the storage capacitor C on the substrate 10, and the second direction Y is perpendicular to the first direction X. Along the second direction Y, the auxiliary signal line 32 is located on one side of the storage capacitor C. Perpendicular to the substrate 10, the auxiliary signal line 32 does not overlap with the storage capacitor C. The auxiliary signal line 32 in the embodiment of the present application is a line extending along the first direction X, which is not a light-shielding metal layer, and a light-shielding metal layer usually cannot avoid the storage capacitor C. The auxiliary signal line 32 in the embodiment of the present application is staggered with the storage capacitor C, which is not for the purpose of light-shielding, but for the purpose of increasing the light transmittance and reducing the transmission voltage drop of the scanning signal. A plurality of auxiliary signal lines 32 arranged along the second direction Y can be arranged in one pixel region P to reduce the transmission voltage drop of the scanning signal on the plurality of scanning signal lines 31.

[0081] Optionally, referring to Figure 3 , Figure 5 , Figure 12 and Figure 13 , the plurality of scanning signal lines 31 comprises an anode reset control signal line SCP2 and an adjusting control signal line SCP3. Along the second direction Y, the anode reset control signal line SCP2 and the adjusting control signal line SCP3 are located on the same side of the storage capacitor C. The auxiliary signal line 32 electrically connected with the anode reset control signal line SCP2 is a straight line segment, and the auxiliary signal line 32 electrically connected with the adjusting control signal line SCP3 is a straight line segment. Compared with a bending line segment or a curved line segment, a straight line segment has a simple structure and is not prone to over-etching and other problems, thereby reducing the process difficulty.

[0082] Exemplarily, referring to Figure 3 , Figure 5 , Figure 12 and Figure 13The anode reset control signal line SCP2 and the adjustment control signal line SCP3 are located between the fourth node N4 and the adjustment signal transmission line DVH. No other second metal layer M2 line or hole is located between the fourth node N4 and the adjustment signal transmission line DVH, so the auxiliary signal line 32 electrically connected to the anode reset control signal line SCP2 and the auxiliary signal line 32 electrically connected to the adjustment control signal line SCP3 do not need to be bent or curved to avoid obstacles.

[0083] Exemplarily, referring to Figure 12 and Figure 13 , the first auxiliary signal line 321 and the second auxiliary signal line 322 are straight line segments.

[0084] Optionally, referring to Figure 3 , Figure 5 , Figure 12 and Figure 13 , the scan signal line 31 includes a data control signal line SCP1 configured to control the thin film transistor 21 (specifically, a data writing transistor T2) to transmit a data signal to the first electrode of the drive transistor T3. The array substrate further includes a data line VDATA and a data line via 52, the data line VDATA being connected to a semiconductor trace 60 in a different layer through the data line via 52, the channel layer 202 being a portion of the semiconductor trace 60 overlapping the gate 201. The portion of the semiconductor trace 60 not overlapping the gate 201 is used as a connection line. Generally, the portion of the semiconductor trace 60 not overlapping the gate 201 is doped to improve conductivity. In the second direction Y, the data control signal line SCP1 is located on the side of the storage capacitor C away from the anode reset control signal line SCP2, and the data control signal line SCP1 is spaced apart from the data line via 52 by at least one scan signal line 31. The data control signal line SCP1 is far away from the data line via 52, and does not need to be bent or curved to avoid obstacles. The auxiliary signal line 32 electrically connected to the data control signal line SCP1 is a straight line segment.

[0085] Exemplarily, referring to Figure 3 , Figure 5 , Figure 12 and Figure 13 , in the second direction Y, the first scan line SN1 is located between the data control signal line SCP1 and the data line via 52. The data control signal line SCP1 is far away from the data line via 52.

[0086] Optionally, referring to Figure 3 and Figure 12The array substrate further comprises an adjusting signal transmission line DVH for transmitting an adjusting signal, the adjusting signal transmission line DVH extends along the first direction X. The film layer where the adjusting signal transmission line DVH is located is between the film layer where the adjusting control signal line SCP3 is located and the film layer where the auxiliary signal line 32 is located. The vertical projection of the adjusting control signal line SCP3 on the substrate 10 is staggered with the vertical projection of the adjusting signal transmission line DVH on the substrate 10. In the direction perpendicular to the substrate 10, the adjusting control signal line SCP3 and the adjusting signal transmission line DVH do not overlap. Thus, the adjusting signal transmission line DVH located between the film layer where the adjusting control signal line SCP3 is located and the film layer where the auxiliary signal line 32 is located does not overlap with the line-changing via hole 51 connecting the adjusting control signal line SCP3 and the auxiliary signal line 32, avoiding the unwanted electrical connection between the adjusting signal transmission line DVH and the adjusting control signal line SCP3.

[0087] Exemplarily, referring to Figure 3 、 Figure 4 and Figure 12 , the adjusting signal transmission line DVH is located in the second sub-gate metal layer MG, the adjusting control signal line SCP3 is located in the first metal layer M1, and the auxiliary signal line 32 is located in the second metal layer M2. The second sub-gate metal layer MG is located between the first metal layer M1 and the second metal layer M2. If the adjusting signal transmission line DVH is arranged to overlap with the adjusting control signal line SCP3, the line-changing via hole 51 connected from the second metal layer M2 to the first metal layer M1 is electrically connected with the adjusting signal transmission line DVH, causing the electrical connection between the adjusting signal transmission line DVH and the adjusting control signal line SCP3, resulting in the abnormal working of the pixel driving circuit 20.

[0088] Figure 15 Another top view structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application is shown in Figure 16 , Figure 15 is a partial structural schematic diagram of the pixel driving circuit shown in Figure 4 、 Figure 15 and Figure 16The scan signal line 31 includes a first sub-signal line 3101 and a second sub-signal line 3102. The gate 201 includes a first sub-gate 2011 and a second sub-gate 2012. In a direction perpendicular to the substrate 10, the first sub-gate 2011 is located between the channel layer 202 (specifically, the channel layer 202 in the oxide semiconductor layer IGZO) and the substrate 10, and the second sub-gate 2012 is located on a side of the channel layer 202 (specifically, the channel layer 202 in the oxide semiconductor layer IGZO) away from the substrate 10. The first sub-gate 2011 is a portion of the first sub-signal line 3101 overlapping the channel layer 202, and the second sub-gate 2012 is a portion of the second sub-signal line 3102 overlapping the channel layer 202. The first sub-signal line 3101 and / or the second sub-signal line 3102 are electrically connected to the auxiliary signal line 32 via the line switching via 51.

[0089] Exemplarily, referring to Figure 15 and Figure 16 The scan signal line 31 includes a first scan line SN1. The first scan line SN1 includes a first sub-scan line SN11 and a second sub-scan line SN12. The first sub-scan line SN11 is the first sub-signal line 3101, and the second sub-scan line SN12 is the second sub-signal line 3102. The first sub-scan line SN11 and the second sub-scan line SN12 are respectively electrically connected to two auxiliary signal lines 32 via two line switching vias 51.

[0090] It can be understood that the scan signal line 31 connected to the gate of the silicon transistor 211 is provided with the auxiliary signal line 32 for electrical connection, so as to reduce the voltage drop of the scan signal transmitted on the scan signal line 31 connected to the gate of the silicon transistor 211. The scan signal line 31 connected to the gate of the oxide transistor 212 is provided with the auxiliary signal line 32 for electrical connection, so as to reduce the voltage drop of the scan signal transmitted on the scan signal line 31 connected to the gate of the oxide transistor 212. Thus, the difference between the voltage drop of the scan signal of the silicon transistor 211 and the voltage drop of the scan signal of the oxide transistor 212 is reduced.

[0091] Figure 17 Another partial structure diagram of a pixel driving circuit provided by an embodiment of the present application is provided, referring to Figure 17 The first sub-scan line SN11 is the first sub-signal line 3101, and the second sub-scan line SN12 is the second sub-signal line 3102. The first sub-scan line SN11 is electrically connected to the auxiliary signal line 32 via the line switching via 51. The second sub-scan line SN12 is not electrically connected to the auxiliary signal line 32. In other embodiments, the second sub-scan line SN12 is electrically connected to the auxiliary signal line 32 via the line switching via 51, and the first sub-scan line SN11 is not electrically connected to the auxiliary signal line 32.

[0092] Figure 18This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 18 The first sub-signal line 3101 and the second sub-signal line 3102 are electrically connected to the same auxiliary signal line 32.

[0093] For example, refer to Figure 18 The first sub-scan line SN11 is electrically connected to the auxiliary signal line 32 through the line switching via 51, and the second sub-scan line SN12 is electrically connected to the auxiliary signal line 32 through the line switching via 51. The first sub-scan line SN11 and the second sub-scan line SN12 are electrically connected to the same auxiliary signal line 32.

[0094] Continue to refer to Figure 16 The auxiliary signal line 20 includes a first sub-auxiliary signal line 3201 and a second sub-auxiliary signal line 3202 spaced apart. The first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are arranged along a second direction Y. The switching via 51 includes a first switching via 511 and a second switching via 512. The first sub-signal line 3101 is electrically connected to the first sub-auxiliary signal line 3201 via the first switching via 511, and the second sub-signal line 3102 is electrically connected to the second sub-auxiliary signal line 3202 via the second switching via 512. The vertical projection of the first switching via 511 onto the substrate 10 is offset from the vertical projection of the second switching via 512 onto the substrate 10. Perpendicular to the substrate 10, the first line-changing via 511 and the second line-changing via 512 do not overlap, and are spaced apart. The first line-changing via 511 and the second line-changing via 512 are not electrically connected within the display area 101, thereby ensuring that the first sub-signal line 3101 and the second sub-signal line 3102 are not electrically connected within the display area 101.

[0095] For example, refer to Figure 16 The first sub-scan line SN11 is electrically connected to the first sub-auxiliary signal line 3201 through the first line-changing via 511, and the second sub-scan line SN12 is electrically connected to the second sub-auxiliary signal line 3202 through the second line-changing via 512. Perpendicular to the substrate 10, the first line-changing via 511 and the second line-changing via 512 do not overlap, and the first sub-scan line SN11 and the second sub-scan line SN12 are not electrically connected within the display area 101.

[0096] Figure 19 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 15 and Figure 19The array substrate further comprises a data line VDATA and a data line via 52. The data line VDATA is connected to the semiconductor trace 60 in the different layer through the data line via 52. The channel layer 202 is the part of the semiconductor trace 60 overlapping with the gate 201. The array substrate further comprises a reset signal transmission line VREF for transmitting a reset signal, the reset signal transmission line VREF extends along the first direction X. The auxiliary signal line 32 electrically connected with the first sub-signal line 3101 or the second sub-signal line 3102 is the third auxiliary signal line 323. Along the second direction Y, the third auxiliary signal line 323 is located between the reset signal transmission line VREF and the data line via 52. The third auxiliary signal line 323 comprises a first auxiliary signal line segment 3231, a second auxiliary signal line segment 3232 and a third auxiliary signal line segment 3233, the second auxiliary signal line segment 3232 connects the first auxiliary signal line segment 3231 and the third auxiliary signal line segment 3233. Along the second direction Y, the second auxiliary signal line segment 3232 is located on the side of the line changing via 51 away from the data line via 52. Along the second direction Y, the line changing via 51 is located between the second auxiliary signal line segment 3232 and the data line via 52. The second auxiliary signal line segment 3232 is the part of the third auxiliary signal line 323 protruding towards the side away from the data line via 52. In the embodiment of the present application, since the third auxiliary signal line 323 is close to the data line via 52, the distance between the third auxiliary signal line 323 and the data line via 52 is short, in order to avoid the data line via 52, the third auxiliary signal line 323 is arranged to be bent or curved.

[0097] Exemplarily, referring to Figure 15 and Figure 19 , along the second direction Y, the first scan line SN1 is located between the reset signal transmission line VREF (specifically, the first reset signal transmission line VREF1) and the data line via 52. The first sub-scan line SN11 is the first sub-signal line 3101, and the second sub-scan line SN12 is the second sub-signal line 3102. The first sub-scan line SN11 is electrically connected with the first sub-auxiliary signal line 3201 through the first line changing via 511. The second sub-scan line SN12 is electrically connected with the second sub-auxiliary signal line 3202 through the second line changing via 512. The first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are both the bent third auxiliary signal line 323. The first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are both wired around the data line via 52.

[0098] Figure 20 Another partial structure schematic diagram of a pixel driving circuit provided by the embodiment of the present application is provided, referring to Figure 15 and Figure 20The scanning signal line 31 includes a data control signal line SCP1 configured to control the thin film transistor 21 to transmit a data signal to the first electrode of the driving transistor T3. The pixel driving circuit 20 further includes a storage capacitor C. In the second direction Y, a third auxiliary signal line 323 is located between the storage capacitor C and the data control signal line SCP1. The third auxiliary signal line 323 is a straight line segment. Compared with a bent line segment or a curved line segment, the straight line segment has a simple structure and is less likely to cause over-etching and other problems, thereby reducing the process difficulty.

[0099] Exemplarily, referring to Figure 15 and Figure 20 In the second direction Y, the second scanning line SN2 is located between the storage capacitor C and the data control signal line SCP1. The third sub-scanning line SN21 is the first sub-signal line 3101, and the fourth sub-scanning line SN22 is the second sub-signal line 3102. The third sub-scanning line SN21 is electrically connected to the first sub-auxiliary signal line 3201 through the first line-changing via 511. The fourth sub-scanning line SN22 is electrically connected to the second sub-auxiliary signal line 3202 through the second line-changing via 512. The first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are both the third auxiliary signal line 323. The first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are both straight line segments.

[0100] Optionally, referring to Figure 3 , Figure 12 or Figure 15 The array substrate further includes a reset signal transmission line VREF and a reset signal auxiliary transmission line VREF’. The reset signal transmission line VREF is configured to transmit a reset signal. The reset signal transmission line VREF extends in the first direction X, and the reset signal transmission line VREF and the reset signal auxiliary transmission line VREF’ are in different layers and are electrically connected through the connection via 53. In the direction perpendicular to the substrate 10, the reset signal auxiliary transmission line VREF’ overlaps the line-changing via 51. Thus, the light-blocking area of the line-changing via 51 overlaps the light-blocking area of the reset signal auxiliary transmission line VREF’, the common light-blocking area of the line-changing via 51 and the reset signal auxiliary transmission line VREF’ is reduced, and the light transmittance is increased.

[0101] Exemplarily, referring to Figure 3The reset signal transmission line VREF includes a first reset signal transmission line VREF1 and a second reset signal transmission line VREF2. The reset signal auxiliary transmission line VREF' extends along the second direction Y. The reset signal auxiliary transmission line VREF' includes a first reset signal auxiliary transmission line VREF3 and a second reset signal auxiliary transmission line VREF4. The first reset signal transmission line VREF1 and the first reset signal auxiliary transmission line VREF3 are electrically connected through the connection via 53. The second reset signal transmission line VREF2 and the second reset signal auxiliary transmission line VREF4 are electrically connected through the connection via 53. In the direction perpendicular to the substrate 10, the first reset signal auxiliary transmission line VREF3 overlaps the wire changing via 51 at the positions of the anode reset control signal line SCP2 and the adjustment control signal line SCP3. In the direction perpendicular to the substrate 10, the second reset signal auxiliary transmission line VREF4 overlaps the wire changing via 51 at the position of the data control signal line SCP1.

[0102] Optionally, referring to Figure 3 , Figure 4 , Figure 12 or Figure 15 , the thin film transistor 21 includes a drive transistor T3 for providing a drive current for the light emitting element LD. The array substrate further includes a light shielding line 40 between the substrate 10 and the drive transistor T3. The light shielding line 40 is located in the light shielding metal layer M0 between the silicon semiconductor layer POLY and the substrate 10. The light shielding line 40 extends along the second direction Y. In the direction perpendicular to the substrate 10, the light shielding line 40 overlaps the wire changing via 51. Thus, the light shielding area of the wire changing via 51 overlaps the light shielding area of the light shielding line 40, reducing the common light shielding area of the wire changing via 51 and the light shielding line 40, and increasing the light transmittance.

[0103] Illustratively, referring to Figure 3 , in the direction perpendicular to the substrate 10, the light shielding line 40 overlaps the wire changing via 51 at the position of the anode reset control signal line SCP2.

[0104] Illustratively, referring to Figure 3 , in the direction perpendicular to the substrate 10, the light shielding line 40 overlaps the connection via 53. For example, in the direction perpendicular to the substrate 10, the light shielding line 40 overlaps the connection via 53 at the position of the first reset signal transmission line VREF1. Thus, the light shielding area of the connection via 53 overlaps the light shielding area of the light shielding line 40, reducing the common light shielding area of the connection via 53 and the light shielding line 40, and increasing the light transmittance.

[0105] Illustratively, referring to Figure 3The light-shielding line 40 overlaps the driving transistor T3 in a direction perpendicular to the substrate 10, and is used to shield light projected from one side of the substrate 10 to the driving transistor T3, so as to reduce the influence of the photo-generated carriers on the channel layer 202 of the driving transistor T3.

[0106] In some embodiments, the light-shielding line 40 can also be omitted. The light-shielding metal layer M0 is a newly added metal layer.

[0107] In some embodiments, the light-shielding line 40 extending along the second direction Y can also be replaced by a light-shielding layer. The light-shielding layer is an entire film layer, not a line, which will reduce the light transmittance. The light-shielding layer has no certain extension direction. The light-shielding layer overlaps a plurality of scan signal lines 31 in a direction perpendicular to the substrate 10. When the light-shielding layer is used as an auxiliary signal line 32, it can only be electrically connected to the scan signal line 31 transmitting the same scan signal, and cannot be electrically connected to two scan signal lines 31 transmitting different scan signals. Moreover, the newly added light-shielding metal layer M0 will increase the thickness of the array substrate.

[0108] Optionally, referring to Figure 8 and Figure 9 The plurality of pixel regions P include a first pixel region P1 and a second pixel region P2 arranged adjacent to each other along the first direction X, and a boundary line LN is formed between the first pixel region P1 and the second pixel region P2. The portion of the auxiliary signal line 32 in the first pixel region P1 is axially symmetrical to the portion of the auxiliary signal line 32 in the second pixel region P2 about the boundary line LN.

[0109] Optionally, referring to Figure 8 and Figure 9 The pixel driving circuit 20 located in the first pixel region P1 is a first pixel driving circuit 2001, and the pixel driving circuit 20 located in the second pixel region P2 is a second pixel driving circuit 2002. The first pixel driving circuit 2001 and the second pixel driving circuit 2002 are at least partially axially symmetrical about the boundary line LN. In the embodiments of the present application, the pixel driving circuit 20 adopts a mirror image design.

[0110] Exemplarily, referring to Figure 3 and Figure 8 The storage capacitor C of the first pixel driving circuit 2001 and the storage capacitor C of the second pixel driving circuit 2002 are axially symmetrical about the boundary line LN, and the thin film transistor 21 (for example, the driving transistor T3) of the first pixel driving circuit 2001 and the thin film transistor 21 (for example, the driving transistor T3) of the second pixel driving circuit 2002 are axially symmetrical about the boundary line LN.

[0111] Exemplarily, referring to Figure 3 and Figure 8The first power supply line VDD passing through the first pixel region P1 is axially symmetrical to the first power supply line VDD passing through the second pixel region P2 about the boundary line LN. The data line VDATA passing through the first pixel region P1 is axially symmetrical to the data line VDATA passing through the second pixel region P2 about the boundary line LN. The first reset signal auxiliary transmission line VREF3 passing through the first pixel region P1 is axially symmetrical to the first reset signal auxiliary transmission line VREF3 passing through the second pixel region P2 about the boundary line LN. The second reset signal auxiliary transmission line VREF4 passing through the first pixel region P1 is axially symmetrical to the second reset signal auxiliary transmission line VREF4 passing through the second pixel region P2 about the boundary line LN. The light shielding line 40 passing through the first pixel region P1 is axially symmetrical to the light shielding line 40 passing through the second pixel region P2 about the boundary line LN.

[0112] Exemplarily, referring to Figure 3 and Figures 3-5 , two adjacent pixel regions P along the first direction X share the same first power supply line VDD, so that two first power supply lines VDD do not need to be respectively arranged for the two pixel regions P, the number of the first power supply lines VDD is reduced, and the light transmittance is improved.

[0113] Optionally, referring to Figures 3-5 , the array substrate further comprises a reset signal transmission line VREF for transmitting a reset signal, the reset signal transmission line VREF extends along the first direction X, and the reset signal transmission line VREF is in the same layer as the channel layer 202. The reset signal transmission line VREF is in the same layer as the semiconductor trace 60, and when the reset signal transmission line VREF is electrically connected to the semiconductor trace 60, a connection via hole does not need to be arranged for the reset signal transmission line VREF and the semiconductor trace 60, the number of the connection via holes is reduced, and the light transmittance is improved.

[0114] Exemplarily, referring to Figure 21 , the reset signal transmission line VREF comprises a first reset signal transmission line VREF1 and a second reset signal transmission line VREF2. The first reset signal transmission line VREF1 and the second reset signal transmission line VREF2 are both in the same layer as the channel layer 202. The first reset signal transmission line VREF1 and the second reset signal transmission line VREF2 are both located in the silicon semiconductor layer POLY. Along the second direction Y, after passing through the second reset transistor T7, the semiconductor trace 60 is directly connected to the second reset signal transmission line VREF2 in the same layer, and a connection via hole 53 does not need to be arranged for the second reset signal transmission line VREF2 and the semiconductor trace 60.

[0115] Figure 21 Another top view structural schematic diagram of a pixel driving circuit is provided for an embodiment of the present application, referring to Figure 21The first reset signal transmission line VREF1 is in the same layer as the first plate C1 of the storage capacitor C, and the first reset signal transmission line VREF1 is located in the first metal layer M1. The second reset signal transmission line VREF2 is in the same layer as the second plate C2 of the storage capacitor C, and the second reset signal transmission line VREF2 is located in the first sub-gate metal layer MC. The resistances of the first metal layer M1 and the first sub-gate metal layer MC are both smaller than the resistance of the silicon semiconductor layer POLY, thereby providing better conductivity.

[0116] Exemplarily, referring to Figure 22 , along the second direction Y, after passing through the second reset transistor T7, the semiconductor wire 60 is electrically connected to the second reset signal transmission line VREF2 in the different layer through the connection via 53.

[0117] Figure 3 For Figure 3 , referring to Figure 4 , Figure 22 and Figure 23 , the pixel driving circuit 20 further includes a storage capacitor C, the storage capacitor C includes a first plate C1 and a second plate C2, and the first plate C1 is located between the second plate C2 and the substrate 10. The array substrate further includes a semiconductor wire 60, a connection via 53, and a connection line 81. At least part of the semiconductor wire 60 extends along the second direction Y, the channel layer 202 is part of the semiconductor wire 60 overlapping with the gate 201, and the channel layer 202 includes an oxide semiconductor material. The semiconductor wire 60 is electrically connected to the connection line 81 through the connection via 53, and the connection line 81 is in the same layer as the auxiliary signal line 32.

[0118] Figure 23 For another partial structure schematic diagram of the pixel driving circuit provided by the embodiment of the present application, referring to Figure 24 , the semiconductor wire 60 connected to the first node N1 is located in the oxide semiconductor layer IGZO. The semiconductor wire 60 located in the oxide semiconductor layer IGZO extends along the second direction Y and is connected to the first plate C1 of the storage capacitor C through the connection line 81. In the embodiment of the present application, the connection line 81 is in the same layer as the first plate C1, so that the connection line 81 is electrically connected to the first plate C1 in the same layer, and a connection via does not need to be arranged for the connection line 81 and the first plate C1, thereby reducing the number of connection vias and increasing the light transmittance.

[0119] Figure 3 For another top view structure schematic diagram of the array substrate provided by the embodiment of the present application, referring to Figure 24 and Figure 25The array substrate further comprises a non-display area 102 located at the periphery of the display area 101. The array substrate comprises a virtual pixel driving circuit 82, a repair line 70 and a welding layer 83. The virtual pixel driving circuit 82 is located in the non-display area 102. The repair line 70 is at least partially located in the display area 101, and the repair line 70 can extend from the display area 101 to the non-display area 102. The repair line 70 is electrically connected with the virtual pixel driving circuit 82. The welding layer 83 is located in the display area 101, and one end of the welding layer 83 is electrically connected with the anode of the light emitting element LD. In a direction perpendicular to the substrate 10, the other end of the welding layer 83 is overlapped with the repair line 70. When the pixel driving circuit 20 in the display area 101 fails, the overlapped welding layer 83 and the repair line 70 can be connected together by means of laser welding, so as to electrically connect the anode of the light emitting element LD with the virtual pixel driving circuit 82 in the non-display area 102, and drive the light emitting element LD to emit light by the virtual pixel driving circuit 82 in the non-display area 102.

[0120] Figure 3 For Figure 3 the pixel driving circuit shown in FIG. 1, referring to FIG. 2, Figure 4 , Figure 25 and Figure 26 , the thin film transistor 21 comprises a source 203 and a drain 204. The welding layer 83, the source 203 and the drain 204 are in the same layer, and the welding layer 83 is located in the second metal layer M2. The gate 201 comprises a first sub-gate 2011 and a second sub-gate 2012. In a direction perpendicular to the substrate 10, the first sub-gate 2011 is located between the channel layer 202 and the substrate 10, and the second sub-gate 2012 is located on the side of the channel layer 202 away from the substrate 10. The repair line 70 is in the same layer with the first sub-gate 2011, and the repair line 70 is located in the first sub-gate metal layer MC. Thus, the repair line 70 and the first sub-gate 2011 can be formed simultaneously in the same process, thereby reducing the process procedure.

[0121] Figure 4 For another pixel driving circuit provided by the embodiment of the present application, referring to FIG. 3 and FIG. 4, Figure 26 and Figure 27 , the repair line 70 is in the same layer with the second sub-gate 2012, and the repair line 70 is located in the second sub-gate metal layer MG. Thus, the repair line 70 and the second sub-gate 2012 can be formed simultaneously in the same process, thereby reducing the process procedure. Further, in a direction perpendicular to the substrate 10, the repair line 70 is relatively close to the second sub-gate 2012, so that the connection via hole 53 between the repair line 70 and the second sub-gate 2012 can be set to a smaller depth, which is beneficial to simplify the manufacturing process.

[0122] Figure 27 For another pixel driving circuit provided by the embodiment of the present application, referring toFigure 27 The repair line 70 includes a first sub-repair line 71 and a second sub-repair line 72. The first sub-repair line 71 is in the same layer as the first sub-gate 2011, and the first sub-repair line 71 is located in the first sub-gate metal layer MC. The second sub-repair line 72 is in the same layer as the second sub-gate 2012, and the second sub-repair line 72 is located in the second sub-gate metal layer MG. In the direction perpendicular to the substrate 10, the first sub-repair line 71 and the second sub-repair line 72 overlap the same solder layer 83. When the pixel driving circuit 20 in the display area 101 fails, the first sub-repair line 71 and the second sub-repair line 72 can be connected together with the same solder layer 83 by means such as laser soldering. Since two repair lines 70 are configured for the same solder layer 83, the repair rate is improved.

[0123] For example, referring to Figure 28 In the direction perpendicular to the substrate 10, the first sub-repair line 71 and the second sub-repair line 72 are staggered, and the first sub-repair line 71 and the second sub-repair line 72 do not overlap. Thus, the overlapping position (i.e., the soldering position) of the first sub-repair line 71 and the solder layer 83 is staggered with the overlapping position (i.e., the soldering position) of the second sub-repair line 72 and the solder layer 83. The present embodiment provides two soldering positions for one pixel area P, and two connection vias are arranged at the two soldering positions. Even if one of the two connection vias fails, it will not affect the electrical connection between the virtual pixel driving circuit 82 and the light emitting element LD, and the repair rate is improved.

[0124] Figure 28 Another partial structure diagram of a pixel driving circuit provided by the present embodiment is shown in Figure 29 In the direction perpendicular to the substrate 10, the first sub-repair line 71 and the second sub-repair line 72 overlap, and any two of the first sub-repair line 71, the second sub-repair line 72 and the solder layer 83 overlap.

[0125] Figure 29 A cross-sectional structure diagram of a display panel provided by the present embodiment is shown in Figure 29 The display panel includes the array substrate in any one of the above embodiments and a plurality of light emitting elements LD (one light emitting element LD is shown in Figure 29 The light emitting element LD is electrically connected to the pixel driving circuit 20, and the light emitting element LD is configured to emit light under the drive of the pixel driving circuit 20.

[0126] For example, referring to Figure 30 The light emitting element LD includes an anode RE, a light emitting functional layer 84 and a cathode COM, and the light emitting functional layer 84 is located between the anode RE and the cathode COM. The light emitting functional layer 84 can include organic light emitting material and / or inorganic light emitting material.

[0127] Figure 30 A schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 1. ​ The display device provided by the embodiment of the present application can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc. The embodiment of the present application does not make special limitations on this.

[0128] Note that the above are only preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises a display area comprising a plurality of pixel areas; A substrate, pixel driving circuits and scanning signal lines, at least part of the pixel driving circuits and the scanning signal lines are located in the display area, on the same side of the substrate, and the scanning signal lines extend along a first direction; At least part of the pixel driving circuits are located in the pixel areas and comprise thin film transistors; the thin film transistors comprise a gate and a channel layer, and the gate is a part of the scanning signal lines overlapping with the channel layer; The array substrate further comprises auxiliary signal lines, the auxiliary signal lines are located in the display area and extend along the first direction; the resistance of the auxiliary signal lines is smaller than that of the scanning signal lines, the auxiliary signal lines are in different layers from the scanning signal lines, and the auxiliary signal lines are electrically connected to the scanning signal lines through line-changing via holes; A plurality of the scanning signal lines in a same line are electrically connected to a same auxiliary signal line.

2. The array substrate of claim 1, wherein, The film layer in which the auxiliary signal lines are located is on a side of the film layer in which the scanning signal lines are located away from the substrate.

3. The array substrate of claim 2, wherein, The thin film transistors comprise a source and a drain, and the auxiliary signal lines, the source and the drain are in the same layer.

4. The array substrate of claim 1, wherein, In the first direction, the length of the scanning signal lines is smaller than that of the auxiliary signal lines.

5. The array substrate of claim 1, wherein, In a direction perpendicular to the substrate, the scanning signal lines and the auxiliary signal lines overlap in a region other than the region in which the line-changing via holes are located.

6. The array substrate of claim 1, wherein, The end of the scanning signal line is electrically connected to the end of the auxiliary signal line.

7. The array substrate of claim 1, wherein, A plurality of the scanning signal lines in a same line comprise first and second scanning signal lines arranged at intervals, and the first and second scanning signal lines are located in a same pixel area.

8. The array substrate of claim 7, wherein, The thin film transistors comprise driving transistors for providing driving current for light-emitting elements; The first scanning signal line is configured to control the thin film transistors to transmit a reset signal to an anode of the light-emitting element, and the second scanning signal line is configured to control the thin film transistors to transmit an adjusting signal to a first electrode of the driving transistors.

9. The array substrate of claim 1, wherein, The scanning signal line comprises first and second signal line segments connected to each other, the first and second signal line segments are located in a same pixel area, and the first and second signal line segments each comprise the gate.

10. The array substrate of claim 1, wherein, A plurality of the pixel areas comprise first and second pixel areas arranged adjacent to each other along the first direction; A plurality of the scanning signal lines in a same line comprise third and fourth scanning signal lines arranged at intervals, the third scanning signal line is located in the first pixel area, and the fourth scanning signal line is located in the second pixel area.

11. The array substrate of claim 1, wherein, A plurality of the pixel areas comprise first and second pixel areas arranged adjacent to each other along the first direction; The scanning signal line comprises third and fourth signal line segments connected to each other, the third signal line segment is located in the first pixel area and comprises the gate, and the fourth signal line segment is located in the second pixel area and comprises the gate.

12. The array substrate of claim 1, wherein, A plurality of the auxiliary signal lines comprise first and second auxiliary signal lines arranged along a second direction, and the second direction intersects the first direction; The thin film transistors comprise driving transistors for providing driving current for light-emitting elements; The plurality of scan signal lines include a first scan signal line and a second scan signal line, the first scan signal line is configured to control the thin film transistor to transmit a reset signal to an anode of the light emitting element, and the second scan signal line is configured to control the thin film transistor to transmit an adjustment signal to a first electrode of the drive transistor. The first scan signal line is electrically connected with the first auxiliary signal line, and the second scan signal line is electrically connected with the second auxiliary signal line.

13. The array substrate of claim 1, wherein, The pixel driving circuit further includes a storage capacitor. The vertical projection of the auxiliary signal line on the substrate is arranged along a second direction with the vertical projection of the storage capacitor on the substrate, and the second direction intersects the first direction.

14. The array substrate of claim 13, wherein, The thin film transistor includes a drive transistor for providing a drive current for the light emitting element. The plurality of scan signal lines include an anode reset control signal line and an adjustment control signal line, the anode reset control signal line is configured to control the thin film transistor to transmit a reset signal to an anode of the light emitting element, and the adjustment control signal line is configured to control the thin film transistor to transmit an adjustment signal to a first electrode of the drive transistor. Along the second direction, the anode reset control signal line and the adjustment control signal line are located on the same side of the storage capacitor. The auxiliary signal line electrically connected with the anode reset control signal line is a straight line segment, and the auxiliary signal line electrically connected with the adjustment control signal line is a straight line segment.

15. The array substrate of claim 14, wherein, The scan signal line includes a data control signal line, the data control signal line is configured to control the thin film transistor to transmit a data signal to a first electrode of the drive transistor. The array substrate further includes a data line and a data line via, the data line is connected to a semiconductor trace in a different layer through the data line via, and the channel layer is a portion of the semiconductor trace overlapping the gate electrode; Along a second direction, the data control signal line is located on a side of the storage capacitor away from the anode reset control signal line, and is spaced apart from the data line via by at least one scan signal line; The auxiliary signal line electrically connected with the data control signal line is a straight line segment.

16. The array substrate of claim 14, wherein, Further including an adjustment signal transmission line for transmitting an adjustment signal, the adjustment signal transmission line extends along the first direction; The film layer in which the adjustment signal transmission line is located is between the film layer in which the adjustment control signal line is located and the film layer in which the auxiliary signal line is located; The vertical projection of the adjustment control signal line on the substrate is staggered with the vertical projection of the adjustment signal transmission line on the substrate.

17. The array substrate of claim 1, wherein, The scan signal line includes a first sub-signal line and a second sub-signal line; The gate electrode includes a first sub-gate electrode and a second sub-gate electrode, and in a direction perpendicular to the substrate, the first sub-gate electrode is located between the channel layer and the substrate, and the second sub-gate electrode is located on a side of the channel layer away from the substrate; The first sub-gate electrode is a portion of the first sub-signal line overlapping the channel layer, and the second sub-gate electrode is a portion of the second sub-signal line overlapping the channel layer. The first sub-signal line and / or the second sub-signal line are electrically connected with the auxiliary signal line through the line-changing via.

18. The array substrate of claim 17, wherein, The auxiliary signal line comprises a first sub-auxiliary signal line and a second sub-auxiliary signal line arranged at intervals. The line-changing via comprises a first line-changing via and a second line-changing via, the first sub-signal line is electrically connected with the first sub-auxiliary signal line through the first line-changing via, and the second sub-signal line is electrically connected with the second sub-auxiliary signal line through the second line-changing via. The vertical projection of the first line-changing via on the substrate is staggered with the vertical projection of the second line-changing via on the substrate.

19. The array substrate of claim 17, wherein, Further comprising a data line and a data line via, the data line is connected to a semiconductor trace in a different layer through the data line via, and the channel layer is a portion of the semiconductor trace overlapping the gate electrode. The array substrate further comprises a reset signal transmission line for transmitting a reset signal, and the reset signal transmission line extends along the first direction. The auxiliary signal line electrically connected with the first sub-signal line or the second sub-signal line is a third auxiliary signal line, and along a second direction, the third auxiliary signal line is located between the reset signal transmission line and the data line via, and the second direction intersects the first direction. The third auxiliary signal line comprises a first auxiliary signal line segment, a second auxiliary signal line segment and a third auxiliary signal line segment, the second auxiliary signal line segment connects the first auxiliary signal line segment and the third auxiliary signal line segment, and along the second direction, the second auxiliary signal line segment is located on a side of the line-changing via away from the data line via.

20. The array substrate of claim 17, wherein, The scan signal line comprises a data control signal line configured to control the thin film transistor to transmit a data signal to a first electrode of a drive transistor. The pixel drive circuit further comprises a storage capacitor. The auxiliary signal line electrically connected with the first sub-signal line or the second sub-signal line is a third auxiliary signal line, and along a second direction, the third auxiliary signal line is located between the storage capacitor and the data control signal line, and the second direction intersects the first direction. The third auxiliary signal line is a straight line segment.

21. The array substrate of claim 1, wherein, Further comprising a reset signal transmission line and a reset signal auxiliary transmission line. The reset signal transmission line is configured to transmit a reset signal, extends along the first direction, is in a different layer from the reset signal auxiliary transmission line, and is electrically connected with the reset signal auxiliary transmission line through a connection via. Perpendicular to the direction of the substrate, the reset signal auxiliary transmission line overlaps the line-changing via.

22. The array substrate of claim 1, wherein, The thin film transistor comprises a drive transistor for providing a drive current for a light-emitting element. The array substrate further comprises a light-shielding line located between the substrate and the drive transistor, extending along a second direction, and the second direction intersects the first direction. Perpendicular to the direction of the substrate, the light-shielding line overlaps the line-changing via.

23. The array substrate of claim 1, wherein, A plurality of the pixel regions comprise a first pixel region and a second pixel region arranged adjacent along the first direction, and a boundary line is formed between the first pixel region and the second pixel region. The part of the auxiliary signal line in the first pixel region is axially symmetrical to the part of the auxiliary signal line in the second pixel region about the boundary line.

24. The array substrate of claim 23, wherein, The pixel driving circuit in the first pixel region is a first pixel driving circuit, and the pixel driving circuit in the second pixel region is a second pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit are at least partially axially symmetrical about the boundary line.

25. The array substrate of claim 1, wherein, A reset signal transmission line for transmitting a reset signal is further included, and the reset signal transmission line extends along the first direction and is in the same layer as the channel layer.

26. The array substrate of claim 1, wherein, The pixel driving circuit further includes a storage capacitor, and the storage capacitor includes a first plate and a second plate, and the first plate is located between the second plate and the substrate. The array substrate further includes a semiconductor trace, a connection via, and a connection line; at least part of the semiconductor trace extends along a second direction, the channel layer is a part of the semiconductor trace overlapping the gate, and the channel layer includes an oxide semiconductor material. The semiconductor trace is electrically connected to the connection line through the connection via, and the connection line is in the same layer as the first plate.

27. The array substrate of claim 1, wherein, A non-display region is further included, and the non-display region is located at the periphery of the display region. A virtual pixel driving circuit, a repair line, and a welding layer are further included; the virtual pixel driving circuit is located in the non-display region, the repair line is at least partially located in the display region and is electrically connected to the virtual pixel driving circuit; and the welding layer is located in the display region. One end of the welding layer is electrically connected to the anode of the light-emitting element, and the other end of the welding layer overlaps the repair line in a direction perpendicular to the substrate.

28. The array substrate of claim 27, wherein, The thin-film transistor includes a source and a drain, and the welding layer, the source, and the drain are in the same layer; The gate includes a first sub-gate and a second sub-gate, and the first sub-gate is located between the channel layer and the substrate in a direction perpendicular to the substrate, and the second sub-gate is located on the side of the channel layer away from the substrate; The repair line is in the same layer as the first sub-gate; or The repair line is in the same layer as the second sub-gate; or The repair line includes a first sub-repair line and a second sub-repair line, the first sub-repair line is in the same layer as the first sub-gate, and the second sub-repair line is in the same layer as the second sub-gate. The display panel includes the array substrate and a plurality of light-emitting elements.

29. A display panel, comprising: The light-emitting elements are electrically connected to the pixel driving circuits and are configured to emit light under the driving of the pixel driving circuits. The display panel includes the array substrate and a plurality of light-emitting elements.

30. A display device comprising: The light-emitting elements are electrically connected to the pixel driving circuits and are configured to emit light under the driving of the pixel driving circuits.

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