A high-speed wavelet denoising system and method
By designing an extended convolution matrix module and a threshold denoising module inside the FPGA, the data processing flow was optimized, solving the problem of excessive power consumption in the wavelet transform system. This resulted in faster computation speed and lower power consumption, while maintaining system flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-17
- Publication Date
- 2026-03-20
AI Technical Summary
Existing wavelet transform systems consume too much power, which reduces system flexibility and increases computational complexity, leading to increased FPGA area requirements.
A wavelet denoising system was designed, including an ADC module, a DMA module, a main memory module, a coprocessor module, a CPU, and a ROM. It utilizes the extended convolution matrix module and threshold denoising module inside the FPGA, and performs data processing through fixed-point units and systolic arrays to reduce the CPU's computational burden and optimize the data transmission process.
Without increasing the circuit area, the computation speed is improved, the system power consumption is reduced, and the real-time performance and flexibility of wavelet transform are maintained.
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Figure CN116361623B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a high-speed wavelet denoising system and method, and belongs to the field of hardware acceleration and signal processing. BACKGROUND
[0002] With the development of the integrated circuit industry, the application field of a chip integration-system on chip (SoC) of an information system core is continuously expanded, and a chip can complete the functions required to be realized by an electronic system.
[0003] As a new type of transform analysis method, the wavelet transform overcomes the shortcoming that the window size of a short-time Fourier transform cannot be changed, simultaneously obtains time domain and frequency domain resolution, and has been widely applied in the fields of signal analysis and signal filtering.
[0004] Early wavelet transforms are usually implemented in a software mode, although the expected effect can be well achieved, but the implementation method cannot quickly perform the wavelet transform. In order to improve the operation speed, the wavelet transform must be implemented on hardware.
[0005] In early hardware implementation of the wavelet transform, Li Qiushuang et al. implement the wavelet transform on an STM32 chip, and the designed power quality detection device reduces the cost, reduces the power consumption and improves the measurement accuracy (Li Qiushuang, Yuan Mingting. Design and implementation of power quality online detection device based on STM32 chip [J]. Modern electronic technology, 2012, 35 (20): 180-182 + 185. DOI: 10.16652 / j.issn.1004-373x.2012.20.011.). In later research, with the improvement of the speed requirement of the algorithm, the FPGA is applied, and Fu Lei implements a real-time image compression algorithm on the FPGA, and further improves the speed of the wavelet transform algorithm (Fu Lei. Implementation of real-time image compression algorithm based on FPGA [D]. Xi'an University of Electronic Science and Technology, 2014.). However, simultaneously improving the operation complexity and the transform speed will increase the power consumption of the whole system, and the area of the FPGA needs to be increased, which will lead to a large circuit area, is not conducive to integration, and reduces the flexibility of the system. SUMMARY
[0006] In order to solve the problem of high power consumption existing in the current wavelet transform system, the application provides a high-speed wavelet denoising system and method, and the technical scheme is as follows:
[0007] The first purpose of the application is to provide a wavelet denoising system, which comprises an ADC module, a DMA module, a main memory module, a coprocessor module, a CPU and a ROM.
[0008] The ADC module converts the input analog signal into a digital signal.
[0009] The DMA module transmits the digital signal into the main memory;
[0010] The CPU dispatches the digital signal from the main memory into the extended convolution matrix module in the CPU through a bus protocol, arranges the collected floating-point data into a matrix data stream, and transmits the matrix data stream to the coprocessor module through a system bus; the CPU controls the ROM to load the existing high-pass filter coefficient and low-pass filter coefficient weight into the PE fixed-point data multiply-accumulator unit of the systolic array operation structure through a bus.
[0011] The coprocessor module adopts a systolic array to perform wavelet decomposition, and the calculation result is transmitted to the CPU through a bus protocol.
[0012] Optionally, the coprocessor module comprises a fixed-point unit and a systolic array.
[0013] The fixed-point unit converts the floating-point data into fixed-point data, and the data is transmitted into the systolic array.
[0014] In the calculation process of the systolic array, the input data is horizontally propagated from left to right, and the wavelet filter coefficient and the output data are vertically propagated from top to bottom; according to the set number N of wavelet transform, after one round of wavelet decomposition, the data is separated into a detail component cA1 and an approximate component cD1 by a data selection module, the approximate component cD1 is reloaded into the systolic array operation structure for a second round of decomposition, and the result data is obtained after N rounds.
[0015] Optionally, the wavelet denoising system further comprises a downsampling module.
[0016] The downsampling module extracts even rows of the approximate component and the detail component for point sampling and recombination, after the downsampling process is completed, at this time, the approximate component of the upper layer is input into the RAM to enter the systolic array for a second round of wavelet decomposition through the DMA module, and the detail component enters the RAM for storage.
[0017] Optionally, the wavelet denoising system further comprises a soft threshold filter module, which filters the signal output by the downsampling module, and the soft threshold function is:
[0018]
[0019] The soft threshold function sets the wavelet coefficient with an absolute value less than a threshold λ to 0, and retains or shrinks the coefficient with a larger absolute value for the detail component cA.
[0020] The second object of the present application is to provide a wavelet denoising method, which is realized based on the wavelet denoising system according to any one of the preceding claims, and comprises the following steps:
[0021] Step 1: The ADC module converts the input analog signal into a digital signal;
[0022] Step 2: The DMA module transmits the digital signal into the main memory;
[0023] Step 3: The CPU schedules the digital signal from the main memory to the extended convolution matrix module in the CPU via the bus protocol, arranges the collected floating-point data into a matrix data stream, and then transmits it to the coprocessor module through the system bus;
[0024] Step 4: The CPU controls the ROM via the bus to load the existing high-pass filter coefficients and low-pass filter coefficient weights into the PE fixed-point data multiplier-accumulator unit of the systolic array arithmetic structure;
[0025] Step 5: The pulsating array performs wavelet decomposition calculation on the input data. The input data propagates horizontally from left to right, while the wavelet filter coefficients and output data propagate vertically from top to bottom.
[0026] Step 6: According to the set number of wavelet transform rounds N, after one round of wavelet decomposition, the data will be separated into detail component cA1 and approximate component cD1 by the data selection module. The approximate component cD1 will be reloaded into the pulse array operation structure for a second round of decomposition. After a total of N rounds, the result data is obtained.
[0027] Optionally, the extended convolution matrix module expands one-dimensional data into a matrix.
[0028] A third objective of this invention is to provide a wavelet denoising device, comprising:
[0029] A signal acquisition device, used to acquire signals to be processed;
[0030] The wavelet denoising system described in any of the above items is used to perform wavelet denoising on the acquired signal;
[0031] A data output device used to output the denoised signal data.
[0032] Optionally, the signal acquisition device includes a sensor.
[0033] Optionally, the data output device includes a computer.
[0034] The beneficial effects of this invention are:
[0035] The wavelet transform system and method of the present application, by utilizing the similarity of matrix expansion and the repeatability of signal denoising, designs an expansion convolution matrix module and a threshold denoising module in the FPGA, and the matrix expansion and threshold denoising are performed by the FPGA, so as to reduce the operation burden of the CPU and improve the operation speed, and only the clock instruction adjustment of the CPU is needed to complete the expansion of the convolution matrix and the denoising of the signal. The difference from the existing convolution operation structure is that the present application designs a data circulation mode with a fixed-point unit, a dequantization module and a DMA as the main structure according to the data flow characteristics of the systolic array calculation structure. The parallel calculation characteristics of the FPGA are utilized to shorten the important path of the system and improve the overall operation performance of the system.
[0036] The present application solves the problem of high power consumption of high-speed wavelet transform in the hardware implementation of wavelet transform by designing a SoC architecture, optimizing the data transmission process of wavelet transform, reducing CPU instruction scheduling and fixed-point quantization, etc., and achieves the reduction of power consumption while ensuring the real-time performance of wavelet transform. Compared with the previous hardware implementation method, the calculation is simpler, and the limited area of the FPGA is reused, that is, the present application improves the operation speed and reduces the system power consumption without increasing the circuit area. BRIEF DESCRIPTION OF DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0038] Figure 1 The architecture diagram of the SoC in the present application is shown.
[0039] Figure 2 The structure diagram of the co-processor and the internal data flow diagram in the present application are shown.
[0040] Figure 3 The flow diagram of data fixed-pointing in the present application is shown.
[0041] Figure 4 The internal circuit of the fixed-pointing unit in the present application is shown.
[0042] Figure 5 The pulsation process diagram in the systolic array structure in the present application is shown.
[0043] Figure 6 The multiply-accumulator circuit of the PE operation unit in the present application is shown. DETAILED DESCRIPTION
[0044] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will make further detailed description to the embodiments of the present application in combination with the drawings.
[0045] Embodiment one:
[0046] The embodiment provides a wavelet denoising system, referring to Figure 1 , comprising an ADC module, a DMA module, a main memory module, a coprocessor module, a CPU and a ROM.
[0047] The ADC module converts the input analog signal into a digital signal.
[0048] The DMA module transmits the digital signal into the main memory.
[0049] The CPU schedules the digital signal from the main memory into the extended convolution matrix module in the CPU through the bus protocol, arranges the collected floating-point data into a matrix data stream and then transmits the matrix data stream to the coprocessor module through the system bus; the CPU loads the existing high-pass filter coefficient and low-pass filter coefficient weight into the PE fixed-point data multiplier-accumulator unit of the systolic array operation structure through the bus control ROM.
[0050] The coprocessor module adopts the systolic array to perform wavelet decomposition, and the calculation result is transmitted to the CPU through the bus protocol.
[0051] Embodiment two:
[0052] The embodiment provides a wavelet denoising system, and the SoC architecture is as shown in Figure 1 The entire SoC is composed of an ADC, a DMA, a main memory, a coprocessor, a CPU and a ROM block.
[0053] The data flow process is as follows: after the ADC converts a one-dimensional analog signal into a one-dimensional digital signal, the DMA rapidly transmits the one-dimensional digital signal into the main memory, the CPU schedules the one-dimensional digital signal from the main memory into the extended convolution matrix module in the CPU through the bus protocol, arranges the collected floating-point data into a matrix data stream and then transmits the matrix data stream to the coprocessor through the system bus, and the specific process of the internal data of the coprocessor is as shown in Figure 2 .
[0054] The internal fixed-point unit of the coprocessor first converts the floating-point data into fixed-point data, and the data is transmitted into the systolic array operation structure. The CPU loads the existing high-pass filter coefficient and low-pass filter coefficient weight into the PE fixed-point data multiplier-accumulator unit of the systolic array operation structure through the bus control ROM, and the systolic array performs the convolution process of wavelet decomposition. In the entire "systolic" process, the input data is horizontally propagated from left to right, and the wavelet filter coefficient and the output data are vertically propagated from top to bottom.
[0055] According to the number of wavelet transform N, after one round of wavelet decomposition, the data will be separated by the data selection module into the detail component cA1 and the approximation component cD1, and the approximation component cD1 will be reloaded into the pulse array operation structure for the second round of decomposition, and after N rounds, the data will be obtained. After the data is processed by the coprocessor internal soft threshold filtering module, it is transmitted to the CPU through the bus protocol.
[0056] 1. Extended convolution matrix module
[0057] The one-dimensional data is expanded into a matrix, and the convolution calculation is changed into a matrix calculation, and the subsequent pulse array structure can effectively accelerate the matrix operation. For example, a 3x3 convolution matrix is convolved with a 2x2 convolution kernel to perform a convolution operation
[0058]
[0059] The extended convolution matrix module in the CPU can convert the convolution matrix into a 4x4 matrix and perform matrix multiplication with the converted convolution kernel [W 11 W 12 W 21 W 22 ], so that the convolution part is completed through matrix multiplication. The module only processes floating-point data transferred from the main memory, and as previously shown, 9 data can be selected for matrix conversion or more, depending on the number of PE units of the designed systolic array structure, while the fixed wavelet convolution kernel matrix is stored in the ROM module for loading.
[0060] 2. Fixed-point unit
[0061] The speed of the floating-point data addition and multiplication process can be further improved through data fixed-pointing. The rule of floating-point quantization is to convert the floating-point number into an integer, which loses some precision while participating in faster multiplication and addition operations in the form of an integer. After the calculation is completed, the dequantization step is performed to restore the fixed-point number to a floating-point number. The fixed-point unit in the coprocessor can convert the floating-point data of the ADC sampling result into fixed-point data. The advantage of fixed-pointing is that while losing a little precision, it avoids the relatively complex floating-point multiplication and addition of FPGA, and performs integer multiplication and addition, improving the convolution process of wavelet decomposition. The entire data flow process is as shown in Figure 3 .
[0062] For the convenience of explanation, the floating-point data is in IEEE754 format. Since the exponent will affect the accuracy of the fixed-point data, and the multiplication unit in the fixed-point unit is fixed (i.e., the decimal point position of the fixed-point data is fixed), in order to ensure the convolution speed of the systolic array and comprehensively consider the accuracy of the fixed-point data, a constant k is set, and the format of the floating-point to fixed-point conversion is set as follows: 1 bit is a sign bit, 31-k bits store an integer, and k bits store a decimal. Figure 4 As shown in FIG. 1, when the one-dimensional digital signal enters the fixed-point unit, the floating-point data M(n) enters the multiplier, at which time float x 2 k = fix, the integer part is right-shifted by k bits, and the last k bits store the decimal part. It should be noted that since k is a constant, only the last k bits of the integer part can ensure the accuracy of the original floating-point data (because the number of bits of the decimal part of the floating-point data may exceed k). The intermediate quantity M right-shifted by k bits enters the rounding unit, the decimal part is removed, the floating-point data M(n) is converted into fixed-point data M'(n), and enters the RAM.
[0063] 3. Systolic array computing structure
[0064] According to the parallel computing characteristics of the FPGA, the multiplication process of the matrix is accelerated, and the Mallat algorithm is accelerated for the fixed-point data by using a systolic array structure. The systolic array structure can make the data flow in the array of the PE operation unit, thereby reducing the number of memory accesses and improving the calculation frequency. The quantized data M'(n) enters the PE operation unit through the RAM module, and the CPU controls the ROM to fill the high-pass filter coefficients and the low-pass filter coefficients. The ROM stores the filter coefficients L(n) that have been quantized. The entire data flow process is shown in FIG. 2. Figure 5
[0065] In the first round of wavelet decomposition, the data stream of the convolution matrix propagates from left to right, and the data stream matrix of the high-pass filter coefficients and the low-pass filter coefficients propagates from top to bottom. According to the matrix parallel computing characteristics of the systolic array structure, each input data and weight data are input at the first time, and one more data is input at each time. The flow of the matrix can be controlled by assigning 0 to the empty position, and the multiplication and accumulation of the data are performed through the PE unit. Finally, according to the set weight matrix, the approximation component cD is in the upper layer of the operation result, and the detail component cA is in the lower layer. Each operation result is the accumulation of the square sum of the quantized data.
[0066] In order to restore the convolution result, the data enters the inverse quantization module, and the result is right shifted by 2k bits. Since the convolution process produces redundancy of calculation items, a downsampling module is needed to extract even rows of the approximate component cD1 and the detail component cA1 for resampling and recombination. After the downsampling process, the approximate component cD of the upper layer is input into the RAM through the DMA for the second round of wavelet decomposition in the systolic array, and the detail component cA1 is stored in the RAM. If three rounds are performed, the scale coefficients cA1, cA2, cA3, cD3 obtained after the third round are input into the CPU through the system bus for soft threshold filtering.
[0067] 4. Soft threshold filtering module
[0068] Suppose a signal can be expressed in the form of m(i) = f(i) + n(i). Where f(i) is the clean signal, n(i) is the Gaussian white noise, and follows the normal distribution. m(i) is the signal collected after superposition. Generally, the noise is variable and irregular, and after wavelet transform, it is distributed in small wavelet coefficients, while the clean signal is regular, and after wavelet transform, it is concentrated in large wavelet coefficients. It can be considered that the wavelet coefficients with large amplitude are mainly signals, and the wavelet coefficients with small amplitude are likely to be noise. Therefore, the threshold method can be used to retain the signal coefficients and set most of the noise coefficients to 0. In order to ensure the filtering effect, the soft threshold filtering method is selected to denoise the signal. In the usual threshold processing, the wavelet threshold denoising is often performed on the detail component cA. A soft threshold function is selected The function is used to set the wavelet coefficients with absolute values less than the threshold to 0, and the wavelet coefficients with large absolute values are retained or shrunk (the function of the threshold function). For the scale coefficients filtered by the soft threshold, only signal reconstruction is needed to restore the filtered signal.
[0069] In this embodiment, the similarity of matrix expansion is utilized, and the expansion convolution matrix module and the threshold denoising module are designed in the FPGA. The matrix expansion is performed by the FPGA, so as to reduce the operation burden of the CPU and improve the operation speed. Only the clock instruction of the CPU is adjusted to complete the expansion of the convolution matrix and the denoising of the signal. Different from the previous convolution operation structure, the data circulation mode with the fixed-point unit, the inverse quantization module and the DMA as the main structure is designed before and after the systolic array calculation structure according to the data flow characteristics. The parallel computing characteristics of the FPGA are utilized to shorten the important path of the system and improve the overall operation performance of the system.
[0070] Some steps in the embodiment of the application can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.
[0071] The above merely describes preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A wavelet denoising system, characterized in that, The system includes: an ADC module, a DMA module, a main memory module, a coprocessor module, a CPU, and a ROM; The ADC module converts the input analog signal into a digital signal; The DMA module transmits the digital signal into the main memory; The CPU schedules the digital signal from the main memory to the extended convolution matrix module in the CPU via a bus protocol. After arranging the acquired floating-point data into a matrix data stream, it transmits it to the coprocessor module via the system bus. The CPU controls the ROM via the bus to load the existing high-pass filter coefficients and low-pass filter coefficient weights into the PE fixed-point data multiplier-accumulator unit of the systolic array arithmetic structure. The coprocessor module uses a pulsating array for wavelet decomposition, and the calculation results are transmitted to the CPU via a bus protocol. The coprocessor module includes: a fixed-point unit and a pulsation array; The fixed-point conversion unit converts floating-point data into fixed-point data, and the data is transmitted into the pulsation array. During the calculation of the pulsating array, the input data propagates horizontally from left to right, while the wavelet filter coefficients and output data propagate vertically from top to bottom. According to the set number of wavelet transform rounds N, after one round of wavelet decomposition, the data will be separated into detail component cA1 and approximate component cD1 by the data selection module. The approximate component cD1 is then reloaded into the pulsating array operation structure for a second round of decomposition. After a total of N rounds, the result data is obtained.
2. The wavelet denoising system according to claim 1, characterized in that, The wavelet denoising system further includes: a downsampling module; The downsampling module extracts even-numbered rows from both the approximate and detail components and recombines them by sampling at intervals. After the downsampling process is completed, the upper-layer approximate components are input into the RAM through the DMA module and enter the pulsating array for the second round of wavelet decomposition, while the detail components are stored in the RAM.
3. The wavelet denoising system according to claim 2, characterized in that, The wavelet denoising system further includes a soft thresholding module, which filters the signal output by the downsampling module. The soft thresholding function is: The soft thresholding function sets wavelet coefficients with absolute values less than the threshold λ to 0 for the detail component cA, while retaining or shrinking coefficients with larger absolute values.
4. A wavelet denoising method, characterized in that, The wavelet denoising method is implemented based on the wavelet denoising system according to any one of claims 1-3, and includes: Step 1: The ADC module converts the input analog signal into a digital signal; Step 2: The DMA module transmits the digital signal into the main memory; Step 3: The CPU schedules the digital signal from the main memory to the extended convolution matrix module in the CPU via the bus protocol, arranges the collected floating-point data into a matrix data stream, and then transmits it to the coprocessor module through the system bus; Step 4: The CPU controls the ROM via the bus to load the existing high-pass filter coefficients and low-pass filter coefficient weights into the PE fixed-point data multiplier-accumulator unit of the systolic array arithmetic structure; Step 5: The pulsating array performs wavelet decomposition calculation on the input data. The input data propagates horizontally from left to right, while the wavelet filter coefficients and output data propagate vertically from top to bottom. Step 6: According to the set number of wavelet transform rounds N, after one round of wavelet decomposition, the data will be separated into detail component cA1 and approximate component cD1 by the data selection module. The approximate component cD1 will be reloaded into the pulsating array operation structure for a second round of decomposition. After a total of N rounds, the result data is obtained.
5. The wavelet denoising method according to claim 4, characterized in that, The extended convolution matrix module expands one-dimensional data into a matrix.
6. A wavelet denoising device, characterized in that, The device includes: A signal acquisition device, used to acquire signals to be processed; The wavelet denoising system according to any one of claims 1-3 is used to perform wavelet denoising on the acquired signal; A data output device used to output the denoised signal data.
7. The wavelet denoising device according to claim 6, characterized in that, The signal acquisition device includes: a sensor.
8. The wavelet denoising device according to claim 6, characterized in that, The data output device includes: a computer.
Citation Information
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