Data processing apparatus, data processing method and related devices

Abstract

The application provides a data processing device, a data processing method and related devices, comprising a neural network processor, a tail address space of any one annular cache space of a circular cache space is used to store data of a first N-1 row of the tail address space of the next annular cache space, and a head address space of any one annular cache space of the circular cache space is used to store data of N-1 rows of the tail address space of the previous annular cache space. The frequency of accessing memory when reading data can be reduced, the bus bandwidth occupation and system power consumption can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of neural network processors, and in particular to a data processing apparatus, a data processing method and related apparatuses. BACKGROUND

[0002] With the development of existing technologies, in order to enhance the artificial intelligence capability of a device, a neural network processing unit (NPU) is generally integrated in a system, a "data-driven parallel computing" architecture is generally adopted, and the NPU is used to accelerate the operation of a neural network and solve the problem of low efficiency of a traditional chip in neural network operation. How to reduce the power consumption of the NPU has become a difficult problem. SUMMARY

[0003] Therefore, the present application provides a data communication method and related apparatuses, which can reduce the frequency of accessing memory when reading data, reduce the bus bandwidth occupation and system power consumption through a specific storage space architecture.

[0004] In a first aspect, an embodiment of the present application provides a data processing apparatus, comprising a neural network processing unit, wherein the neural network processing unit comprises a processing unit array and M storage modules, the processing unit array comprises M sets of processing units in columns, M is an even positive integer, the neural network processing unit is applicable to a convolution kernel of NxN, N is a positive integer greater than 1 and less than x;

[0005] Each storage module comprises a ring buffer space corresponding to each layer of a neural network, M ring buffer spaces of each layer form at most M / 2 circular buffer spaces, and each circular buffer space comprises at least 2 and at most M ring buffer spaces.

[0006] Each ring buffer space comprises x rows of buffer address spaces, x is a positive integer greater than 2, the x rows of buffer address spaces comprise N-1 rows of head address spaces and N-1 rows of tail address spaces, the N-1 rows of tail copy spaces after the tail address space of any one ring buffer space forming the circular buffer space are used to store the data of the N-1 rows of head address spaces of the next ring buffer space, and the N-1 rows of head copy spaces before the head address space of any one ring buffer space forming the circular buffer space are used to store the data of the N-1 rows of tail address spaces of the previous ring buffer space.

[0007] The M storage modules are used to distribute the to-be-stored data, and the M sets of processing units in columns are used to read the distributed to-be-stored data from the M storage modules.

[0008] In a second aspect, the embodiments of the present application provide a data processing method, applied to the data processing apparatus in the first aspect of the embodiments of the present application, and the method comprises the following steps:

[0009] obtaining to-be-stored data;

[0010] dividing the to-be-stored data into n to-be-stored sub-data according to a channel number n of the to-be-stored data, n being a positive integer less than or equal to M / 2;

[0011] writing each to-be-stored sub-data into a circular cache space composed of INT(M / n) ring cache space groups, and any one of the circular cache space groups being used to store any one of the to-be-stored sub-data.

[0012] In a third aspect, the embodiments of the present application provide an electronic device, comprising a memory and a processor, the memory is configured to store a program, and the processor executes the program stored in the memory, and when the program stored in the memory is executed, the processor is configured to execute the instructions of the steps in the method according to any one of the second aspect of the embodiments of the present application.

[0013] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, which stores a computer program, the computer program comprises program instructions, and the program instructions, when executed by a processor, cause the processor to execute the method according to any one of the second aspect of the embodiments of the present application.

[0014] In a fifth aspect, the embodiments of the present application provide a computer product, wherein the computer program product includes a non-transitory computer readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform some or all of the steps described in any method of the second aspect of the embodiments of the present application. The computer program product can be a software installation package.

[0015] It can be seen that, by the data processing device, the data processing method and the related device, the neural network processor includes a processing unit array and M storage modules, the processing unit array includes M column processing unit sets, M is an even positive number, the neural network processor is suitable for an NxN convolution kernel, N is a positive integer greater than 1 and less than x; each storage module includes a ring buffer space corresponding to the number of neural network layers, M ring buffer spaces of each layer form at most M / 2 circular buffer spaces, and each circular buffer space includes at least 2 and at most M ring buffer spaces; each ring buffer space includes x rows of cache address spaces, x is a positive integer greater than 2, the x rows of cache address spaces include the first N-1 rows of header address spaces and the last N-1 rows of tail address spaces; the N-1 rows of tail copy spaces after the tail address space of any one ring buffer space forming the circular buffer space are used to store the data of the first N-1 rows of header address spaces of the next ring buffer space, and the N-1 rows of header copy spaces before the header address space of any one ring buffer space forming the circular buffer space are used to store the data of the N-1 rows of tail address spaces of the previous ring buffer space; the M storage modules are used to distribute the first data, and the M column processing unit sets are used to read the distributed first data from the M storage modules. The frequency of accessing memory when reading data can be reduced, the bus bandwidth occupation amount and system power consumption can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0017] Figure 1 An architecture schematic diagram of a data processing device provided by the embodiments of the present application;

[0018] Figure 2 A structure schematic diagram of a storage module provided by the embodiments of the present application;

[0019] Figure 3 A structure schematic diagram of a ring buffer space provided by the embodiments of the present application;

[0020] Figure 4 An example structure diagram of a circular buffer space provided by the embodiments of the present application;

[0021] Figure 5 A flow schematic diagram of a data processing method provided by the embodiments of the present application;

[0022] Figure 6 An architecture schematic diagram of a neural network processor provided by an embodiment of the present application is shown in FIG. 1.

[0023] Figure 7 A bandwidth proportion comparison schematic diagram provided by an embodiment of the present application is shown in FIG. 2.

[0024] Figure 8 A structure schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0025] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor are within the scope of protection of the present application.

[0026] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, not to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0027] It should be understood that the term "and / or" herein is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this paper represents that the front and rear associated objects are a "or" relationship. "Multiple" appears in the embodiments of the present application means two or more.

[0028] The "connection" appearing in the embodiments of the present application means direct connection or indirect connection and various connection modes to realize communication between devices, which is not limited by the embodiments of the present application.

[0029] Reference to "an embodiment" in this text means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. The person skilled in the art explicitly and implicitly understands that the embodiments described herein can be combined with other embodiments.

[0030] The background and related terms of the present application are described below.

[0031] Background related:

[0032] In the design of NPU architecture, multiple levels of cache are usually designed to improve the data bandwidth of the system. The basic computing unit in the NPU is usually an arithmetic and logic unit (ALU) with storage, also known as a processing element (PE). The storage in the PE is called level 0 cache. And the data processed by the neural network is usually data divided into multiple channels, such as image data including multiple color channels, etc. In the NPU systolic array architecture for convolutional neural networks, a common architecture is to split the buffer into independent small buffers corresponding to different channels composed of static random access memory (SRAM) to increase the bandwidth, and each SRAM corresponds to a column of PEs. When a column of PEs in the PE array needs to access data not in the SRAM corresponding to it, the existing method is to increase an extra bus in the buffer of different SRAMs to support data access between different SRAMs, which increases the area and power consumption of the chip. Another method is to combine multiple SRAMs into one large SRAM, but since different SRAMs have overlapping data, the overlapping data needs to be accessed multiple times from the dynamic random access memory (DRAM), and each time reading from the DRAM has a power consumption about 100 times higher than accessing the SRAM, greatly increasing the bus bandwidth and system power consumption.

[0033] To solve the above problems, the present application provides a data processing device, a data processing method and related devices, which can reduce the frequency of accessing memory when reading data, reduce the bus bandwidth occupancy and system power consumption through a specific storage space architecture.

[0034] The following will be described in combination with Figure 1 A data processing device in an embodiment of the present application is described, Figure 1 The architecture schematic diagram of a data processing device provided in the embodiment of the present application, the data processing device 100 includes a processing unit array 110 and M storage modules 120, the processing unit array 110 includes M columns of processing unit sets 111, M is an even positive number, and is suitable for an NxN convolution kernel, N is a positive integer greater than 1 and less than x.

[0035] Each storage module 120 includes a ring buffer space corresponding to each layer of the neural network, and M ring buffer spaces of each layer form at most M / 2 circular buffer spaces, and each circular buffer space includes at least 2 and at most M ring buffer spaces.

[0036] Each ring buffer space includes x row buffer address spaces, x is a positive integer greater than 2, and the x row buffer address spaces include N-1 front header address spaces and N-1 rear tail address spaces; the N-1 rear tail copy space after the tail address space of any one ring buffer space forming the circular buffer space is used to store the data of the N-1 front header address space of the next ring buffer space, and the N-1 front header copy space before the header address space of any one ring buffer space forming the circular buffer space is used to store the data of the N-1 rear tail address space of the previous ring buffer space.

[0037] The M storage modules 120 are used to distribute the to-be-stored data, and the M column processing unit sets are used to read the distributed to-be-stored data from the M storage modules.

[0038] In the above, the storage module 120 can be an SRAM, and the column processing unit set 111 can include a plurality of PEs.

[0039] For ease of understanding, the following will be described in combination with Figure 2 Any one of the storage modules 120 in the embodiments of the present application is described separately, Figure 2 A structure diagram of a storage module provided in the embodiments of the present application includes a ring buffer space (Ring buffer) α, that is, ring buffer space 0~ring buffer space α-1 in the figure, and different ring buffer spaces correspond to different layers in the neural network.

[0040] In a possible embodiment, when opening the ring buffer space of each storage module 120, the space can be opened in units of spaces occupied by image even row pixel points to ensure that the buffer addresses of different storage modules 120 in the same layer of the neural network are aligned.

[0041] Further, the following will be described in combination with Figure 3 The ring storage space in the embodiments of the present application is described, Figure 3 A structure diagram of a ring buffer space provided in the embodiments of the present application includes x row buffer address spaces, that is, row 0~row x-1 in the figure, when the convolution kernel is NxN, N-1 can be set as the header address space, and N-1 can be set as the tail address space. The first N-1 rows of the header address space can be set as the header copy space, and the last N-1 rows of the tail address space can be set as the tail copy space.

[0042] Further, in combination with Figure 4 The circular cache space in the embodiment of the present application is described, Figure 4 An example structure diagram of the circular cache space provided by the embodiment of the present application can be seen that when two ring cache spaces constitute the circular cache space, each ring cache space is set to include 8 rows of cache address spaces, that is, row 0 to row 7 in the first ring cache space and row 8 to row 15 in the second ring cache space (the middle rows are not shown), and the convolution kernel size is set to 3x3. Then it can be determined that the first 2 rows and the last 2 rows in the first ring cache space are copied to the first 2 rows of the head copy space before row 8 in the second ring cache space, and the data in row 8 and row 9 is copied to the last 2 rows of the tail copy space after row 7. Similarly, the data in row 14 and row 15 is copied to the first 2 rows of the head copy space before row 0, and the data in row 0 and row 1 is copied to the last 2 rows of the tail copy space after row 15, thereby forming a circular cache space. It can be understood that the copy space actually stores data, and when data in the head address space or the tail address space is needed, it can be obtained from the head copy space or the tail copy space. For example, when the data in row 7, row 8 and row 9 is needed, the data in row 7 is read from the first ring cache space, and the data in row 8 and row 9 is read from the tail copy space of the first ring cache space. Details are not described here.

[0043] Through the above data processing device, distributed storage of data can be performed, and distributed stored data can be read, thereby reducing the frequency of accessing memory when reading data, reducing bus bandwidth occupation and system power consumption.

[0044] The following describes the data processing method in the embodiment of the present application, Figure 5 The data processing method in the embodiment of the present application is described, and the data processing method is applied to the above data processing device, Figure 5 A flowchart of the data processing method provided by the embodiment of the present application is shown, which specifically includes the following steps:

[0045] Step 501, obtaining to-be-stored data.

[0046] Step 502, dividing the to-be-stored data into n to-be-stored sub-data according to the channel number n of the to-be-stored data.

[0047] The to-be-stored data can be image data with n channels. In order to ensure that the data of each channel is evenly distributed and stored in M storage modules, it is necessary to satisfy n less than or equal to M / 2.

[0048] The to-be-stored data can be obtained from a dynamic random access memory (DRAM) and written into the M storage modules.

[0049] Step 503, write each to-be-stored sub-data into a circular cache space composed of INT(M / n) ring cache spaces.

[0050] Any one of the circular cache spaces is used to store any one of the to-be-stored sub-data.

[0051] Wherein, the number of rows y of each first sub-data can be obtained, and then each first sub-data is sequentially written into a circular cache space composed of INT(M / n) ring cache spaces, and written for y / (INT(M / n)*x) rounds to store the first data.

[0052] It can be understood that when n is 2 and M is 4, there are 2 first sub-data, 2 circular cache spaces can be constructed to store 2 first sub-data, that is, each first sub-data is written into a circular cache space composed of INT(4 / 2)=2 ring cache spaces; when n is 2 and M is 9, there are 2 first sub-data, 2 circular cache spaces can be constructed to store 2 first sub-data, that is, each first sub-data is written into a circular cache space composed of INT(9 / 2)=4 ring cache spaces, which can maximize the distributed storage.

[0053] Specifically, when each first sub-data is written into each row of cache address space, the following steps can be performed:

[0054] S1, judging whether the first cache address space where the to-be-stored data is stored exists a corresponding first tail copy space or a corresponding first head copy space.

[0055] The first cache address space can be any row of cache address space that each first sub-data needs to be written into. Since N-1 head address spaces exist corresponding N-1 tail copy spaces, and N-1 tail address spaces exist corresponding N-1 head copy spaces, whether the first cache address space exists a corresponding first tail copy space or a corresponding first head copy space can be determined according to the number of rows. Details are not described herein.

[0056] S2, when the first cache address space where the to-be-stored data is stored exists a corresponding first tail copy space or a corresponding first head copy space, the to-be-stored data is written into the first cache address space, the first tail copy space or the first head copy space at the same time.

[0057] When the first cache address space has a corresponding first header copy space, the to-be-cached data can be written into the first cache address space and the first header copy space simultaneously; when the first cache space has a corresponding first tail copy space, the to-be-cached data can be written into the first cache address space and the first tail copy space simultaneously.

[0058] S3, when the first cache address space of the to-be-stored data storage does not have a corresponding first tail copy space or a corresponding first header copy space, the to-be-stored data is written into the first cache address space.

[0059] When the first cache address space is not a header address space or a tail address space, the to-be-stored data is written into the first cache space.

[0060] Step 504, reading the to-be-cached sub-data in each circular cache space.

[0061] The first to-be-stored sub-data can be read from the tail copy space corresponding to the header address space when the to-be-stored sub-data of any one header address space needs to be read.

[0062] In one possible embodiment, when the to-be-stored sub-data of any one header address space needs to be read, the first to-be-stored sub-data is read from the tail copy space corresponding to the header address space.

[0063] In one possible embodiment, when the to-be-stored sub-data of any one tail address space needs to be read, the first to-be-stored sub-data is read from the header copy space corresponding to the tail address space.

[0064] In one possible embodiment, when the to-be-stored sub-data of any one header address space or any one tail address space does not need to be read, each row of to-be-cached sub-data is read in sequence.

[0065] As can be seen, through the above data processing method, the to-be-cached data can be obtained from the external storage module, and the to-be-stored data can be written into the SRAM and the copy space according to the copy space, so that the external storage module does not need to be accessed again when reading, reducing the bus bandwidth occupation and system power consumption. And improve the size of data storage, for example, when the number of channels is 2 and the number of SRAMs is 8, four SRAMs can be used for one channel, and the size of the image that can be stored is 4 times that of the average storage. This will not be repeated here.

[0066] For ease of understanding, the data processing apparatus and data processing method in the present application are exemplarily illustrated below in combination with examples. For example, it is assumed that there are four storage modules, SRAM0, SRAM1, SRAM2 and SRAM3, and the first data to be stored is 2-channel image data. The existing method generally stores the data of one channel in SRAM0 and the data of the other channel in SRAM1, and SRAM2 and SRAM3 are in idle state, which is a waste of resources.

[0067] According to the present application, the head-to-tail address spaces of SRAM0 and SRAM2 are copied to each other, and the head-to-tail address spaces of SRAM1 and SRAM3 are copied to each other. When the data of DRAM is acquired, the data of the overlapping part of SRAM0 and SRAM2 can be written into the copy space of SRAM0 and the copy space of SRAM2 at the same time, and the data of the overlapping part of SRAM1 and SRAM3 can be written into the copy space of SRAM1 and the copy space of SRAM3 at the same time. Therefore, when the processing unit set corresponding to SRAM0 or SRAM2 needs to read the data of the overlapping part, it is not necessary to access DRAM again, but only needs to acquire the data from the copy space. It can be seen that, through the architecture of the present application, distributed storage can be performed, that is, the data of one channel is stored in SRAM0 and SRAM2, and the data of the other channel is stored in SRAM1 and SRAM3. At the same time, distributed reading can be performed, as shown in the following table, and the details are not described herein again. It can be seen that the frequency of accessing memory when reading data can be reduced, and the bus bandwidth occupation and system power consumption can be reduced. Figure 6

[0068] It can be understood that the above is an exemplary illustration. The data of one channel can be divided into several storage modules, for example, the data of one channel can be stored in SRAM0 and SRAM4, or SRAM1 and SRAM2, and the like, which is not specifically limited herein.

[0069] The application example can be applied to the following scenarios:

[0070] n x 2 ≤ M

[0071] n is the number of channels of data to be stored, and M is the number of storage modules.

[0072] ​For example, the data to be stored is an image with 2 channels and 2000 rows. The existing method stores channel 1 in the circular storage space 1 of the allocated storage module 1. Circular storage space 1 can store 20 rows of data, and the corresponding circular storage space 2 of the other storage module 2 can also store 20 rows of data. Therefore, 40 rows of data can be retrieved at a time. According to previous analysis, with a 3x3 convolution kernel, retrieving 40 rows of data results in 8 rows of overlapping data. It would take 50 rounds to retrieve all the image data. These 50 rounds require additional retrieval of 400 rows of overlapping data, which represents 400 / 2000 = 0.2 of the total image rows. This means 20% of the data is overlapping and requires repeated DRAM access and data transfer. If the copy space strategy proposed in this technology is adopted, the bus bandwidth and system power consumption occupied by this 20% data transfer can be saved.

[0073] like Figure 7 As shown, Figure 7 This is a schematic diagram of bandwidth ratio comparison provided by an embodiment of this application. The shaded area represents the bus bandwidth usage when reading the overlapping area. It can be seen that in the existing solution, the bus bandwidth usage increases in a short period of time because the overlapping area needs to be read repeatedly. However, this solution does not need to repeatedly access DRAM, so the bus bandwidth ratio is relatively low.

[0074] The following is combined Figure 8 An electronic device according to an embodiment of this application will be described. Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 8 As shown, the electronic device 800 includes a processor 801, a communication interface 802, and a memory 803, which are interconnected. The electronic device 800 may also include a bus 804, through which the processor 801, communication interface 802, and memory 803 are interconnected. The bus 804 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 804 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 8 The bus is represented by a single thick line, but this does not indicate that there is only one bus or one type of bus. The memory 803 stores a computer program, which includes program instructions. The processor is configured to call the program instructions and execute the above-mentioned... Figure 5 All or part of the methods described herein.

[0075] The above describes the scheme of the embodiments of the present application mainly from the perspective of the process of executing the method. It can be understood that, in order to implement the above functions, the electronic device comprises a hardware structure and / or a software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the unit and algorithm steps of each example described in the embodiments provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is implemented in the form of hardware or computer software driven hardware depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0076] The embodiments of the present application can divide the functional units of the electronic device according to the above method examples. For example, each functional unit can be divided according to each function, or two or more functions can be integrated in one processing unit. The integrated unit can be implemented in the form of hardware or software functional unit. It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, there can be another division method.

[0077] The embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program causes the computer to execute part or all of the steps of any method described in the above method embodiments.

[0078] The embodiments of the present application also provide a computer program product, which includes a non-transitory computer readable storage medium storing a computer program. The computer program is operable to cause a computer to execute part or all of the steps of any method described in the above method embodiments. The computer program product can be a software installation package, and the computer includes an electronic device.

[0079] It should be noted that, for the foregoing method embodiments, in order to simply describe, they are all described as a combination of a series of actions, but those skilled in the art should know that the present application is not limited to the order of the actions described, because according to the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0080] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0081] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments described above is merely illustrative, and the division of the units can be changed according to actual needs. For example, the units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0082] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0083] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0084] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable memory. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a memory and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned memory includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0085] Those of ordinary skill in the art can understand that all or part of the steps of the various methods in the above embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer readable memory, which can include a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0086] The above has carried out the detailed introduction to the embodiment of the application, the principle and implementation mode of the application have been described in this article by applying specific examples, the above embodiment explanation is only for helping understanding the method of the application and its core idea; at the same time, for the general technical personnel in the art, according to the idea of the application, the specific implementation mode and application range will have the change, and the above-mentioned, the content of the specification should not be understood as the limitation of the application.

Claims

1. A data processing apparatus, characterized in that, The system includes a neural network processor, which comprises a processing unit array and M storage modules. The processing unit array comprises M columns of processing unit sets, where M is a positive even number. The neural network processor is suitable for NxN convolution kernels, where N is a positive integer greater than 1 and less than x. Each storage module includes a circular cache space that corresponds one-to-one with the number of neural network layers. The M circular cache spaces of each layer form at most M / 2 circular cache spaces, and each circular cache space includes at least 2 and at most M circular cache spaces. Each circular cache space includes x lines of cache address space, where x is a positive integer greater than 2. The x lines of cache address space include the first N-1 lines of header address space and the last N-1 lines of tail address space. The N-1 lines of tail copy space after the tail address space of any circular cache space that makes up the circular cache space are used to store the data of the first N-1 lines of header address space of the next circular cache space that is copied. The N-1 lines of header copy space before the header address space of any circular cache space that makes up the circular cache space are used to store the data of the N-1 lines of tail address space of the previous circular cache space that is copied. The M storage modules are used for distributed storage of data to be stored, and the M-column processing unit set is used to read the distributed storage of the data to be stored from the M storage modules.

2. A data processing method, characterized in that, Applied to the data processing apparatus of claim 1, the method comprises: Retrieve the data to be stored; The data to be stored is divided into n sub-data to be stored based on the number of channels n, where n is a positive integer less than or equal to M / 2; Each piece of data to be stored is written into a circular cache space consisting of INT(M / n) circular cache spaces, and any one circular cache space is used to store any piece of data to be stored.

3. The method according to claim 2, characterized in that, The step of writing each sub-data to be stored into a circular cache space composed of INT(M / n) circular cache spaces includes: Obtain the row number y of each sub-data to be stored; Each piece of sub-data to be stored is sequentially written into the circular cache space composed of INT(M / n) circular cache spaces, and written as y / (INT(M / n)). x) rounds are used to store the data to be stored.

4. The method according to claim 2, characterized in that, The step of writing each sub-data to be stored into a circular cache space composed of INT(M / n) circular cache spaces includes: Determine whether the first cache address space of the data to be stored exists to have a corresponding first tail copy space or a corresponding first head copy space; When the first cache address space containing the data to be stored contains a corresponding first tail copy space or a corresponding first head copy space, the data to be stored is simultaneously written into the first cache address space, the first tail copy space, or the first head copy space.

5. The data processing method according to claim 4, characterized in that, After determining whether the first cache address space of the data to be stored exists a corresponding first tail copy space or a corresponding first head copy space, the method further includes: When the first cache address space for the data to be stored does not contain a corresponding first tail copy space or a corresponding first head copy space, the data to be stored is written into the first cache address space.

6. The method according to any one of claims 2-5, characterized in that, After writing each sub-data to be stored into a circular cache space composed of INT(M / n) circular cache spaces, the method further includes: Read the sub-data to be stored from each of the circular cache spaces.

7. The method according to claim 6, characterized in that, The step of reading the sub-data to be stored in each of the circular cache spaces includes: Read INT(M / n) values ​​from each of the M / n circular cache spaces in sequence. x) rows y) to read each first sub-data to be stored.

8. The method according to claim 7, characterized in that, The process involves sequentially reading INT(M / n) circular cache spaces. x) Row y to read each of the first sub-data to be stored, including: When it is necessary to read any sub-data to be stored in the header address space, the first sub-data to be stored is read from the tail copy space corresponding to the header address space; When it is necessary to read any sub-data to be stored in the tail address space, the first sub-data to be stored is read from the head copy space corresponding to the tail address space; When it is not necessary to read any header address space or any tail address space, read each line of sub-data to be stored sequentially.

9. An electronic device, characterized in that, include: A memory and a processor, the memory being used to store a program, the processor executing the program stored in the memory, and when the program stored in the memory is executed, the processor being used to perform the data processing method as described in any one of claims 2 to 8.

10. A computer storage medium, characterized in that, The computer storage medium stores program code for execution by an electronic device, the program code being used to implement the method as described in any one of claims 2 to 8.

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