Data processing method and device, computer device, and storage medium

Abstract

The application discloses a data processing method and device, computer equipment and a storage medium, and belongs to the technical field of computers. The method comprises the following steps: processing input data of a neural network based on a first operator by a first processing unit to obtain a processing result, the first processing unit being matched with the first operator in multiple operators; sending the processing result to a second processing unit based on a direct connection path between the first processing unit and the second processing unit, the second processing unit being matched with a second operator of the neural network; and processing the processing result based on the second operator by the second processing unit. The method adds a direct connection path between processing units, so that the processing units can directly exchange data through the direct connection path, and are free from a control unit. Therefore, the processing units can directly and unobstructedly cooperate, and the efficiency of data processing through operators in the neural network is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, computer equipment, and storage medium. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence technology, neural network-based data processing methods have been widely applied. Since different operators in a neural network are adapted to different processing units, different processing units are needed to execute the corresponding operators and work together to complete the data processing task. In related technologies, the various processing units interact with each other through control units to complete the data processing task. However, the efficiency of interaction between different processing units is extremely low, resulting in low data processing efficiency. Summary of the Invention

[0003] This application provides a data processing method, apparatus, computer equipment, and storage medium, which can improve data processing efficiency. The technical solution is as follows:

[0004] According to one aspect of the embodiments of this application, a data processing method is provided, the method comprising:

[0005] The first processing unit processes the input data based on the first operator of the neural network to obtain the processing result, and the first processing unit is matched with the first operator.

[0006] Based on the direct connection between the first processing unit and the second processing unit, the processing result is sent to the second processing unit, and the second processing unit is matched with the second operator of the neural network;

[0007] The processing unit processes the processing result based on the second operator.

[0008] According to another aspect of the embodiments of this application, a data processing apparatus is provided, the apparatus comprising:

[0009] The first processing module is used to process the input data through the first processing unit based on the first operator of the neural network to obtain the processing result, wherein the first processing unit is matched with the first operator;

[0010] The data sending module is used to send the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit, wherein the second processing unit is matched with the second operator of the neural network;

[0011] The second processing module is used to process the processing result based on the second operator through the second processing unit.

[0012] According to another aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory; the memory stores at least one piece of program code, the at least one piece of program code being executed by the processor to implement the data processing method as described above.

[0013] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, the storage medium storing at least one piece of program code, the at least one piece of program code being executed by a processor to implement the data processing method as described above.

[0014] According to another aspect of the embodiments of this application, a computer program product is provided, which stores at least one piece of program code, said at least one piece of program code being loaded and executed by a processor to implement the data processing method described above.

[0015] According to another aspect of the embodiments of this application, a chip is provided, the chip including programmable logic circuits and / or program instructions, which, when the chip is run on a terminal, is used to implement the data processing method described above.

[0016] The data processing scheme provided in this application adds a direct connection between processing units, enabling them to interact directly through this direct connection. This greatly improves the interaction efficiency between processing units. In this case, after processing a unit performs data processing based on a matching operator, it directly sends the processing result to another processing unit. The other processing unit can then directly obtain the processing result and continue processing it. This scheme eliminates the need for a control unit, allowing processing units to cooperate directly and without obstacles, thereby improving the efficiency of data processing through operators in the neural network. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of an implementation environment provided by an exemplary embodiment of this application is shown;

[0019] Figure 2 A flowchart illustrating a data processing method provided in an exemplary embodiment of this application is shown;

[0020] Figure 3 A flowchart illustrating another data processing method provided by an exemplary embodiment of this application is shown;

[0021] Figure 4 This illustration shows a schematic diagram of a connection method between processing units provided in an exemplary embodiment of this application;

[0022] Figure 5 This invention provides a schematic diagram of the structure of a processing unit according to an exemplary embodiment of the present application.

[0023] Figure 6 A schematic diagram of a data processing procedure provided by an exemplary embodiment of this application is shown;

[0024] Figure 7 A flowchart illustrating another data processing procedure provided by an exemplary embodiment of this application is shown;

[0025] Figure 8 This invention provides a structural block diagram of a data processing apparatus according to an exemplary embodiment of the present application.

[0026] Figure 9 This invention provides a structural block diagram of a terminal according to an exemplary embodiment of the present application.

[0027] Figure 10 The diagram shows a structural block diagram of a server provided in an exemplary embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0029] In this article, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0030] This application provides a data processing method, executed by a computer device 100. Optionally, the computer device 100 is a terminal, such as a mobile phone, desktop computer, laptop computer, tablet computer, smart TV, smart speaker, vehicle terminal, smart robot, or other types of terminals. Optionally, the computer device 100 is a server, which can be a single server, a server cluster composed of several servers, or a cloud computing server center. The computer device 100 processes input data based on operators in a neural network using the method provided in this application, thereby improving data processing efficiency. Optionally, the computer device is equipped with a chip, such as an artificial intelligence chip, which enables the computer device to execute the data processing method of this application embodiment.

[0031] Figure 1 This is a schematic diagram of a computer device 100 provided in an embodiment of this application. (See reference) Figure 1 The computer device 100 includes at least two processing units, such as a first processing unit 101 and a second processing unit 102. The first processing unit 101 and the second processing unit 102 are matched with different operators. Optionally, the first processing unit 101 is matched with a computationally dense and linear operator, such as a convolution operator or a pooling operator. The second processing unit 102 is matched with a non-linear operator, such as an activation function. The computer device 100 executes the operator matched with the processing unit through the processing unit to ensure the execution efficiency of the operator.

[0032] In this embodiment, since the neural network includes multiple operators, and these operators are matched with different processing units, the processing units matched with the multiple operators need to cooperate when processing the input data of the neural network. Specifically, the first processing unit 101 processes the input data based on the first operator in the neural network to obtain a processing result, and then sends the processing result to the second processing unit 102 via a direct connection between the first processing unit 101 and the second processing unit 102. Upon receiving the processing result, the second processing unit 102 continues to process the result based on the second operator in the neural network. In other words, each processing unit executes the operator in the neural network that matches it, and the resulting processing result is sent to other processing units via direct connections.

[0033] The data processing method provided in this application can be applied to image processing scenarios. For example, a computer device acquires an input image from an image processing network, processes the input image using a first image processing unit based on a first operator in the image processing network, obtains a processing result, and sends the processing result to a second image processing unit via a direct connection between the first and second image processing units. Then, the second image processing unit further processes the processing result using a second operator in the image processing network. The first image processing unit is matched with the first operator, and the second image processing unit is matched with the second operator. This method can improve the efficiency of image processing based on an image processing network.

[0034] The data processing method provided in this application can be applied to audio processing scenarios. For example, a computer device acquires input audio from an audio processing network, processes the input audio using a first audio processing unit based on a first operator in the audio processing network, obtains a processing result, and sends the processing result to a second audio processing unit via a direct connection between the first and second audio processing units. Then, the second audio processing unit further processes the processing result using a second operator in the audio processing network. The first audio processing unit is matched with the first operator, and the second audio processing unit is matched with the second operator. This method can improve the efficiency of audio processing based on an audio processing network.

[0035] The data processing method provided in this application can be applied to video processing scenarios. For example, a computer device acquires input video from a video processing network, processes the input video using a first video processing unit based on a first operator in the video processing network, obtains a processing result, and sends the processing result to a second video processing unit via a direct connection between the first and second video processing units. Then, the second video processing unit further processes the result based on a second operator in the video processing network. The first video processing unit is matched with the first operator, and the second video processing unit is matched with the second operator. This method can improve the efficiency of video processing based on a video processing network.

[0036] Of course, the method provided in this application embodiment can also be applied to other data processing scenarios, such as scenarios of processing multimedia data through a multimedia processing network or scenarios of processing text data through a text processing network. This application embodiment does not limit this.

[0037] Figure 2 A flowchart illustrating a data processing method provided in an exemplary embodiment of this application is shown. See also: Figure 2 The executing entity is a computer device, and the method includes:

[0038] 201. The computer device processes the input data through a first processing unit based on a first operator of a neural network to obtain a processing result. The first processing unit is matched with the first operator among the plurality of operators.

[0039] The neural network can be any type of data processing network, such as image processing networks, audio processing networks, text processing networks, multimedia processing networks, etc. The neural network includes multiple operators, optionally including convolution operators, activation operators, pooling operators, and normalization operators. By inputting data of any type into the corresponding type of data processing network, and processing the data based on the multiple operators within that network, the desired effect can be achieved. For example, if the function of an image processing network is to denoise an image, then processing the input image using the multiple operators within that image processing network can remove noise from the image.

[0040] Optionally, the first operator is the operator ranked first in the neural network. Since different operators have different computational characteristics, and different processing units have different data processing methods, different operators may be matched with different processing units. Compared to the processing unit matched with the operator, other processing units can also execute the operator, but at a slower speed. Therefore, in this embodiment, each operator in the neural network is executed by the processing unit matched with that operator to ensure the efficiency of data processing based on the neural network.

[0041] The computer device includes multiple processing units, wherein the first processing unit and the second processing unit are matched with different operators. Optionally, the first processing unit and the second processing unit can be any processing engine. For example, the first processing unit can be an NPU (Neural-network Processing Unit), and the second processing unit can be a DSP (Digital Signal Processor). Another example is that the first processing unit can be a TPU (Tensor Processing Unit), and the second processing unit can be a GPU (Graphics Processing Unit). Yet another example is that the first processing unit is an NPU, and the second processing unit is a TPU. The first processing unit and the second processing unit can be any data processing acceleration engine, and the embodiments of this application do not impose any limitations on this.

[0042] 202. The computer device sends the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit, and the second processing unit matches the second operator of the neural network.

[0043] A direct link is a pathway that directly connects two processing units without any other units between them. Optionally, each processing unit matched with multiple operators in a neural network has a direct link, allowing any two processing units to directly interact with each other based on this direct link.

[0044] 203. The computer device processes the processing result based on the second operator through the second processing unit.

[0045] The second processing unit receives the processing result sent by the first processing unit, and then continues to process the result based on the second operator. It should be noted that if the second operator is the last operator in the neural network, then the second processing unit processes the result based on the second operator to obtain the output data of the neural network. If the second operator is not the last operator in the neural network, then the second processing unit processes the result based on the second operator to obtain an updated processing result. Subsequently, the second processing unit or other processing units execute other operators in the neural network until all operators in the neural network have been executed.

[0046] The data processing scheme provided in this application adds a direct connection between processing units, enabling them to interact directly through this direct connection. This greatly improves the interaction efficiency between processing units. In this case, after processing a unit performs data processing based on a matching operator, it directly sends the processing result to another processing unit. The other processing unit can then directly obtain the processing result and continue processing it. This scheme eliminates the need for a control unit, allowing processing units to cooperate directly and without obstacles, thereby improving the efficiency of data processing through operators in the neural network.

[0047] Figure 3 A flowchart illustrating a data processing method provided in an exemplary embodiment of this application is shown. See also: Figure 3 The method includes:

[0048] 301. Computer equipment acquires input data from a neural network, which includes multiple operators.

[0049] Optionally, the computer device acquires data stored by the CPU (Central Processing Unit) at a target storage location and determines this data as the input data for the neural network. The target storage location is used to store the input data for the neural network.

[0050] 302. The computer device processes the input data through the first processing unit based on the first operator to obtain the processing result, and the first processing unit is matched with the first operator among the plurality of operators.

[0051] Optionally, after storing the input data of the neural network in the target storage location, the CPU sends a data processing instruction to the first processing unit to instruct the first processing unit to begin executing a data processing operation. Accordingly, the first processing unit responds to the data processing instruction, processes the input data based on the first operator, and obtains the processing result.

[0052] In one possible implementation, the first processing unit includes a first processor. Accordingly, the computer device processes input data based on a first operator through the first processing unit to obtain a processing result, including: the computer device executing a wait instruction through the first processor to wait for a data processing instruction; and in response to receiving a data processing instruction, processing the input data based on the first operator to obtain a processing result. The wait instruction is used to indicate that the data processing operation should be stopped until a data processing instruction is received, at which point the data processing operation will be re-executed. Optionally, the first processor in the first processing unit is an ALU (Arithmetic Logic Unit), and the first memory is called memory.

[0053] Optionally, the wait instruction is sent by the CPU to the first processing unit, or the wait instruction is read by the first processing unit from memory, which can be any memory, such as public memory or memory in the first processing unit. This application embodiment does not limit this.

[0054] In this embodiment of the application, since the wait instruction is used to indicate that the data processing operation is stopped and the data processing operation is resumed when the data processing instruction is received, the first processor executes the wait instruction, thereby realizing the timing of the first processor to execute the data processing operation through the data processing instruction.

[0055] In one possible implementation, the first processing unit further includes a first memory storing instructions that the first processing unit needs to execute. Accordingly, the computer device processes the input data based on the first operator through the first processing unit to obtain a processing result, including: the computer device reading a wait instruction located before the first operator from the first memory through the first processor; then executing the wait instruction, i.e., stopping the data processing operation, until the first operator is read from the first memory upon receiving a data processing instruction, and processing the input data based on the first operator to obtain a processing result.

[0056] The computer device executes instructions sequentially from the first processing unit, according to the order of instructions stored in the first memory, reading the first instruction in the order of the unexecuted instructions each time. Since there are wait instructions preceding the first operator, the first processor executes the wait instructions first until it receives the data processing instruction, then reads the next instruction after the wait instruction in the first memory, i.e., the first operator, and executes that first operator.

[0057] In this embodiment of the application, by storing a wait instruction before the first operator in the first memory, the first processing unit can only execute the first operator when it receives a data processing instruction, thereby realizing the control of the timing of the first processor to perform data processing operations.

[0058] In one possible implementation, before acquiring input data from the neural network, the computer device first divides multiple operators in the neural network into matching processing units and determines the execution order of the multiple operators within each processing unit. That is, the computer device determines the processing unit matching each of the multiple operators; for each processing unit, according to the order of the multiple operators matched by that processing unit in the neural network, the multiple operators are stored in the processing unit's memory, a wait instruction is inserted before at least one operator in the memory, and a data transmission instruction is inserted after at least one operator. The wait instruction is used to instruct the data processing operation to stop until a data processing instruction is received, at which point the data processing operation will resume; the data transmission instruction is used to instruct the processing result and the data processing instruction to be sent to other processing units when the current processing unit has completed processing based on the operator.

[0059] Because the wait instruction is inserted before the operator and indicates that data processing operations should be performed upon receiving a data processing instruction, while the data send instruction is inserted after the operator and indicates that the processing result and data processing instruction should be sent to other processing units after the current processing unit has completed processing based on the operator, so that other processing units can respond to the data processing instruction and process the result, and each processing unit executes instructions sequentially according to the order of instructions in memory, there will be no resource occupation conflict, that is, no situation where a processing unit executes multiple operators simultaneously, ensuring that a processing unit can only execute one operator at a time, and there will also be no data conflict, that is, multiple operators in the neural network can be processed sequentially, and the execution of the later operator can depend on the processing result of the previous operator. The wait instruction and the data send instruction are actually handshake signals between processing units, which enables multiple processing units to avoid data conflicts and resource conflicts when jointly processing data based on the neural network without the participation of a control unit, thus realizing a self-synchronization mechanism.

[0060] Optionally, the computer device uses a compiler to determine the processing unit that matches each of the plurality of operators. For each processing unit, according to the order in which the plurality of operators that match the processing unit are arranged in the neural network, the plurality of operators are stored in the memory of the processing unit. A wait instruction is inserted before at least one operator in the memory, and a data transmission instruction is inserted after at least one operator. Here, a compiler is a program that compiles a high-level language into a low-level language that a computer device can execute. In this embodiment, the compiler is used to divide the operators in the neural network and determine the execution order of the operators divided in each processing unit, so that the neural network can complete the division of operators and the determination of the execution order during the compilation stage.

[0061] In this embodiment of the application, considering that each operator in the neural network may be matched with a different processing unit, the operators in the neural network are divided into matching processing units before the input data is processed by the neural network, and the execution order of the multiple operators assigned to each processing unit is determined. This allows the processing unit to directly perform data processing based on the multiple operators assigned to it and the determined execution order of the operators when the input data of the neural network is subsequently obtained, instead of temporarily determining the processing unit matched to each operator during the data processing based on the neural network. This can improve the data processing efficiency.

[0062] Furthermore, by inserting a wait instruction before the operator, which indicates that a data processing operation will be performed upon receiving a data processing instruction, and inserting a data sending instruction after the operator, the processing result and the data processing instruction are sent to other processing units when the current processing unit completes processing based on the operator. This enables other processing units to respond to the data processing instruction and process the result. As a result, a self-synchronization mechanism is achieved when multiple processing units jointly perform data processing based on the neural network without the participation of a control unit.

[0063] In one possible implementation, the computer device inserts a wait instruction before at least one operator in the memory and inserts a data transmission instruction after at least one operator, including: when there is an association between at least two adjacent operators in the memory, the computer device inserts a wait instruction before the first operator of the at least two operators and inserts a data transmission instruction after the last operator of the at least two operators.

[0064] Operators that are related have data dependencies. For example, if two operators are data dependent, then the execution of one operator depends on the processing result of the other operator, that is, the output of the other operator.

[0065] In this embodiment, since there is a data dependency between adjacent operators in the neural network, if there is no data dependency between two adjacent operators assigned to any processing unit, it means that the operator that is data dependent on the previous operator of these two operators has been assigned to other processing units. Therefore, when there is an association between at least two adjacent operators in the memory, a wait instruction is inserted before the first operator of the at least two operators and a data transmission instruction is inserted after the last operator of the at least two operators, so that the two operators with data dependency in the neural network can be processed continuously, thereby ensuring the correct execution of the operators in the neural network.

[0066] 303. The computer device obtains the associated operator of the first operator and determines the associated operator as the second operator, wherein the data processing of the associated operator depends on the processing result of the first operator.

[0067] The data processing of the correlation operator depends on the processing result of the first operator; that is, the output of the first operator should be the input of the correlation operator.

[0068] In one possible implementation, the computer device obtains the associated operators of the first operator and identifies the associated operators as the second operator, including: the computer device obtaining operator association relationships, which indicate the associated operators of operators included in the neural network, wherein the data processing of the associated operators of any operator depends on the processing result of that operator. Then, the computer device queries the associated operators of the first operator from the operator association relationships; and identifies the queried associated operators as the second operator.

[0069] Optionally, the operator association relationship is the arrangement order of multiple operators in the neural network, where each operator is followed by an operator whose processing result depends on the first operator; this is called the associated operator of that operator. Accordingly, the computer device queries the operator following the first operator from this arrangement order and identifies that operator as the associated operator of the first operator.

[0070] In this embodiment of the application, considering the data dependency between multiple operators in the neural network, after the first operator is executed, the associated operator of the first operator is determined as the second operator, and the processing result of the first operator is sent to the processing unit matched by the second operator. This ensures that the execution of the second operator can be based on the processing result of the first operator, thus ensuring the correct execution of the operators in the neural network.

[0071] 304. The computer device sends the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit, and the second processing unit matches the second operator among the plurality of operators.

[0072] In one possible implementation, the second processing unit includes a second processor and a second memory. Accordingly, the computer device sends a processing result to the second processing unit via a direct connection between the first and second processing units. This includes: the computer device storing the processing result in the second memory via the direct connection between the first and second processing units, and sending a data processing instruction to the second processor. Optionally, the data processing instruction carries the storage address of the processing result.

[0073] In this embodiment, the first processing unit does not need to store the processing result in a common memory unit via a bus, and then have the second processing unit read the processing result from the common memory unit via the bus. Instead, the processing result is directly stored in the memory of the second processing unit via a direct connection. This allows the processor of the second processing unit to directly read the processing result from its own memory and process it when it receives a data processing instruction, greatly shortening the data transmission link and thus improving the efficiency of data interaction.

[0074] In one possible implementation, the first processing unit includes a first processor and a first memory. Accordingly, the computer device, through the first processing unit, stores the processing result in the second memory based on a direct connection with the second processing unit, and sends a data processing instruction to the second processor. This includes: the computer device, through the first processor, reading a data sending instruction located after the first operator from the first memory; in response to the data sending instruction, storing the processing result in the second memory based on the direct connection with the second processor; and sending a data processing instruction to the second processor, wherein the data sending instruction is used to instruct that when the current processing unit completes processing based on the operator, the processing result and the data processing instruction are sent to other processing units.

[0075] In this embodiment, since the data sending instruction is used to instruct the current processing unit to send the processing result and the data processing instruction to other processing units when the current processing unit completes the processing based on the operator, by storing the data sending instruction after the operator in the memory of the processing unit, the processing unit can execute the data sending instruction after executing the operator, thereby realizing the storage of the processing result in the memory of the second processor and the sending of the data processing instruction to the second processor, so that the second processing unit can read the processing result from its own memory based on the data processing instruction and continue to process the processing result.

[0076] In one possible implementation, after the computer device processes the input data based on a first operator through a first processing unit to obtain a processing result, and before sending the processing result to a second processing unit, the method further includes: the computer device processes the processing result based on a third operator through the first processing unit to obtain an updated processing result, wherein the third operator is an operator in a neural network, and the third operator is matched with the first processing unit. Optionally, the third operator is an associated operator of the first operator, that is, the input of the third operator is the output of the first operator, and the third operator depends on the processing result of the first operator.

[0077] It should be noted that, since at least two consecutive operators in a neural network may match the same processing unit, after the current processing unit processes based on the current operator, if the next operator still matches the processing unit, the processing unit will continue processing based on that operator to obtain an updated processing result, until the next operator after the currently processed operator does not match the current processing unit. Then, the current processing unit sends the latest processing result to the processing unit that matches the next operator.

[0078] In this embodiment of the application, the first processing unit can process the processing result based on the third operator to obtain the updated processing result, and then send the updated processing result to the second processing unit. In other words, the same processing unit can continuously execute multiple matching operators, which ensures that when multiple processing units perform data processing together based on the neural network, each processing unit can execute the operator that matches it, and the execution order of multiple operators in the neural network is accurate.

[0079] 305. The computer device processes the processing result based on the second operator through the second processing unit.

[0080] In one possible implementation, the computer device executes a wait instruction via a second processor of the second processing unit to wait for a data processing instruction from the first processing unit; in response to receiving a data processing instruction from the first processing unit, it processes the processing result based on a second operator.

[0081] Optionally, the wait instruction is sent by the CPU to the second processing unit, or the wait instruction is read by the second processing unit from memory, which can be any memory, such as public memory or memory within the second processing unit. This application embodiment does not limit this.

[0082] Optionally, the computer device stores the processing result in the second memory of the second processing unit through the first processor of the first processing unit, and the data processing instruction includes the storage address of the processing result in the second memory. Accordingly, the computer device reads the processing result from the second memory based on the storage address in response to receiving the data processing instruction from the first processing unit through the second processor.

[0083] In this embodiment, since the wait instruction is used to indicate that the data processing operation is stopped and resumed when the data processing instruction is received, the second processor executes the wait instruction, thereby realizing the timing of the second processor executing the data processing operation through the data processing instruction.

[0084] In one possible implementation, the computer device reads a wait instruction located before the second operator from the second memory via a second processor; then executes the wait instruction, i.e., stops executing the data processing operation until a data processing instruction is received, at which point the second operator is read from the second memory, and the processing result is processed based on the second operator.

[0085] The computer device executes instructions sequentially from the second processing unit, according to the order of instructions stored in the second memory, reading the first instruction in the order of the unexecuted instructions each time. Since there are wait instructions preceding the second operator, the second processor executes the wait instructions first until it receives the data processing instruction, then reads the next instruction after the wait instruction in the second memory, i.e., the second operator, and executes that second operator.

[0086] In this embodiment of the application, by storing a wait instruction before the second operator in the second memory, the second processing unit can only execute the second operator when it receives a data processing instruction, thereby realizing the control of the timing of the second processor to perform data processing operations.

[0087] It's important to note that if the second operator is the last operator in the neural network, the second processing unit processes the result based on the second operator to obtain the neural network's output data. If the second operator is not the last operator in the neural network, the second processing unit processes the result based on the second operator to obtain an updated result, and then the second processing unit or other processing units execute other operators in the neural network. For example, in the neural network, if the next operator after the second operator is the fourth operator, and the fourth operator matches the third processing unit, the second processing unit sends the updated result to the third processing unit, which then continues processing based on the fourth operator, and so on, until all operators in the neural network have been executed. The way the second processing unit sends the result to the third processing unit is the same as the way the first processing unit sends the result to the second processing unit, and the way the third processing unit processes data based on the fourth operator is the same as the way the second processing unit processes data based on the second operator; these details will not be elaborated further here.

[0088] It should be noted that step 303 above is an optional step. For example, in the case of only two processing units, the computer device does not need to first determine the second operator and then determine which processor the first processing unit should send the processing result to based on the second operator. For example, after the computer device executes the first operator through the first processing unit, if the next instruction in the first memory following the first operator is a data transmission instruction, then the computer device can directly send the processing result and the data processing instruction to the other processing unit besides the first processing unit through the first processing unit.

[0089] Figure 4 This is a schematic diagram illustrating a connection method between processing units provided in an embodiment of this application. (See reference) Figure 4Taking two processing units as an example, the first and second processing units are respectively connected to the control unit, and both are connected to a common storage unit via a bus. In related technologies, after the first processing unit executes an operator in the neural network, it stores the processing result in the common storage unit via the bus, and then notifies the control unit via an interrupt. The control unit determines the processing unit matched for the next operator in the neural network. If the processing unit is the second processing unit, the control unit sends a notification to the second processing unit. The second processing unit then reads the processing result from the common storage unit via the bus, and performs data processing based on the next operator, and so on, until multiple operators in the neural network have been processed. In this process, the control unit needs to interact frequently with each processing unit, consuming the control unit's resources. Furthermore, the interaction efficiency between the processing units is extremely low. Also, because the processing result is stored in the common storage unit, the data storage and retrieval links are long, resulting in extremely low data transmission efficiency. In this embodiment, a direct connection is added between the first processing unit and the second processing unit, enabling the first processing unit and the second processing unit to interact directly based on the direct connection. This greatly shortens the transmission link of the processing results. Furthermore, the first processing unit and the second processing unit achieve self-synchronization based on waiting instructions and data sending instructions, eliminating the need for a control unit and improving interaction efficiency. As a result, the overall efficiency of data processing based on neural networks is improved.

[0090] Figure 5 This is a schematic diagram of a processing unit provided in an embodiment of this application. (Reference) Figure 5 Each processing unit includes a processor and a memory, which are connected. The processor is capable of reading data from the memory and storing data in the memory. Furthermore, two processing units are directly connected, and either processing unit can directly store data in the memory of another processing unit directly connected to it. For example, a first processor in a first processing unit can directly store data in a second memory, and a second processor in a second processing unit can directly store data in a first memory.

[0091] The following is based on Figure 6 The data processing procedure in this application is illustrated using the neural network shown as an example.

[0092] First, computer equipment uses a compiler to compile the neural network, thereby assigning the multiple operators in the neural network to matching processing units. For example... Figure 6As shown, since operators 0, 2, and 4 in the neural network are matched with the first processing unit, and operators 1, 3, and 5 are matched with the second processing unit, operators 0, 2, and 4 are allocated to the first memory of the first processing unit, and operators 1, 3, and 5 are allocated to the second memory of the second processing unit. Then, the computer device inserts a wait instruction before each operator in the first and second memories, and inserts a data transmission instruction after each operator.

[0093] Second, the first processor in the first processing unit reads and executes instructions sequentially according to the order of instructions in the first memory. It first reads and executes a wait instruction, which stops data processing operations in order to wait for a data processing instruction. Similarly, the second processor in the second processing unit reads and executes instructions sequentially according to the order of instructions in the second memory. It first reads and executes a wait instruction, which stops data processing operations in order to wait for a data processing instruction.

[0094] Third, the computer device, through the CPU, stores the input data of the neural network in the target storage location, and then sends a data processing instruction to the first processor in the first processing unit. In response to this instruction, the first processor reads the input data from the storage location and reads operator 0 from the first memory. Based on operator 0, it processes the input data to obtain the processing result. Then, it reads the data transmission instruction following operator 0 from the first memory. In response to this instruction, based on the direct connection between the first and second processing units, it stores the processing result in the second memory of the second processing unit and sends a data processing instruction to the second processor in the second processing unit. Finally, the first processor reads the wait instruction preceding operator 2 from the first memory and executes the wait instruction.

[0095] Fourth, during the execution of the wait instruction, the second processor receives a data processing instruction sent by the first processor. In response to this instruction, it reads operator 1 and its processing result from the second memory, and further processes the result based on operator 1 to obtain an updated result. Then, it reads the data sending instruction following operator 1, and in response, stores the updated result in the first memory and sends a data processing instruction to the first processor. Finally, the second processor reads the wait instruction preceding operator 3 and executes it.

[0096] Fifth, during the execution of the wait instruction, the first processor receives a data processing instruction from the second processor. In response to this instruction, it reads operator 2 and the latest processing result from the first memory, and continues processing the result based on operator 2 to obtain an updated result. Then, the first processor reads the data sending instruction following operator 2, stores the updated processing result in the second memory, and sends a data processing instruction to the second processor. Next, the first processor reads the wait instruction preceding operator 4 and executes it. This process continues until all operators in the neural network have completed data processing.

[0097] Sixth, taking the processing unit that matches the last operator in the neural network as the first processing unit as an example, after the first processor finishes executing the last operator, it stores the obtained output data in the common storage unit based on the bus, and then sends a processing completion notification to the CPU in the form of an interrupt to notify the server that the current input data processing is complete.

[0098] Seventh, in response to the processing completion notification, the CPU stores the new input data in the target storage location, sends a data processing instruction to the first processor, and then the first processor processes the new input data in the same way.

[0099] The following is based on Figure 7 The data processing procedure in this application is illustrated using the neural network shown as an example.

[0100] First, computer equipment uses a compiler to compile the neural network, thereby assigning the multiple operators in the neural network to matching processing units. For example... Figure 7 As shown, since operators 0 and 4 in the neural network are matched with the first processing unit, and operators 1, 2, 3, and 5 are matched with the second processing unit, operators 0 and 4 are allocated to the first memory of the first processing unit, and operators 1, 2, 3, and 5 are allocated to the second memory of the second processing unit. Then, the computer device inserts a wait instruction before each operator in the first memory and a data transmission instruction after each operator. Similarly, the computer device inserts a wait instruction before operators 1 and 5 in the second memory and a data transmission instruction after operators 3 and 5. It should be noted that there is an association between operators 1 and 2, meaning that operator 2 processes based on the result of operator 1. There is also an association between operators 2 and 3, meaning that operator 3 processes based on the result of operator 2. Therefore, a wait instruction is inserted before operator 1 and a data send instruction is inserted after operator 3, instead of inserting wait instructions and data send instructions between these three operators, to ensure that the second processing unit can execute these three operators continuously.

[0101] Second, the first processor in the first processing unit reads and executes instructions sequentially according to the order of instructions in the first memory. It first reads and executes a wait instruction, which stops data processing operations in order to wait for a data processing instruction. Similarly, the second processor in the second processing unit reads and executes instructions sequentially according to the order of instructions in the second memory. It first reads and executes a wait instruction, which stops data processing operations in order to wait for a data processing instruction.

[0102] Third, the computer device, through the CPU, stores the input data of the neural network in the target storage location, and then sends a data processing instruction to the first processor in the first processing unit. In response to this instruction, the first processor reads the input data from the storage location and reads operator 0 from the first memory. Based on operator 0, it processes the input data to obtain a processing result. Then, it reads the data transmission instruction following operator 0 from the first memory. In response to this instruction, based on the direct connection between the first and second processing units, it stores the processing result in the second memory of the second processing unit and sends a data processing instruction to the second processor in the second processing unit. Finally, the first processor reads the wait instruction preceding operator 4 from the first memory and executes it.

[0103] Fourth, during the execution of the wait instruction, the second processor receives a data processing instruction sent by the first processor. In response to this instruction, it reads operator 1 and its processing result from the second memory, and further processes the result based on operator 1 to obtain an updated result. Then, it reads operator 2 from the second memory and processes the current result based on operator 2 to obtain an updated result. Next, it reads operator 3 from the second memory and processes the current result based on operator 3 to obtain an updated result. Then, it reads the data transmission instruction following operator 3, and in response, stores the updated result in the first memory and sends a data processing instruction to the first processor. Finally, the second processor reads the wait instruction preceding operator 5 and executes it.

[0104] Fifth, during the execution of the wait instruction, the first processor receives a data processing instruction from the second processor. In response to this instruction, it reads operator 4 and the latest processing result from the first memory, processes the result based on operator 4, and obtains an updated result. Then, the first processor reads the data sending instruction following operator 4, stores the updated result in the second memory, and sends a data processing instruction to the second processor. Next, the first processor reads the wait instruction following operator 4 and executes it. This process continues until all operators in the neural network have completed data processing.

[0105] Sixth, taking the processing unit that matches the last operator in the neural network as the first processing unit as an example, after the first processor finishes executing the last operator, it stores the obtained output data in the common storage unit based on the bus, and then sends a processing completion notification to the CPU in the form of an interrupt to notify the server that the current input data processing is complete.

[0106] Seventh, in response to the processing completion notification, the CPU stores the new input data in the target storage location, sends a data processing instruction to the first processor, and then the first processor processes the new input data in the same way.

[0107] The data processing scheme provided in this application adds a direct connection between processing units, enabling them to interact directly through this direct connection. This greatly improves the interaction efficiency between processing units. In this case, after processing a unit performs data processing based on a matching operator, it directly sends the processing result to another processing unit. The other processing unit can then directly obtain the processing result and continue processing it. This scheme eliminates the need for a control unit, allowing processing units to cooperate directly and without obstacles, thereby improving the efficiency of data processing through operators in the neural network.

[0108] Furthermore, since the wait instruction is used to indicate the cessation of data processing operations until a data processing instruction is received, the first processor executes the wait instruction, thus enabling the timing of the first processor's execution of data processing operations to be controlled through the data processing instruction.

[0109] Furthermore, by storing a wait instruction before the first operator in the first memory, the first processing unit can only execute the first operator when it receives a data processing instruction, thereby controlling the timing of the first processor's execution of data processing operations.

[0110] Furthermore, considering that each operator in a neural network may be matched with a different processing unit, the operators in the neural network are assigned to matching processing units before the input data is processed by the neural network. The execution order of the multiple operators assigned to each processing unit is also determined. This allows the processing unit to directly process the data based on the multiple operators assigned to it and the determined execution order of the operators when the input data of the neural network is subsequently obtained, rather than temporarily determining the processing unit matched to each operator during the data processing based on the neural network. This can improve the data processing efficiency.

[0111] Furthermore, by inserting a wait instruction before the operator, which indicates that a data processing operation will be performed upon receiving a data processing instruction, and inserting a data sending instruction after the operator, the processing result and the data processing instruction are sent to other processing units when the current processing unit completes processing based on the operator. This enables other processing units to respond to the data processing instruction and process the result. As a result, a self-synchronization mechanism is achieved when multiple processing units jointly perform data processing based on the neural network without the participation of a control unit.

[0112] Furthermore, since adjacent operators in a neural network have data dependencies, if two adjacent operators assigned to any processing unit do not have data dependencies, it means that the operator that has data dependencies on the previous operator of these two operators has been assigned to other processing units. Therefore, when there is an association between at least two adjacent operators in memory, a wait instruction is inserted before the first operator of the at least two operators, and a data send instruction is inserted after the last operator of the at least two operators. This allows the two operators with data dependencies to be processed continuously, thereby ensuring the correct execution of operators in the neural network.

[0113] Furthermore, considering the data dependencies between multiple operators in a neural network, after executing the first operator, the associated operator of the first operator is determined as the second operator. Subsequently, the processing result of the first operator is sent to the processing unit matched by the second operator. This ensures that the execution of the second operator is based on the processing result of the first operator, thus guaranteeing the correct execution of the operators in the neural network.

[0114] Furthermore, the first processing unit does not need to store the processing result in a common memory unit via a bus, and then have the second processing unit read the processing result from the common memory unit via a bus. Instead, it directly stores the processing result in the memory of the second processing unit based on a direct connection between the two units. This allows the processor of the second processing unit to directly read the processing result from its own memory and process it when it receives a data processing instruction, greatly shortening the data transmission link and thus improving the efficiency of data interaction.

[0115] Furthermore, the first processing unit can process the processing result based on the third operator to obtain the updated processing result, and then send the updated processing result to the second processing unit. In other words, the same processing unit can continuously execute multiple matching operators, which ensures that when multiple processing units jointly process data based on the neural network, each processing unit can execute the operator that matches it, and the execution order of multiple operators in the neural network is accurate.

[0116] Furthermore, since the wait instruction is used to indicate the cessation of data processing operations until a data processing instruction is received, the second processor executes the wait instruction, thus enabling the timing of the second processor's data processing operations to be controlled through the data processing instruction.

[0117] Furthermore, by storing a wait instruction before the second operator in the second memory, the second processing unit can only execute the second operator when it receives a data processing instruction, thereby controlling the timing of the second processor's data processing operations.

[0118] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0119] Please refer to Figure 8 This illustration shows a structural block diagram of a data processing apparatus provided in an exemplary embodiment of this application. The data processing apparatus includes:

[0120] The first processing module 801 is used to process the input data through the first processing unit based on the first operator of the neural network to obtain the processing result. The first processing unit is matched with the first operator.

[0121] The data sending module 802 is used to send the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit, and the second processing unit matches the second operator of the neural network.

[0122] The second processing module 803 is used to process the processing result based on the second operator through the second processing unit.

[0123] The data processing scheme provided in this application adds a direct connection between processing units, enabling them to interact directly through this direct connection. This greatly improves the interaction efficiency between processing units. In this case, after processing a unit performs data processing based on a matching operator, it directly sends the processing result to another processing unit. The other processing unit can then directly obtain the processing result and continue processing it. This scheme eliminates the need for a control unit, allowing processing units to cooperate directly and without obstacles, thereby improving the efficiency of data processing through operators in the neural network.

[0124] In one possible implementation, the first processing unit includes a first processor.

[0125] The first processing module 801 is configured to execute a wait instruction via a first processor to wait for a data processing instruction; and in response to receiving a data processing instruction, to process the input data based on a first operator to obtain a processing result.

[0126] In one possible implementation, the second processing unit includes a second processor and a second memory.

[0127] The data transmission module 802 is used to store the processing results in the second memory through the first processing unit based on the direct connection path, and to send data processing instructions to the second processor.

[0128] In one possible implementation, the second processing module 803 is configured to execute a wait instruction via a second processor to wait for a data processing instruction from the first processing unit; and in response to receiving a data processing instruction from the first processing unit, to process the processing result based on a second operator.

[0129] In one possible implementation, the device further includes:

[0130] The unit determination module is used to determine the processing unit that matches each of the multiple operators contained in the neural network;

[0131] The data storage module is used to store multiple operators in the memory of each processing unit according to the order of the multiple operators matched by the processing unit in the neural network, insert a wait instruction before at least one operator in the memory, and insert a data transmission instruction after at least one operator.

[0132] The waiting instruction is used to instruct the data processing operation to stop until a data processing instruction is received, at which point the data processing operation will be resumed. The data sending instruction is used to instruct the processing result and the data processing instruction to be sent to other processing units when the current processing unit has completed processing based on the operator.

[0133] In one possible implementation, the data storage module is configured to insert a wait instruction before the first of at least two adjacent operators and a data send instruction after the last of at least two operators, provided that there is an association between them in the memory; wherein the associated operators have data dependencies.

[0134] In one possible implementation, the first processing module 801 is further configured to process the processing result based on the third operator through the first processing unit to obtain an updated processing result, wherein the third operator is matched with the first processing unit.

[0135] In one possible implementation, the device further includes:

[0136] The operator determination module is used to obtain operator association relationships. The operator association relationships indicate the associated operators of the operators contained in the neural network. The data processing of associated operators depends on the processing results of the operators. From the operator association relationships, the associated operators of the first operator are queried. The queried associated operators are determined as the second operator.

[0137] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0138] This application provides a computer device including a processor and a memory; the memory stores at least one piece of program code, which is executed by the processor to implement the data processing methods provided in the above-described method embodiments.

[0139] Optionally, the computer device is equipped with a chip, such as an artificial intelligence chip, through which the computer device can execute the data processing methods in the embodiments of this application.

[0140] In some embodiments, the computer device is a terminal; please refer to [reference needed]. Figure 9This diagram illustrates a structural block diagram of a terminal provided in an exemplary embodiment of this application. In some embodiments, the terminal 900 is a smartphone, tablet, wearable device, or other terminal capable of accessing a wireless local area network as a wireless station. The terminal 900 in this application includes at least one or more of the following components: a processor 910, a memory 920, and at least two wireless links 930.

[0141] In some embodiments, the processor 910 includes one or more processing cores. The processor 910 connects to various parts within the terminal 900 using various interfaces and lines, and executes various functions and processing results of the terminal 900 by running or executing program code stored in the memory 920 and calling data stored in the memory 920. In some embodiments, the processor 910 is implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 910 can integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and modem. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the modem is used for wireless communication. It is understandable that the aforementioned modem could also be implemented separately as a single chip without being integrated into the processor 910.

[0142] In some embodiments, the processor 910 is used to control the operating status of at least two wireless links 930. Accordingly, the processor 910 is a processor integrating a Wireless Fidelity (Wi-Fi) chip. This Wi-Fi chip is a chip with dual Wi-Fi processing capabilities. For example, the Wi-Fi chip is a dual-band dual-concurrent (DBDC) chip, or a dual-band simultaneous (DBS) chip, etc.

[0143] In some embodiments, the memory 920 includes random access memory (RAM), and in some embodiments, the memory 920 includes read-only memory (ROM). In some embodiments, the memory 920 includes non-transitory computer-readable storage medium. The memory 920 can be used to store program code. The memory 920 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described below, etc.; the data storage area may store data created according to the use of the terminal 900 (such as audio data, phone book, etc.).

[0144] In some embodiments, the memory 920 stores reception schemes for different wireless links 930 receiving beacon frames, as well as identifiers of access nodes connected to different wireless links 930, identifiers of the wireless links 930, etc.

[0145] The at least two wireless links 930 are used to connect different access points (APs). They receive downlink data from the APs. These different access points can be access points within the same router or access points within different routers.

[0146] In some embodiments, the terminal 900 further includes a display screen. The display screen is a display component used to display a user interface. In some embodiments, the display screen is a touch-enabled display screen, allowing users to perform touch operations on the display screen using fingers, styluses, or any suitable object. In some embodiments, the display screen is typically located on the front panel of the terminal 900. In some embodiments, the display screen is designed as a full-screen, curved screen, irregularly shaped screen, dual-sided screen, or foldable screen. In some embodiments, the display screen is also designed as a combination of a full-screen and a curved screen, or a combination of an irregularly shaped screen and a curved screen, etc., which are not limited in this embodiment.

[0147] In addition, those skilled in the art will understand that the structure of the terminal 900 shown in the above figures does not constitute a limitation on the terminal 900. The terminal 900 may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the terminal 900 may also include components such as a microphone, speaker, input unit, sensor, audio circuit, module, power supply, and Bluetooth module, which will not be described in detail here.

[0148] In some embodiments, the computer device is a server; please refer to [reference needed]. Figure 10 This diagram illustrates a structural block diagram of a server provided in an exemplary embodiment of this application. The server 1000 can vary significantly due to different configurations or performance characteristics. It may include one or more Central Processing Units (CPUs) 1001 and one or more memories 1002. The memories 1002 store at least one line of program code, which is loaded and executed by the processor 1001 to implement the methods provided in the various method embodiments described above. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated upon here.

[0149] This application also provides a computer-readable storage medium storing at least one piece of program code, which is loaded and executed by the processor to implement the data processing methods shown in the above embodiments.

[0150] According to another aspect of the embodiments of this application, a chip is provided, which includes programmable logic circuits and / or program instructions, and when the chip is run on a terminal, it is used to implement the data processing methods shown in the various embodiments above.

[0151] This application also provides a computer program product that stores at least one piece of program code, which is loaded and executed by the processor to implement the data processing methods shown in the above embodiments.

[0152] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0153] Those skilled in the art will understand that all or part of the steps in the data processing method of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. The above descriptions are merely optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing method, characterized in that, The method includes: The first processing unit processes the input data based on the first operator of the neural network to obtain the processing result, and the first processing unit is matched with the first operator. Based on the direct connection between the first processing unit and the second processing unit, the processing result is sent to the second processing unit, and the second processing unit is matched with the second operator of the neural network; The processing result is processed by the second processing unit based on the second operator; The method further includes: Determine the processing unit that matches each of the multiple operators contained in the neural network; For each processing unit, according to the order in which the multiple operators matched by the processing unit are arranged in the neural network, the multiple operators are stored in the memory of the processing unit, a wait instruction is inserted before at least one operator in the memory, and a data transmission instruction is inserted after at least one operator. The waiting instruction is used to instruct the data processing operation to stop until a data processing instruction is received, at which point the data processing operation will be resumed. The data sending instruction is used to instruct the processing unit to send the processing result and the data processing instruction to other processing units when the current processing unit completes processing based on the operator.

2. The method according to claim 1, characterized in that, The first processing unit includes a first processor. The step of processing the input data using a first operator based on a neural network to obtain a processing result includes: The first processor executes a wait instruction to wait for a data processing instruction; In response to receiving the data processing instruction, the input data is processed based on the first operator to obtain the processing result.

3. The method according to claim 1, characterized in that, The second processing unit includes a second processor and a second memory. The step of sending the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit includes: The first processing unit stores the processing result in the second memory based on the direct connection path and sends data processing instructions to the second processor.

4. The method according to claim 3, characterized in that, The method further includes: The second processor executes a wait instruction to wait for a data processing instruction from the first processing unit. In response to receiving a data processing instruction from the first processing unit, the processing result is processed based on the second operator.

5. The method according to claim 1, characterized in that, The insertion of a wait instruction before at least one operator in the memory and the insertion of a data transmission instruction after at least one operator include: In the case where there is an association between at least two adjacent operators in the memory, the wait instruction is inserted before the first operator among the at least two operators, and the data transmission instruction is inserted after the last operator among the at least two operators; The operators with the aforementioned relationships have data dependencies on each other.

6. The method according to any one of claims 1-4, characterized in that, After the first processing unit processes the input data based on the first operator of the neural network to obtain the processing result, and before sending the processing result to the second processing unit, the method further includes: The first processing unit processes the processing result based on the third operator to obtain the updated processing result, wherein the third operator is matched with the first processing unit.

7. The method according to any one of claims 1-4, characterized in that, Before sending the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit, the method further includes: Obtain operator association relationships, wherein the operator association relationships indicate the associated operators of the operators contained in the neural network, and the data processing of the associated operators depends on the processing results of the operators; From the operator association relationships, query the associated operators of the first operator; The queried association operator is identified as the second operator.

8. A data processing apparatus, characterized in that, The device includes: The first processing module is used to process the input data through the first processing unit based on the first operator of the neural network to obtain the processing result, wherein the first processing unit is matched with the first operator; The data sending module is used to send the processing result to the second processing unit based on the direct connection between the first processing unit and the second processing unit, wherein the second processing unit is matched with the second operator of the neural network; The second processing module is used to process the processing result based on the second operator through the second processing unit; The device further includes: The unit determination module is used to determine the processing unit that matches each of the multiple operators contained in the neural network; A data storage module is configured to, for each processing unit, store the plurality of operators in the memory of the processing unit according to the arrangement order of the plurality of operators matched by the processing unit in the neural network, insert a wait instruction before at least one operator in the memory, and insert a data transmission instruction after at least one operator. The waiting instruction is used to instruct the data processing operation to stop until a data processing instruction is received, at which point the data processing operation will be resumed. The data sending instruction is used to instruct the processing unit to send the processing result and the data processing instruction to other processing units when the current processing unit completes processing based on the operator.

9. The apparatus according to claim 8, characterized in that, The first processing unit includes a first processor; The first processing module is configured to execute a wait instruction via the first processor to wait for a data processing instruction; and in response to receiving the data processing instruction, to process the input data based on the first operator to obtain the processing result.

10. The apparatus according to claim 8, characterized in that, The second processing unit includes a second processor and a second memory. The data transmission module is used to store the processing result in the second memory based on the direct connection path through the first processing unit, and to send data processing instructions to the second processor.

11. The apparatus according to claim 10, characterized in that, The device further includes: The second processing module is configured to execute a wait instruction via the second processor to wait for a data processing instruction from the first processing unit; and in response to receiving a data processing instruction from the first processing unit, to process the processing result based on the second operator.

12. A computer device, characterized in that, The computer device includes a processor and a memory; the memory stores at least one piece of program code, which is executed by the processor to implement the data processing method as described in any one of claims 1 to 7.

13. A computer-readable storage medium, characterized in that, The storage medium stores at least one piece of program code, which is executed by a processor to implement the data processing method as described in any one of claims 1 to 7.

14. A chip, characterized in that, The chip includes programmable logic circuits and / or program instructions, which, when the chip is run on a terminal, are used to implement the data processing method as described in any one of claims 1 to 7.

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