Array substrate, manufacturing method thereof and display device

Abstract

The application discloses an array substrate and a preparation method thereof and a display device. The preparation method comprises the following steps: providing a substrate, depositing a transparent metal oxide conductive layer, patterning the transparent metal oxide conductive layer by using a first mask to form a transparent conductive layer, reducing the transparent conductive layer to form a metal reflective layer, depositing a buffer layer and a transparent metal oxide semiconductor layer, patterning the transparent metal oxide semiconductor layer by using a second mask to form a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, reducing the third semiconductor layer to form a drain, depositing an insulating layer and a gate metal layer, patterning the gate and the gate insulating layer by using a third mask, and ion-doping the second semiconductor layer and the first semiconductor layer which are not covered by the gate and the gate insulating layer to form a pixel electrode and a pixel electrode connecting area. By using the above method, the problem that the brightness of the display device cannot be improved under the condition of considering the cost and ensuring the stability of the device is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a method for fabricating the same, and a display device. Background Technology

[0002] Liquid crystal display (LCD) technology has undergone a long development cycle and is now a mature display technology. Among them, thin film transistor liquid crystal displays (TFT-LCD) have become the mainstream product in LCD display technology applications due to their advantages such as thinness, environmental friendliness, high performance, and long lifespan, as well as their wide applicability to various sizes.

[0003] Existing TFT-LCD liquid crystal display devices consist of a liquid crystal display panel and a backlight module. The liquid crystal display panel typically comprises a color filter (CF) substrate, a thin film transistor (TFT) substrate, and a liquid crystal (LC) layer sandwiched between the two substrates. Since the liquid crystal display panel itself does not emit light, the display effect is mainly achieved by the backlight module emitting light, which is then adjusted by the liquid crystal layer of the display panel to control the brightness of the screen. Because top-gate coplanar TFTs can use self-alignment processes, reducing parasitic capacitance and allowing for smaller fabrication, they are widely used in the development of high-resolution liquid crystal displays.

[0004] However, since there is no obstruction below the top-gate TFT, the conductive channel is more susceptible to the influence of the backlight and ambient light from below, which will affect the electrical stability of the TFT. Furthermore, the improvement of the brightness of liquid crystal display devices is usually accompanied by the increase of process technology, the increase of production cost, and the reduction of lifespan. It is impossible to improve the brightness of liquid crystal display devices while taking into account both cost and device stability. Summary of the Invention

[0005] This application mainly provides an array substrate and its fabrication method, as well as a display device, to solve the problem in the prior art that it is impossible to improve the brightness of the display device while taking into account both cost and device stability.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a method for fabricating an array substrate for use in a liquid crystal display device, comprising:

[0007] A substrate is provided, on which a transparent metal oxide conductive layer is deposited;

[0008] The transparent metal oxide conductive layer is patterned using a first photomask to form a common electrode and a transparent conductive layer spaced apart from each other;

[0009] The transparent conductive layer is reduced using a plasma reducing gas to form a metallic reflective layer;

[0010] A buffer layer and a transparent metal oxide semiconductor layer are deposited sequentially; the transparent metal oxide semiconductor layer is patterned using a second photomask to form a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer.

[0011] The third semiconductor layer is reduced using a plasma reducing gas to form a drain electrode;

[0012] An insulating layer and a gate metal layer are deposited sequentially; the gate metal layer and the insulating layer are patterned using a third photomask to form a gate and a gate insulating layer; wherein the gate and the gate insulating layer cover a portion of the second semiconductor layer;

[0013] The portion of the second semiconductor layer not covered by the gate and the gate insulating layer is ion-doped with the first semiconductor layer to form a pixel electrode-pixel electrode connection region.

[0014] The first passivation layer and the second passivation layer are deposited sequentially.

[0015] The step of patterning the transparent metal oxide conductive layer using a first photomask to form mutually spaced common electrodes and a transparent conductive layer includes:

[0016] A first photoresist layer is deposited on the transparent metal oxide conductive layer;

[0017] The first photoresist layer is patterned using a first photomask to form a first photoresist segment and a second photoresist segment spaced apart from each other; the thickness of the first photoresist segment is greater than the thickness of the second photoresist segment.

[0018] Using the first photoresist segment and the second photoresist segment as blocking layers, the transparent metal oxide conductive layer is etched to obtain the common electrode corresponding to the first photoresist segment and the transparent conductive layer corresponding to the second photoresist segment.

[0019] The step of reducing the transparent conductive layer with a plasma reducing gas to form a metallic reflective layer includes:

[0020] The first and second photoresist segments are subjected to ashing treatment;

[0021] While thinning the first photoresist segment, the second photoresist segment is removed to expose the transparent conductive layer;

[0022] Using the first photoresist segment as a blocking layer, the transparent conductive layer is reduced by plasma reducing gas to form the metallic reflective layer;

[0023] Remove the first photoresist segment to expose the common electrode.

[0024] Wherein, the first photoresist layer is a positive photoresist; the thickness of the first photoresist segment is 2-4 μm, the thickness of the second photoresist segment is 0.5-1.5 μm; the first photomask includes an opaque area corresponding to the first photoresist segment, a semi-transparent area corresponding to the second photoresist segment, and a fully transparent area corresponding to the remaining positions.

[0025] The step of patterning the transparent metal oxide semiconductor layer using a second photomask to form the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes:

[0026] A second photoresist layer is deposited on the transparent metal oxide semiconductor layer;

[0027] The second photoresist layer is patterned using a second photomask to form a third photoresist segment and a fourth photoresist segment; the thickness of the third photoresist segment is greater than the thickness of the fourth photoresist segment.

[0028] Using the third and fourth photoresist segments as blocking layers, the transparent metal oxide semiconductor layer is etched to obtain the first semiconductor layer and the second semiconductor layer corresponding to the third photoresist segment, and the third semiconductor layer corresponding to the fourth photoresist segment.

[0029] The step of reducing the third semiconductor layer with a plasma reducing gas to form the drain includes:

[0030] The third and fourth photoresist segments are subjected to ashing treatment;

[0031] While thinning the third photoresist segment, the fourth photoresist segment is removed to expose the third semiconductor layer;

[0032] Using the third photoresist segment as a barrier layer, the third semiconductor layer is reduced by plasma reducing gas to form the drain electrode;

[0033] Remove the third photoresist segment to expose the first semiconductor layer and the second semiconductor layer.

[0034] Wherein, the second photoresist layer is a positive photoresist; the thickness of the third photoresist segment is 2-4 μm, and the thickness of the fourth photoresist segment is 0.5-1.5 μm; the second photomask includes an opaque area corresponding to the third photoresist segment, a semi-transparent area corresponding to the fourth photoresist segment, and a fully transparent area corresponding to the remaining positions.

[0035] The step of patterning the gate metal layer and the insulating layer using a third photomask to form the gate and the gate insulating layer includes:

[0036] A third photoresist layer is deposited on the gate metal layer;

[0037] The third photoresist layer is patterned using a third photomask to form the fifth photoresist segment;

[0038] Using the fifth photoresist segment as a blocking layer, the gate metal layer and the insulating layer are etched to obtain the gate and gate insulating layer corresponding to the fifth photoresist segment;

[0039] Remove the fifth photoresist segment to expose the gate.

[0040] The third photoresist layer is a positive photoresist; the thickness of the fifth photoresist segment is 0.5-1.5 μm; the third photomask includes an opaque area corresponding to the fifth photoresist segment and a fully transparent area corresponding to the remaining positions.

[0041] Wherein, the portion of the second semiconductor layer covered by the gate and the gate insulating layer forms a conductive channel;

[0042] The transparent metal oxide conductive layer is made of one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; the thickness of the transparent metal oxide conductive layer is 550-700 μm; the plasma reducing gas includes any one of hydrogen and carbon monoxide; the transparent metal oxide semiconductor layer is made of amorphous indium gallium zinc oxide; the thickness of the transparent metal oxide semiconductor layer is 400-1700 μm;

[0043] The first, second, and third photomasks include any one of grayscale photomasks, halftone photomasks, phase-shifting mask photomasks, and single-slit photomasks.

[0044] The ion doping method is plasma doping; the plasma doping gas includes any one of hydrogen, ammonia, and argon.

[0045] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide an array substrate prepared by any of the preparation methods described above, comprising:

[0046] substrate;

[0047] A common electrode and a metal reflective layer are disposed on one side of the substrate; the common electrode and the metal reflective layer are disposed in the same layer and spaced apart from each other.

[0048] A buffer layer is disposed on the side of the common electrode and the metal reflective layer away from the substrate;

[0049] A pixel electrode, a pixel electrode connection region, a conductive channel, and a drain are disposed on the side of the buffer layer away from the substrate and are interconnected; the pixel electrode, the pixel electrode connection region, the conductive channel, and the drain are disposed in the same layer; the conductive channel is located between the drain and the pixel electrode connection region;

[0050] A gate insulating layer is disposed on the side of the conductive channel away from the substrate.

[0051] A gate is disposed on the side of the gate insulating layer away from the substrate;

[0052] The first passivation layer and the second passivation layer are sequentially stacked on the side of the gate away from the substrate;

[0053] The projection of the conductive channel onto the plane of the metal reflective layer is located within the metal reflective layer.

[0054] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a display device, comprising:

[0055] The display panel includes the array substrate described above;

[0056] A backlight module is disposed on one side of the display panel and is used to provide backlight for the display panel.

[0057] The beneficial effects of this application are as follows: Unlike existing technologies, this application discloses an array substrate and its fabrication method, as well as a display device. The fabrication method includes: providing a substrate; depositing a transparent metal oxide conductive layer on the substrate; patterning the transparent metal oxide conductive layer using a first photomask to form a common electrode and a transparent conductive layer spaced apart; reducing the transparent conductive layer using a plasma reducing gas to form a metal reflective layer; sequentially depositing a buffer layer and a transparent metal oxide semiconductor layer; patterning the transparent metal oxide semiconductor layer using a second photomask to form a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; reducing the third semiconductor layer using a plasma reducing gas to form a drain electrode; sequentially depositing an insulating layer and a gate metal layer; patterning the gate metal layer and the insulating layer using a third photomask to form a gate and a gate insulating layer; wherein the gate and gate insulating layer cover a portion of the second semiconductor layer; ion-doping the portion of the second semiconductor layer not covered by the gate and gate insulating layer and the first semiconductor layer to form a pixel electrode and a pixel electrode connection region; and sequentially depositing a first passivation layer and a second passivation layer. The above method solves the problem in existing technologies that it is impossible to improve the brightness of display devices while taking into account both cost and device stability. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0059] Figure 1 This is a schematic flowchart of the method for fabricating the array substrate provided in this application;

[0060] Figure 2 yes Figure 1 A schematic diagram of the structure corresponding to step S1 in the middle section;

[0061] Figure 3 yes Figure 1 A flowchart illustrating step S2;

[0062] Figure 4 yes Figure 3 A schematic diagram of the structure corresponding to step S21;

[0063] Figure 5 yes Figure 3 A schematic diagram of the structure corresponding to step S22;

[0064] Figure 6 yes Figure 3 A schematic diagram of the structure corresponding to step S23;

[0065] Figure 7 yes Figure 1 A flowchart illustrating step S3;

[0066] Figure 8 yes Figure 7 A schematic diagram of the structure corresponding to step S32 in the middle section;

[0067] Figure 9 yes Figure 7 A schematic diagram of the structure corresponding to step S33 in the middle section;

[0068] Figure 10 yes Figure 7 A schematic diagram of the structure corresponding to step S34 in the middle section;

[0069] Figure 11 yes Figure 1 A flowchart illustrating step S4 in the middle section;

[0070] Figure 12 yes Figure 11 A schematic diagram of the structure corresponding to step S41;

[0071] Figure 13 yes Figure 11 A schematic diagram of the structure corresponding to step S42;

[0072] Figure 14 yes Figure 11 A schematic diagram of the structure corresponding to step S43 in the middle section;

[0073] Figure 15 yes Figure 1 A flowchart illustrating step S5 in the middle section;

[0074] Figure 16 yes Figure 15 A schematic diagram of the structure corresponding to step S52 in the middle section;

[0075] Figure 17 yes Figure 15 A schematic diagram of the structure corresponding to step S53 in the middle section;

[0076] Figure 18 yes Figure 15 A schematic diagram of the structure corresponding to step S54 in the middle section;

[0077] Figure 19 yes Figure 1 A flowchart illustrating step S6;

[0078] Figure 20 yes Figure 19 A schematic diagram of the structure corresponding to step S61 in the middle section;

[0079] Figure 21 yes Figure 19A schematic diagram of the structure corresponding to step S62 in the middle section;

[0080] Figure 22 yes Figure 19 A schematic diagram of the structure corresponding to step S63 in the middle section;

[0081] Figure 23 yes Figure 19 A schematic diagram of the structure corresponding to step S64 in the middle section;

[0082] Figure 24 yes Figure 1 A schematic diagram of the structure corresponding to step S7 in the middle section;

[0083] Figure 25 yes Figure 1 A schematic diagram of the structure corresponding to step S8 in the middle section;

[0084] Figure 26 This is a schematic diagram of the display device provided in this application.

[0085] Icon labels:

[0086] Display device 600; backlight module 500; display panel 400; liquid crystal layer 300; color filter substrate 200; array substrate 100; substrate 1; transparent metal oxide conductive layer 2; common electrode 21.

[0087] 22. Transparent conductive layer; 23. Metal reflective layer; X. First photomask; A. Opaque area; B. Semi-transparent area; C. Fully transparent area; 3. First photoresist layer; 31. First photoresist segment; 32. Second photoresist segment; 4. Buffer layer; 5. Transparent metal oxide semiconductor layer; 51. First semiconductor layer; 52. Second semiconductor layer;

[0088] Third semiconductor layer 53; Drain 54; Pixel electrode 55; Pixel electrode connection area 56; Conductive trench 0 57; Second photomask Y; Third photomask Z; Second photoresist layer 6; Third photoresist segment 61;

[0089] Fourth photoresist segment 62; insulating layer 7; gate insulating layer 71; gate metal layer 8; gate 81; third photoresist layer 9; fifth photoresist segment 91; first passivation layer 10; second passivation layer 11. Detailed Implementation

[0090] 5. The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings.

[0091] The embodiments described herein are clearly and completely provided. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0092] The terms "first," "second," and "third" used in the embodiments of this application are for descriptive purposes only.

[0093] This should not be interpreted as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first," "second," or "third" may explicitly or implicitly include at least one of those features. In the description of this application, "multiple" means at least...

[0094] Two, for example, two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example...

[0095] A process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0096] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0097] See Figures 1 to 2 , Figure 1 This is a schematic flowchart of the method for fabricating the array substrate provided in this application. Figure 2 yes Figure 1 A schematic diagram of the structure corresponding to step S1.

[0098] See Figure 1 This application provides a method for fabricating an array substrate 100 to form an array substrate 100 that can be used in a liquid crystal display device. The fabrication method includes:

[0099] S1: Provide a substrate 1, and deposit a transparent metal oxide conductive layer 2 on the substrate 1.

[0100] Specifically, a substrate 1 is first provided. The substrate 1 can be a glass substrate or a transparent substrate of other materials. A transparent metal oxide conductive layer 2 is deposited on one surface of the substrate 1. The material of the transparent metal oxide conductive layer 2 can include one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide, or other materials can be selected. Preferably, the material of the transparent metal oxide conductive layer 2 is transparent indium zinc oxide. The transparent metal oxide conductive layer 2 can be a single-layer structure or a stacked layer of multiple materials. The thickness of the transparent metal oxide conductive layer 2 is in the range of 550-700 μm. The transparent metal oxide conductive layer 2 can be deposited on the substrate 1 using any of the following methods: LPE (liquid phase deposition), MOCVD (metal-organic chemical vapor deposition), HVPE (hydride vapor deposition), and MBE (molecular beam deposition). Alternatively, the transparent metal oxide conductive layer 2 can be formed using methods such as inkjet printing or vapor deposition. After step S1, the following can be obtained: Figure 2 The structure shown.

[0101] See Figures 3 to 6 , Figure 3 yes Figure 1 A flowchart of step S2 is shown. Figure 4 yes Figure 3 The structural diagram corresponding to step S21 is shown below. Figure 5 yes Figure 3 The structural diagram corresponding to step S22 is shown below. Figure 6 yes Figure 3 A schematic diagram of the structure corresponding to step S23.

[0102] S2: The transparent metal oxide conductive layer 2 is patterned using the first photomask X to form a common electrode 21 and a transparent conductive layer 22 that are spaced apart from each other.

[0103] Specifically, step S2, which involves patterning the transparent metal oxide conductive layer 2 using a first photomask X to form a common electrode 21 and a transparent conductive layer 22 spaced apart, includes:

[0104] S21: Deposit a first photoresist layer 3 on the transparent metal oxide conductive layer 2.

[0105] Specifically, a first photoresist layer 3 is deposited on the side of the transparent metal oxide conductive layer 2 away from the substrate 1, wherein the first photoresist layer 3 is a positive photoresist. After step S21, the following can be obtained: Figure 4 The structure shown.

[0106] S22: The first photoresist layer 3 is patterned using the first photomask X to form a first photoresist segment 31 and a second photoresist segment 32 that are spaced apart from each other; the thickness of the first photoresist segment 31 is greater than the thickness of the second photoresist segment 32.

[0107] Specifically, a first photoresist layer 3 is patterned using a first photomask X. The first photomask X includes an opaque region A, a semi-transparent region B, and a fully transparent region C. The opaque region A and the semi-transparent region B are spaced apart, forming spaced first photoresist segments 31 and second photoresist segments 32 in the first photoresist layer 3. The opaque region A corresponds to the first photoresist segment 31, the semi-transparent region B corresponds to the second photoresist segment 32, and the fully transparent region C corresponds to the remaining positions excluding the first and second photoresist segments 31 and 32. The thickness of the first photoresist segment 31 is greater than the thickness of the second photoresist segment 32, wherein the thickness of the first photoresist segment 31 is in the range of 2-4 μm, and the thickness of the second photoresist segment 32 is in the range of 0.5-1.5 μm. The first photomask X can include any one of a grayscale photomask, a halftone photomask, a phase-shifting mask photomask, and a single-slit photomask. Preferably, the first photomask X is a halftone photomask. After step S22, the following can be obtained: Figure 5 The structure shown.

[0108] S23: Using the first photoresist segment 31 and the second photoresist segment 32 as blocking layers, the transparent metal oxide conductive layer 2 is etched to obtain the common electrode 21 corresponding to the first photoresist segment 31 and the transparent conductive layer 22 corresponding to the second photoresist segment 32.

[0109] Specifically, using the first photoresist segment 31 and the second photoresist segment 32 as blocking layers, the transparent metal oxide conductive layer 2 is etched to obtain a common electrode 21 and a transparent conductive layer 22 spaced apart from each other. The common electrode 21 corresponds to the position of the first photoresist segment 31, and the transparent conductive layer 22 corresponds to the position of the second photoresist segment 32. The common electrode 21 and the transparent conductive layer 22 are disposed in the same layer. After step S23, the following can be obtained: Figure 6 The structure shown.

[0110] See Figures 7 to 10 , Figure 7 yes Figure 1 A flowchart illustrating step S3. Figure 8 yes Figure 7 A schematic diagram of the structure corresponding to step S32. Figure 9 yes Figure 7 A schematic diagram of the structure corresponding to step S33. Figure 10 yes Figure 7 A schematic diagram of the structure corresponding to step S34.

[0111] S3: The transparent conductive layer 22 is reduced by plasma reducing gas to form a metallic reflective layer 23.

[0112] Specifically, step S3, which involves using a plasma reducing gas to reduce the transparent conductive layer 22 to form the metallic reflective layer 23, includes:

[0113] S31: Ashing process is performed on the first photoresist segment 31 and the second photoresist segment 32.

[0114] S32: While thinning the first photoresist segment 31, remove the second photoresist segment 32 to expose the transparent conductive layer 22.

[0115] Specifically, since the thickness of the first photoresist segment 31 is greater than the thickness of the second photoresist segment 32, the second photoresist segment 32 is removed while the first photoresist segment 31 is thinned until the transparent conductive layer 22 covered by the second photoresist segment 32 is exposed. After step S32, the following can be obtained: Figure 8 The structure shown.

[0116] S33: Using the first photoresist segment 31 as a blocking layer, the transparent conductive layer 22 is reduced by plasma reducing gas to form a metallic reflective layer 23.

[0117] Specifically, using the first photoresist segment 31 as a blocking layer, the common electrode 21 located below the first photoresist segment 31 is blocked. A plasma reducing gas is used to reduce the exposed transparent conductive layer 22, so that the transparent conductive layer 22 forms a metallic reflective layer 23 after reduction by the plasma reducing gas. The plasma reducing gas can include any one of hydrogen and carbon monoxide, or other plasma reducing gases; preferably, the plasma reducing gas is hydrogen. Step S33 can obtain... Figure 9 The structure shown.

[0118] S34: Remove the first photoresist segment 31 to expose the common electrode 21.

[0119] Specifically, the first photoresist segment 31 located above the common electrode 21 is removed, exposing the common electrode 21. After step S34, the following can be obtained: Figure 10 The structure shown.

[0120] It is understood that in this embodiment, gas reduction technology is used to directly generate the metal reflective layer 23 by reducing the transparent conductive layer 22 with plasma reducing gas. There is no need to separately deposit a film layer for forming the metal reflective layer 23. Both the metal reflective layer 23 and the common electrode 21 are formed from the transparent metal oxide conductive layer 2, and are disposed in the same layer. That is, using gas reduction technology, only one layer of transparent metal oxide conductive layer 2 needs to be deposited on the substrate 1, and the first photomask X is used to prepare the metal reflective layer 23 and the common electrode 21, saving steps and effectively reducing costs. Simultaneously, the metal reflective layer 23 can reflect light incident upon it, which is beneficial for the array substrate 100 formed subsequently to reflect some light when applied to the display panel, preventing light from hitting the conductive channel 57 of the TFT and affecting the array substrate 100, thereby improving the electrical stability of the device. Furthermore, the reflected light can be reused, which helps improve light utilization.

[0121] See Figures 11 to 14 , Figure 11 yes Figure 1 A flowchart illustrating step S4. Figure 12 yes Figure 11 The structural diagram corresponding to step S41 is shown below. Figure 13 yes Figure 11 A schematic diagram of the structure corresponding to step S42. Figure 14 yes Figure 11 A schematic diagram of the structure corresponding to step S43.

[0122] S4: Sequentially deposit a buffer layer 4 and a transparent metal oxide semiconductor layer 5; use a second photomask Y to pattern the transparent metal oxide semiconductor layer 5 to form a first semiconductor layer 51, a second semiconductor layer 52 and a third semiconductor layer 53.

[0123] Specifically, firstly, the result obtained in step S3 Figure 10In the structure shown, a buffer layer 4 and a transparent metal oxide semiconductor layer 5 are deposited sequentially, such that the buffer layer 4 and the transparent metal oxide semiconductor layer 5 cover the common electrode 21, the metal reflective layer 23, and the substrate 1. The buffer layer 4 can be made of a high-transmittance insulating material, and the transparent metal oxide semiconductor layer 5 can be made of, but is not limited to, amorphous indium gallium zinc oxide. Preferably, the transparent metal oxide semiconductor layer 5 is made of amorphous indium gallium zinc oxide, and its thickness is 400-1700 μm. The buffer layer 4 and the transparent metal oxide semiconductor layer 5 can be deposited using any of the following methods: LPE (liquid phase deposition), MOCVD (metal-organic chemical vapor deposition), HVPE (hydride vapor deposition), and MBE (molecular beam deposition). Alternatively, inkjet printing or vapor deposition can be used to form the buffer layer 4 and the transparent metal oxide semiconductor layer 5. It is understood that depositing the buffer layer 4 can prevent short circuits caused by contact between different conductive layers of the array substrate 100, thereby improving the performance of the array substrate 100.

[0124] The step S4, which involves patterning the transparent metal-oxide semiconductor layer 5 using a second photomask Y to form the first semiconductor layer 51, the second semiconductor layer 52, and the third semiconductor layer 53, specifically includes:

[0125] S41: Deposit a second photoresist layer 6 on the transparent metal oxide semiconductor layer 5.

[0126] Specifically, a second photoresist layer 6 is deposited on the side of the transparent metal oxide semiconductor layer 5 away from the substrate 1. The second photoresist layer 6 is a positive photoresist. Through step S41, the following can be obtained: Figure 12 The structure shown.

[0127] S42: The second photoresist layer 6 is patterned using a second photomask Y to form a third photoresist segment 61 and a fourth photoresist segment 62; the thickness of the third photoresist segment 61 is greater than the thickness of the fourth photoresist segment 62.

[0128] Specifically, a second photomask Y is used to pattern the second photoresist layer 6. The second photomask Y includes an opaque region A, a semi-transparent region B, and a fully transparent region C. The opaque region A and the semi-transparent region B are arranged adjacent to each other, forming a third photoresist segment 61 and a fourth photoresist segment 62 in the second photoresist layer 6. The third photoresist segment 61 and the fourth photoresist segment 62 are arranged adjacent to each other. The opaque region A corresponds to the third photoresist segment 61, the semi-transparent region B corresponds to the fourth photoresist segment 62, and the fully transparent region C corresponds to the remaining positions excluding the third and fourth photoresist segments 61 and 62. The thickness of the third photoresist segment 61 is greater than the thickness of the fourth photoresist segment 62, with the thickness of the third photoresist segment 61 ranging from 2 to 4 μm, and the thickness of the fourth photoresist segment 62 ranging from 0.5 to 1.5 μm. The second photomask Y can include any one of a grayscale photomask, a halftone photomask, a phase-shifting mask, and a single-slit photomask. Preferably, the second photomask Y is a halftone photomask. After step S42, the following can be obtained: Figure 13 The structure shown.

[0129] S43: Using the third photoresist segment 61 and the fourth photoresist segment 62 as blocking layers, the transparent metal oxide semiconductor layer 5 is etched to obtain the first semiconductor layer 51 and the second semiconductor layer 52 corresponding to the third photoresist segment 61, and the third semiconductor layer 53 corresponding to the fourth photoresist segment 62.

[0130] Specifically, using the third photoresist segment 61 and the fourth photoresist segment 62 as blocking layers, the transparent metal oxide semiconductor layer 5 is etched to obtain a first semiconductor layer 51, a second semiconductor layer 52, and a third semiconductor layer 53. The first semiconductor layer 51 and the second semiconductor layer 52 are positioned below the third photoresist segment 61, the third semiconductor layer 53 is positioned below the fourth photoresist segment 62, and the second semiconductor layer 52 is located between the first semiconductor layer 51 and the third semiconductor layer 53. The first semiconductor layer 51 has the shape of a pixel electrode 55, the second semiconductor layer 52 has the shape of a pixel electrode connection region 56, and the third semiconductor layer 53 has the shape of a drain electrode 54. After step S43, the following can be obtained: Figure 14 The structure shown.

[0131] See Figures 15 to 18 , Figure 15 yes Figure 1 A flowchart illustrating step S5. Figure 16 yes Figure 15 A schematic diagram of the structure corresponding to step S52. Figure 17 yes Figure 15 A schematic diagram of the structure corresponding to step S53. Figure 18 yes Figure 15 A schematic diagram of the structure corresponding to step S54.

[0132] S5: The third semiconductor layer 53 is reduced using a plasma reducing gas to form a drain electrode 54.

[0133] Specifically, step S5, which involves reducing the third semiconductor layer 53 with a plasma reducing gas to form the drain electrode 54, includes:

[0134] S51: Ashing process is performed on the third photoresist segment 61 and the fourth photoresist segment 62.

[0135] S52: While thinning the third photoresist segment 61, remove the fourth photoresist segment 62 to expose the third semiconductor layer 53.

[0136] Specifically, since the thickness of the third photoresist segment 61 is greater than the thickness of the fourth photoresist segment 62, the fourth photoresist segment 62 is removed while the third photoresist segment 61 is thinned, until the third semiconductor layer 53 covered by the fourth photoresist segment 62 is exposed. After step S52, the following can be obtained: Figure 16 The structure shown.

[0137] S53: Using the third photoresist segment 61 as a barrier layer, the third semiconductor layer 53 is reduced by plasma reducing gas to form the drain electrode 54.

[0138] Specifically, using the third photoresist segment 61 as a blocking layer, the first semiconductor layer 51 and the second semiconductor layer 52 located below the third photoresist segment 61 are blocked. A plasma reducing gas is used to reduce the exposed third semiconductor layer 53, forming a conductive drain 54 under the reducing action of the plasma reducing gas. The plasma reducing gas can include any one of hydrogen and carbon monoxide, or other plasma reducing gases; preferably, hydrogen is used. Step S53 yields the following... Figure 17 The structure shown.

[0139] S54: Remove the third photoresist segment 61 to expose the first semiconductor layer 51 and the second semiconductor layer 52.

[0140] Specifically, the third photoresist segment 61 located on the side of the first semiconductor layer 51 and the second semiconductor layer 52 away from the substrate 1 is removed, exposing the first semiconductor layer 51 and the second semiconductor layer 52. After step S54, the following can be obtained: Figure 18 The structure shown.

[0141] It is understood that in this embodiment, gas reduction technology is used to reduce the third semiconductor layer 53 to form the drain 54 by plasma reducing gas, eliminating the need to separately deposit a drain metal layer to form the drain 54, thus saving process steps and costs.

[0142] See Figures 19 to 23 , Figure 19 yes Figure 1 A flowchart of step S6 is shown. Figure 20 yes Figure 19 The structural diagram corresponding to step S61 is shown below. Figure 21 yes Figure 19 The structural diagram corresponding to step S62 is shown below. Figure 22 yes Figure 19 A schematic diagram of the structure corresponding to step S63. Figure 23 yes Figure 19 A schematic diagram of the structure corresponding to step S64.

[0143] S6: Sequentially deposit insulating layer 7 and gate metal layer 8; use third photomask Z to pattern gate metal layer 8 and insulating layer 7 to form gate 81 and gate insulating layer 71; wherein, gate 81 and gate insulating layer 71 cover part of second semiconductor layer 52.

[0144] Specifically, an insulating layer 7 and a gate metal layer 8 are sequentially deposited on the side of the first semiconductor layer 51 and the second semiconductor layer 52 away from the substrate 1. The insulating layer 7 and the gate metal layer 8 cover the first semiconductor layer 51, the second semiconductor layer 52, and the buffer layer 4. The insulating layer 7 and the gate metal layer 8 can be deposited using any of the following methods: liquid phase deposition, metal-organic chemical vapor deposition, hydride vapor deposition, and molecular beam deposition. Alternatively, the insulating layer 7 and the gate metal layer 8 can be formed using methods such as inkjet printing or vapor deposition.

[0145] The step S6, which involves patterning the gate metal layer 8 and the insulating layer 7 using a third photomask Z to form the gate 81 and the gate insulating layer 71, includes:

[0146] S61: Deposit a third photoresist layer 9 on the gate metal layer 8.

[0147] Specifically, a third photoresist layer 9 is deposited on the side of the gate metal layer 8 away from the substrate 1. The third photoresist layer 9 is a positive photoresist. After step S61, the following can be obtained: Figure 20 The structure shown.

[0148] S62: The third photoresist layer 9 is patterned using the third photomask Z to form the fifth photoresist segment 91.

[0149] Specifically, a third photomask Z is used to pattern the third photoresist layer 9. The third photomask Z includes only an opaque area A and a fully transparent area C, so that the third photoresist layer 9 forms a fifth photoresist segment 91. The fifth photoresist segment 91 corresponds to the position of the opaque area A, and the fully transparent area C corresponds to the remaining positions excluding the fifth photoresist segment 91. The thickness of the fifth photoresist segment 91 is in the range of 0.5-1.5 μm. The third photomask Z can include any one of a grayscale photomask, a halftone photomask, a phase-shifting mask, and a single-slit photomask. After step S62, the following can be obtained: Figure 21 The structure shown.

[0150] S63: Using the fifth photoresist segment 91 as a blocking layer, the gate metal layer 8 and the insulating layer 7 are etched to obtain the gate 81 and the gate insulating layer 71 corresponding to the fifth photoresist segment 91.

[0151] Specifically, using the fifth photoresist segment 91 as a blocking layer, the stacked insulating layer 7 and gate metal layer 8 are etched away, removing the portions of the insulating layer 7 and gate metal layer 8 except those covered by the fifth photoresist segment 91, to obtain the gate 81 and gate insulating layer 71 corresponding to the area below the fifth photoresist segment 91. After step S63, the following can be obtained: Figure 22 The structure shown.

[0152] S64: Remove the fifth photoresist segment 91 to expose the gate 81.

[0153] Specifically, the fifth photoresist segment 91 located on the side of the gate 81 away from the substrate 1 is removed, exposing the gate 81. After step S64, the following can be obtained: Figure 23 The structure shown.

[0154] See Figures 24 to 25 , Figure 24 yes Figure 1 A schematic diagram of the structure corresponding to step S7. Figure 25 yes Figure 1 A schematic diagram of the structure corresponding to step S8.

[0155] S7: Ion doping is performed on the portion of the second semiconductor layer 52 and the first semiconductor layer 51 that is not covered by the gate 81 and the gate insulating layer 71 to form the pixel electrode 55 and the pixel electrode connection region 56.

[0156] Specifically, after step S6, the gate 81 and the gate insulating layer 71 cover a portion of the second semiconductor layer 52, while the first semiconductor layer 51 and another portion of the second semiconductor layer 52 are not covered by the gate 81 and the gate insulating layer 71. Ion doping is then performed on the first semiconductor layer 51 and the portion of the second semiconductor layer 52 that are not covered by the gate 81 and the gate insulating layer 71. The ion doping can be performed by plasma doping, and the plasma doping gas can include any one of hydrogen, ammonia, and argon, or other plasma gases can be used for ion doping.

[0157] After ion doping, the first semiconductor layer 51 and a portion of the second semiconductor layer 52 are transformed from transparent metal oxide semiconductors to transparent metal oxide conductors. The first semiconductor layer 51 forms the pixel electrode 55, and the portion of the second semiconductor layer 52 not covered by the gate 81 and the gate insulating layer 71 forms the pixel electrode connection region 56. The pixel electrode 55 and the pixel electrode connection region 56 are interconnected, eliminating the need for a source electrode, thus simplifying the process and reducing production costs. The portion of the second semiconductor layer 52 covered by the gate 81 and the gate insulating layer 71, i.e., the undoped portion, forms a conductive channel 57. The conductive channel 57 is located directly above the metal reflective layer 23, and its projection onto the plane of the metal reflective layer 23 lies within the metal reflective layer 23. After step S7, the following can be obtained: Figure 24 The structure shown.

[0158] It is understood that in this embodiment, the gate 81 is formed above the conductive channel 57, and the TFT is a top-gate coplanar TFT, which can reduce the size of parasitic capacitance and is more conducive to device miniaturization. The gate 81 and the gate insulating layer 71 are formed using the third photomask Z, and the conductive channel 57, the pixel electrode 55, and the pixel electrode connection area 56 are formed using the second photomask Y. That is, the gate 81 and the gate insulating layer 71 are formed with the conductive channel 57 using two different photomasks, and the gate 81 and the gate insulating layer 71 have different shapes and are two different patterns with the conductive channel 57, which can avoid leakage.

[0159] S8: Sequentially deposit the first passivation layer 10 and the second passivation layer 11.

[0160] Specifically, a first passivation layer 10 and a second passivation layer 11 are sequentially deposited on the side of the gate 81 away from the substrate 1. The materials of the first passivation layer 10 and the second passivation layer 11 can be the same. The material of the first passivation layer 10 can include any one of silicon oxide and silicon nitride, or both silicon oxide and silicon nitride. Depositing the passivation layer can also prevent short circuits caused by contact between different conductive layers of the array substrate 100. After step S8, the following can be obtained: Figure 25 The structure shown, Figure 25 The structure shown is the final structure formed by the fabrication method of the array substrate 100 provided in this application.

[0161] The array substrate 100 prepared by the method provided in this embodiment has a metal reflective layer 23 disposed directly below the conductive channel 57. When the array substrate 100 is applied to the display panel 400, the metal reflective layer 23 can reflect the light from the backlight module 500 illuminating the top gate of the TFT back to the backlight module 500, avoiding the problem of light affecting the electrical stability of the TFT at the location of the conductive channel 57, thus improving the stability of the device. At the same time, the light reflected by the metal reflective layer 23 is reflected again by the reflector of the backlight module 500 and re-emitted at another angle back to the display panel 400 for reuse, which helps to reduce light loss, improve light utilization, and thus improve the display brightness of the display device 600 and avoid energy waste. In addition, in this embodiment, only three photomasks are used to prepare the array substrate 100, which reduces the number of photomasks used, saves processes, and effectively reduces production costs. The method for fabricating the array substrate 100 provided in this application can effectively solve the problem in the prior art that it is impossible to improve the brightness of the display device 600 while taking into account both cost and device stability.

[0162] See Figure 26 , Figure 26 This is a schematic diagram of the display device provided in this application.

[0163] This application also provides a display device 600, which includes a display panel 400 and a backlight module 500. The backlight module 500 is disposed on one side of the display panel 400 and is used to provide backlight for the display panel 400. In one embodiment, the display panel 400 can be a liquid crystal display panel, such as... Figure 26 As shown, the display panel 400 includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The color filter substrate 200 is disposed opposite to the array substrate 100, and the liquid crystal layer 300 is sandwiched between the array substrate 100 and the color filter substrate 200.

[0164] Wherein, the array substrate 100 is an array substrate 100 prepared by the above-described method for preparing an array substrate 100, and its structure is similar to... Figure 25 The array substrate 100 has the same structure as shown, including a substrate 1, a common electrode 21 and a metal reflective layer 23, a buffer layer 4, a pixel electrode 55, a pixel electrode connection area 56, a conductive channel 57 and a drain 54, a gate insulating layer 71, a gate 81, a first passivation layer 10 and a second passivation layer 11.

[0165] Specifically, substrate 1 can be a glass substrate or a transparent substrate of other materials. The common electrode 21 and the metal reflective layer 23 are disposed alternately on one side of substrate 1, and the common electrode 21 and the metal reflective layer 23 are disposed in the same layer. The metal reflective layer 23 can reflect the light that shines on it. The buffer layer 4 is disposed on the side of the common electrode 21 and the metal reflective layer 23 away from substrate 1, covering the common electrode 21, the metal reflective layer 23 and the substrate 1. The material of the buffer layer 4 can be an insulating material with high light transmittance.

[0166] Pixel electrode 55, pixel electrode connection area 56, conductive channel 57 and drain 54 are disposed on the side of substrate 1 away from buffer layer 4. Pixel electrode 55, pixel electrode connection area 56, conductive channel 57 and drain 54 are disposed in the same layer and interconnected. Conductive channel 57 is located between drain 54 and pixel electrode connection area 56. The interconnection between pixel electrode 55 and pixel electrode connection area 56 eliminates the need for a source electrode, which simplifies the process and reduces production costs.

[0167] A gate insulating layer 71 is disposed on the side of the conductive channel 57 away from the substrate 1, and the gate insulating layer 71 is positioned corresponding to the conductive channel 57. A gate 81 is disposed on the side of the gate insulating layer 71 away from the substrate 1, and is positioned corresponding to the gate insulating layer 71 and the conductive channel 57. The gate insulating layer 71 and the gate 81 have the same shape. The conductive channel 57, the gate insulating layer 71, and the gate 81 are respectively disposed above the metal reflective layer 23. The cross-sectional area of ​​the metal reflective layer 23 is larger than the cross-sectional area of ​​the conductive channel 57 and the gate 81. The projection of the conductive channel 57 onto the plane of the metal reflective layer 23 is located within the metal reflective layer 23.

[0168] The first passivation layer 10 and the second passivation layer 11 are stacked sequentially on the side of the gate 81 away from the substrate 1. It can be understood that by setting the buffer layer 4 and the first passivation layer 10 and the second passivation layer 11, the problem of short circuit of the device caused by contact between different conductive layers can be avoided.

[0169] See Figure 26Because a metal reflective layer 23 is disposed below the conductive channel 57 of the array substrate 100, and the cross-sectional area of ​​the metal reflective layer 23 is larger than the cross-sectional area of ​​the conductive channel 57, when the light emitted by the backlight module 500 shines on the location of the TFT gate 81 and the conductive channel 57, this part of the light is reflected by the metal reflective layer 23 of the array substrate 100 and will not shine on the conductive channel 57 and the gate 81. This effectively avoids the problem of the light from the backlight module 500 directly shining on the location of the gate 81 and the conductive channel 57, affecting the electrical stability of the array substrate 100. At the same time, the light is reflected by the metal reflective layer 23. The reflected light 23 shines on the backlight module 500, and is reflected again by the reflector plate (not shown) of the backlight module 500, and shines on the array substrate 100 of the display panel 400 at another angle, thus being reused. This reduces light loss, improves light utilization, and thus improves the brightness of the display device 600, avoiding energy waste. Without increasing the light intensity of the backlight module 500 or adjusting the overall pixel structure design, the brightness of the display device 600 is improved, solving the problem in the prior art that it is impossible to improve the brightness of the display device 600 while taking into account cost and ensuring device stability.

[0170] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for fabricating an array substrate, used to fabricate an array substrate for use in a liquid crystal display device, characterized in that, include: A substrate is provided, on which a transparent metal oxide conductive layer is deposited; The transparent metal oxide conductive layer is patterned using a first photomask to form a common electrode and a transparent conductive layer spaced apart from each other; The transparent conductive layer is reduced using a plasma reducing gas to form a metallic reflective layer; wherein the common electrode and the metallic reflective layer are disposed in the same layer and spaced apart from each other; A buffer layer and a transparent metal oxide semiconductor layer are deposited sequentially; the transparent metal oxide semiconductor layer is patterned using a second photomask to form a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The third semiconductor layer is reduced using a plasma reducing gas to form a drain electrode; An insulating layer and a gate metal layer are deposited sequentially; the gate metal layer and the insulating layer are patterned using a third photomask to form a gate and a gate insulating layer; wherein the gate and the gate insulating layer cover a portion of the second semiconductor layer; The portion of the second semiconductor layer not covered by the gate and the gate insulating layer is ion-doped with the first semiconductor layer to form a pixel electrode and a pixel electrode connection region; wherein the pixel electrode, the pixel electrode connection region and the drain are disposed on the same layer; The first passivation layer and the second passivation layer are deposited sequentially.

2. The preparation method according to claim 1, characterized in that, The step of patterning the transparent metal oxide conductive layer using a first photomask to form mutually spaced common electrodes and a transparent conductive layer includes: A first photoresist layer is deposited on the transparent metal oxide conductive layer; The first photoresist layer is patterned using a first photomask to form a first photoresist segment and a second photoresist segment spaced apart from each other; the thickness of the first photoresist segment is greater than the thickness of the second photoresist segment. Using the first photoresist segment and the second photoresist segment as blocking layers, the transparent metal oxide conductive layer is etched to obtain the common electrode corresponding to the first photoresist segment and the transparent conductive layer corresponding to the second photoresist segment.

3. The preparation method according to claim 2, characterized in that, The step of reducing the transparent conductive layer with a plasma reducing gas to form a metallic reflective layer includes: The first and second photoresist segments are subjected to ashing treatment; While thinning the first photoresist segment, the second photoresist segment is removed to expose the transparent conductive layer; Using the first photoresist segment as a blocking layer, the transparent conductive layer is reduced by plasma reducing gas to form the metallic reflective layer; Remove the first photoresist segment to expose the common electrode.

4. The preparation method according to claim 2, characterized in that, The first photoresist layer is a positive photoresist; the thickness of the first photoresist segment is 2-4 μm, and the thickness of the second photoresist segment is 0.5-1.5 μm; the first photomask includes an opaque area corresponding to the first photoresist segment, a semi-transparent area corresponding to the second photoresist segment, and a fully transparent area corresponding to the remaining positions.

5. The preparation method according to claim 1, characterized in that, The step of patterning the transparent metal oxide semiconductor layer using a second photomask to form the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes: A second photoresist layer is deposited on the transparent metal oxide semiconductor layer; The second photoresist layer is patterned using a second photomask to form a third photoresist segment and a fourth photoresist segment; the thickness of the third photoresist segment is greater than the thickness of the fourth photoresist segment. Using the third and fourth photoresist segments as blocking layers, the transparent metal oxide semiconductor layer is etched to obtain the first semiconductor layer and the second semiconductor layer corresponding to the third photoresist segment, and the third semiconductor layer corresponding to the fourth photoresist segment.

6. The preparation method according to claim 5, characterized in that, The step of reducing the third semiconductor layer with a plasma reducing gas to form the drain includes: The third and fourth photoresist segments are subjected to ashing treatment; While thinning the third photoresist segment, the fourth photoresist segment is removed to expose the third semiconductor layer; Using the third photoresist segment as a barrier layer, the third semiconductor layer is reduced by plasma reducing gas to form the drain electrode; Remove the third photoresist segment to expose the first semiconductor layer and the second semiconductor layer.

7. The preparation method according to claim 5, characterized in that, The second photoresist layer is a positive photoresist; the thickness of the third photoresist segment is 2-4 μm, and the thickness of the fourth photoresist segment is 0.5-1.5 μm; the second photomask includes an opaque area corresponding to the third photoresist segment, a semi-transparent area corresponding to the fourth photoresist segment, and a fully transparent area corresponding to the remaining positions.

8. The preparation method according to claim 1, characterized in that, The step of patterning the gate metal layer and the insulating layer using a third photomask to form the gate and the gate insulating layer includes: A third photoresist layer is deposited on the gate metal layer; The third photoresist layer is patterned using a third photomask to form the fifth photoresist segment; Using the fifth photoresist segment as a blocking layer, the gate metal layer and the insulating layer are etched to obtain the gate and gate insulating layer corresponding to the fifth photoresist segment; Remove the fifth photoresist segment to expose the gate.

9. The preparation method according to claim 8, characterized in that, The third photoresist layer is a positive photoresist; the thickness of the fifth photoresist segment is 0.5-1.5μm; the third photomask includes an opaque area corresponding to the fifth photoresist segment and a fully transparent area corresponding to the remaining positions.

10. The preparation method according to claim 1, characterized in that, The portion of the second semiconductor layer covered by the gate and the gate insulating layer forms a conductive channel; The transparent metal oxide conductive layer is made of one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; the thickness of the transparent metal oxide conductive layer is 550-700 μm; the plasma reducing gas includes any one of hydrogen and carbon monoxide; the transparent metal oxide semiconductor layer is made of amorphous indium gallium zinc oxide; the thickness of the transparent metal oxide semiconductor layer is 400-1700 μm; The first, second, and third photomasks include any one of grayscale photomasks, halftone photomasks, phase-shifting mask photomasks, and single-slit photomasks. The ion doping method is plasma doping; the plasma doping gas includes any one of hydrogen, ammonia, and argon.

11. An array substrate prepared by the preparation method according to any one of claims 1-10, characterized in that, include: substrate; A common electrode and a metal reflective layer are disposed on one side of the substrate; the common electrode and the metal reflective layer are disposed in the same layer and spaced apart from each other; the common electrode and the metal reflective layer are formed from the same transparent metal oxide conductive layer; A buffer layer is disposed on the side of the common electrode and the metal reflective layer away from the substrate; A pixel electrode, a pixel electrode connection region, a conductive channel, and a drain are disposed on the side of the buffer layer away from the substrate and are interconnected; the pixel electrode, the pixel electrode connection region, the conductive channel, and the drain are disposed in the same layer; the conductive channel is located between the drain and the pixel electrode connection region; the pixel electrode, the pixel electrode connection region, and the drain are formed from the same transparent metal oxide semiconductor layer; A gate insulating layer is disposed on the side of the conductive channel away from the substrate. A gate is disposed on the side of the gate insulating layer away from the substrate; The first passivation layer and the second passivation layer are sequentially stacked on the side of the gate away from the substrate; The projection of the conductive channel onto the plane of the metal reflective layer is located within the metal reflective layer.

12. A display device, characterized in that, include: The display panel includes the array substrate as described in claim 11; A backlight module is disposed on one side of the display panel and is used to provide backlight for the display panel.

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