A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: forming a plurality of spaced pads on a base structure; forming a dielectric layer on the base structure, the dielectric layer comprising a first dielectric region and a second dielectric region surrounding the first dielectric region, the first dielectric region having a plurality of spaced openings penetrating the first dielectric region, the openings exposing the pads, and the thickness of the first dielectric region around the openings being smaller than the thickness of the second dielectric region; and forming a redistribution layer on the inner wall surface of the openings and the top surface of the first dielectric region. The preparation method can improve the problem of poor electrical connection between the redistribution layer and the pads.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Current advanced semiconductor packaging typically requires sequential processes for a dielectric layer and a re-distribution layer (RDL). The dielectric layer process includes: dielectric layer photolithography and etching to create a patterned dielectric layer. The re-distribution layer process includes: re-distribution layer photolithography, re-distribution layer metal deposition, and removal of photoresist and the re-distribution layer metal on the photoresist to create a patterned re-distribution layer. If the dielectric layer opening size is small, subsequent re-distribution layer photolithography may encounter poor development, leaving residual photoresist. This can lead to poor or even non-existent bonding between the re-distribution layer's metal pads and the chip's metal pads. This problem is particularly severe when two or more dielectric layers exist, especially when the dielectric layer openings have different depths. Summary of the Invention

[0003] The technical problem to be solved by this invention is how to improve the poor connection between the redistribution layer and the pad.

[0004] This invention provides a method for fabricating a semiconductor structure, comprising the following steps: providing a basic structure; forming a plurality of spaced pads on the basic structure; forming a dielectric layer on the basic structure, the dielectric layer comprising a first dielectric region and a second dielectric region surrounding the first dielectric region, the first dielectric region having a plurality of spaced openings penetrating the first dielectric region, the openings exposing the pads, the thickness of the first dielectric region surrounding the openings being less than the thickness of the second dielectric region; and forming a redistribution layer on the inner wall surface of the openings and the top surface of the first dielectric region.

[0005] Optionally, the step of forming the dielectric layer includes: forming an initial dielectric layer covering the pads on the base structure; forming a first photoresist layer on the initial dielectric layer, wherein the first photoresist layer is a positive photoresist; providing a mask, the mask including a second mask region, a third mask region, and a plurality of spaced first mask regions, wherein the second mask regions surround the plurality of spaced first mask regions, the third mask regions surround the second mask regions, and the transmittance of the second mask regions is greater than the transmittance of the third mask regions and less than the transmittance of the first mask regions; exposing the first photoresist layer using the mask; after the exposure process, developing the first photoresist layer; after the development process, etching the initial dielectric layer using the first photoresist layer as a mask, thereby forming the dielectric layer from the initial dielectric layer.

[0006] Optionally, the transmittance of the first mask area is 90% to 100%; the transmittance of the second mask area is 50% to 80%; and the transmittance of the third mask area is 0% to 5%.

[0007] Optionally, the transmittance of the first mask area is 100%; the transmittance of the second mask area is 50%; and the transmittance of the third mask area is 0%.

[0008] Optionally, the second mask region includes a mask connecting region and a plurality of mask surrounding regions, the mask surrounding regions surrounding the first mask region, and the mask connecting region connecting at least two mask surrounding regions.

[0009] Optionally, the angle between the top surface of the first medium region and the sidewall surface of the second medium region facing the first medium region is 110° to 150°; the angle between the top surface of the first medium region around the opening and the sidewall surface of the opening is 110° to 150°.

[0010] Optionally, the top surface of the redistribution layer on the first dielectric region around the opening is flush with the top surface of the second dielectric region.

[0011] The present invention also provides a semiconductor structure, comprising: a base structure; a plurality of spaced pads located on the base structure; a dielectric layer located on the base structure, the dielectric layer comprising a first dielectric region and a second dielectric region surrounding the first dielectric region, the first dielectric region having a plurality of spaced openings penetrating the first dielectric region, the openings being located on the pads, the thickness of the first dielectric region surrounding the openings being less than the thickness of the second dielectric region; and a redistribution layer located on the inner wall surface of the openings and the top surface of the first dielectric region, the redistribution layer being electrically connected to the pads.

[0012] Optionally, the second medium region includes a medium connection region and a plurality of medium surrounding regions, the medium surrounding regions surrounding the first medium region, and the medium connection region connecting at least two medium surrounding regions.

[0013] Optionally, the angle between the top surface of the first medium region and the sidewall surface of the second medium region facing the first medium region is 110° to 150°; the angle between the top surface of the first medium region around the opening and the sidewall surface of the opening is 110° to 150°.

[0014] Optionally, the top surface of the redistribution layer on the first dielectric region around the opening is flush with the top surface of the second dielectric region.

[0015] The technical solution of the present invention has the following beneficial effects:

[0016] The semiconductor structure fabrication method provided by the present invention reduces the slope of the sidewall of the opening and the top surface of the first dielectric region by less than the thickness of the second dielectric region. This reduces the longitudinal distance between the top surface of the pad and the top surface of the first dielectric region, which facilitates the patterning of the redistribution layer and avoids the formation of by-product residues during the process of defining the pattern of the redistribution layer, thus ensuring good contact between the redistribution layer and the pad.

[0017] Secondly, the thickness of the first dielectric region is less than that of the second dielectric region, and the top surface of the first dielectric region is lower than that of the second dielectric region. This reduces the height of the top surface of the redistribution layer, decreases the distance between the top surface of the redistribution layer and the top surface of the second dielectric region around the opening, and prevents the redistribution layer from being excessively recessed within the opening, providing a flatter surface for subsequent processes. Thirdly, the reduced distance between the top surface of the redistribution layer and the top surface of the second dielectric region reduces the overall thickness of the semiconductor structure, thus reducing warpage. A flatter surface and lower warpage reduce the risk of development defects in subsequent patterning processes. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a mask plate according to an embodiment of this application;

[0020] Figures 2 to 3 This is a schematic diagram of the process of forming a semiconductor structure according to an embodiment of this application;

[0021] Figure label:

[0022] 1. Basic structure; 11. Pads; 2. Dielectric layer; 21. First dielectric region; 22. Second dielectric region; 3. Redistribution layer; 41. First mask region; 42. Second mask region; 421. Mask connection region; 422. Mask surrounding region; 43. Third mask region. Detailed Implementation

[0023] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] Example 1

[0025] This embodiment provides a method for fabricating a semiconductor structure, including the following steps: (Refer to...) Figure 2 A basic structure 1 is provided; a plurality of spaced pads 11 are formed on the basic structure 1; a dielectric layer 2 is formed on the basic structure 1, the dielectric layer 2 including a first dielectric region 21 and a second dielectric region 22 surrounding the first dielectric region 21, the first dielectric region 21 having a plurality of spaced openings penetrating the first dielectric region 21, the openings exposing the pads 11, the thickness of the first dielectric region 21 around the openings being less than the thickness of the second dielectric region 22; Reference Figure 3 A redistribution layer 3 is formed on the inner wall surface of the opening and the top surface of the first dielectric region 21.

[0026] The basic structure in this embodiment can be a single semiconductor chip or multiple different types of semiconductor chips packaged together. As long as it is a basic structure that needs to improve the functional density of semiconductor chips, shorten interconnect length, or reconfigure the system through a redistribution layer.

[0027] In this embodiment, since the thickness of the first dielectric region 21 around the opening is less than the thickness of the second dielectric region 22, the slope between the sidewall of the opening and the top surface of the first dielectric region 21 is reduced, and the longitudinal distance between the top surface of the pad 11 and the top surface of the first dielectric region 21 is reduced. This facilitates the patterning of the redistribution layer 3, avoids the formation of by-product residues during the process of defining the pattern of the redistribution layer 3, and ensures good contact between the redistribution layer 3 and the pad 11.

[0028] Secondly, the thickness of the first dielectric region 21 is less than the thickness of the second dielectric region 22, and the top surface of the first dielectric region 21 is lower than the top surface of the second dielectric region 22. This reduces the height of the top surface of the redistribution layer 3, decreases the distance between the top surface of the redistribution layer 3 and the top surface of the second dielectric region 22 around the opening, and prevents the redistribution layer 3 from being excessively recessed in the opening, providing a flatter surface for subsequent processes. Furthermore, the reduced distance between the top surface of the redistribution layer 3 and the top surface of the second dielectric region 22 reduces the overall thickness of the semiconductor structure, thus reducing the warpage of the semiconductor structure. A flatter surface and lower warpage reduce the risk of poor development in subsequent patterning processes.

[0029] In one embodiment, the top surface of the redistribution layer 3 on the first dielectric region 21 around the opening is flush with the top surface of the second dielectric region 22. The resulting overall surface composed of the redistribution layer 3 and the dielectric layer 2 is flatter, reducing the difficulty of subsequent processes.

[0030] In one embodiment, the sum of the thickness of the redistribution layer 3 and the thickness of the first dielectric region 21 is less than or equal to the thickness of the second dielectric region 22, achieving the effect of embedding the redistribution layer 3 into the dielectric layer 2, thereby reducing the thickness of the semiconductor structure. After the redistribution layer 3 is embedded into the dielectric layer 2, the total thickness of the semiconductor structure is reduced, the stiffness difference between the base structure 1 and the dielectric layer 2 is increased, the warpage of the semiconductor structure can be reduced, and a flatter surface can be provided for subsequent processes (including photolithography or coating processes), reducing the difficulty of subsequent process control.

[0031] In this embodiment, refer to Figure 2 The step of forming the dielectric layer 2 includes: forming an initial dielectric layer covering the pads 11 on the base structure 1; forming a first photoresist layer on the initial dielectric layer, wherein the first photoresist layer is a positive photoresist; providing a mask, for reference. Figure 1 The photomask includes a second mask region 42, a third mask region 43, and a plurality of spaced first mask regions 41. The second mask region 42 surrounds the plurality of spaced first mask regions 41, and the third mask region 43 surrounds the second mask region 42. The transmittance of the second mask region 42 is greater than that of the third mask region 43 and less than that of the first mask region 41. The first photoresist layer is exposed using the photomask. After the exposure process, the first photoresist layer is developed. After the development process, the initial dielectric layer is etched using the first photoresist layer as a mask, so that the initial dielectric layer forms the dielectric layer 2.

[0032] In this embodiment, because the transmittance of the second mask region 42 is greater than that of the third mask region 43 and less than that of the first mask region 41, when photolithography is performed through the mask plate, the different areas of the first photoresist layer can be exposed to different depths at one time by using mask regions with different transmittances. During the development process of the first photoresist layer, the thickness of the first photoresist layer in different areas can be made to be different, which reduces the complexity of the manufacturing process, reduces manufacturing costs and manufacturing time, and greatly improves production efficiency. Specifically, for ease of explanation, the initial dielectric layer includes a first initial region and a second initial region surrounding the first initial region. The first initial region includes a first etchable region and a second etchable region, with the second etchable region surrounding the first etchable region. The thickness of the first photoresist layer on the first initial region is less than the thickness of the first photoresist layer on the second initial region, and the thickness of the first photoresist layer on the first etchable region is less than the thickness of the first photoresist layer on the second etchable region. In one embodiment, the thickness of the first photoresist layer on the first etchable region is zero. The initial dielectric layer is etched using this first photoresist layer as a mask. During the etching process, the first etchable region is etched first, and the first etchable region is removed to form an opening in the dielectric layer 2. During the formation of the opening, the first photoresist layer on the second etchable region is removed, exposing the second etchable region. This allows etching of a portion of the thickness of the second etchable region, forming a first dielectric region 21 around the opening, while the second initial region forms a second dielectric region 22. Afterward, the first photoresist layer is removed.

[0033] The first mask region 41 corresponds to the opening penetrating the first dielectric region 21, the second mask region 42 corresponds to the first dielectric region 21 surrounding the opening, and the third mask region 43 corresponds to the second dielectric region 22, providing a flatter surface for the subsequent formation of the redistribution layer.

[0034] Furthermore, the second mask region 42 includes a mask connecting region 421 and a plurality of mask surrounding regions 423, the mask surrounding regions 423 surrounding the first mask region 41, and the mask connecting region 421 connecting at least two mask surrounding regions 423.

[0035] Since the mask surrounding region 423 surrounds the first mask region 41, a photolithography process is performed on the surface of the initial dielectric layer to form a patterned first photoresist layer. After using the first photoresist layer as a mask to perform an etching process on the initial dielectric layer, the sidewall of the opening penetrating the first dielectric region 21 formed has a stepped shape. (Refer to...) Figure 2 The presence of this step reduces the depth-to-width ratio of the opening, thereby mitigating the slope of the opening.

[0036] The step of forming the redistribution layer 3 includes: forming a second photoresist layer on the second dielectric region, the second photoresist layer exposing the first dielectric region and the opening; forming a redistribution layer on the inner wall of the opening and the first dielectric region surrounding the opening using the second photoresist layer as a mask; and then removing the second photoresist layer. The step of forming the second photoresist layer includes: forming a second initial photoresist layer on the first dielectric region, the second dielectric region, and in the opening; exposing and developing the second initial photoresist layer to form the second photoresist layer. The second initial photoresist layer uses a negative photoresist. If the negative photoresist is exposed to light, it is not easy to remove during development. Since the aspect ratio of the opening is reduced, the probability of light refraction at the step affecting the second initial photoresist layer at the bottom of the opening is reduced. This makes it easier to develop and remove the second initial photoresist layer on the surface of the pad 11 corresponding to the opening, thereby improving the development effect of the second initial photoresist layer and avoiding the second initial photoresist layer remaining on the surface of the pad 11. This also avoids affecting the electrical connection between the redistribution layer 3 and the pad 11 on the base structure 1.

[0037] In one embodiment, reference Figure 2 The included angle α between the top surface of the first dielectric region 21 and the sidewall surface of the second dielectric region 22 facing the first dielectric region 21 is 110° to 150°, for example: 110°, 120°, 130°, 140° or 150°. According to the characteristics of photolithography and etching processes, the closer the included angle α is to 90°, the higher the quality requirements of the photoresist, the higher the exposure accuracy requirements of the photolithography machine, and the higher the etching accuracy requirements of the etching machine. If the included angle α is less than 110°, it will inevitably increase the cost of photolithography and etching processes. If the included angle α is greater than 150°, it will inevitably increase the linewidth of the photolithography process, thereby affecting the accuracy of the photolithography process.

[0038] In one embodiment, reference Figure 2 The included angle b between the top surface of the first medium region 21 surrounding the opening and the sidewall surface of the opening is 110° to 150°, for example: 110°, 120°, 130°, 140° or 150°. The principle is the same as above, and will not be repeated here.

[0039] In one embodiment, the transmittance of the first mask region 41 is 90% to 100%, for example, 90%, 95%, or 100%; the transmittance of the first mask region 41 is 50% to 80%, for example, 50%, 60%, 70%, or 80%; the transmittance of the third mask region 43 is 0% to 5%, for example, 0%, 2%, or 5%; the transmittance of the first mask region 41, the transmittance of the first mask region 41, and the transmittance of the third mask region 43 are specifically determined by the depth of the opening, the thickness of the first dielectric region 21, and the thickness of the second dielectric region 22, which can be determined by those skilled in the art according to actual needs.

[0040] In one embodiment, reference Figure 1 A photomask is provided. The diameter of the first mask region 41 is 15 μm, and the transmittance of the first mask region 41 is 100%. The diameter of the mask surrounding region 422 is 35 μm, the width of the mask connecting region 421 is 15 μm, the transmittance of the second mask region 42 is 50%, and the transmittance of the third mask region 43 is 0%. The above photomask is used to perform a photolithography process on the surface of a dielectric layer with a thickness of 5 μm, and then an etching process is performed to obtain a first dielectric region with a thickness of 2 μm and a second dielectric region with a thickness of 5 μm. Then, a redistribution layer photolithography process and a redistribution layer metal deposition process are performed on the patterned dielectric layer surface and the exposed pad surface to remove the patterned photoresist and the redistribution layer metal located on the photoresist, forming a patterned redistribution layer with a thickness of 3 μm and a trace width of 15 μm.

[0041] Example 2

[0042] This embodiment provides a semiconductor structure, including: a base structure 1; a plurality of spaced pads 11 located on the base structure 1; a dielectric layer 2 located on the base structure 1, the dielectric layer 2 including a first dielectric region 21 and a second dielectric region 22 surrounding the first dielectric region 21, the first dielectric region 21 having a plurality of spaced openings penetrating the first dielectric region 21, the openings being located on the pads 11, the thickness of the first dielectric region 21 surrounding the openings being less than the thickness of the second dielectric region 22; and a redistribution layer 3 located on the inner wall surface of the openings and the top surface of the first dielectric region 21, the redistribution layer being electrically connected to the pads.

[0043] In this embodiment, since the thickness of the first dielectric region 21 around the opening is less than the thickness of the second dielectric region 22, the slope between the sidewall of the opening and the top surface of the first dielectric region 21 is reduced, and the longitudinal distance between the top surface of the pad 11 and the top surface of the first dielectric region 21 is reduced. This facilitates the patterning of the redistribution layer 3, avoids the formation of by-product residues during the process of defining the pattern of the redistribution layer 3, and ensures good contact between the redistribution layer 3 and the pad 11.

[0044] Secondly, the thickness of the first dielectric region 21 is less than the thickness of the second dielectric region 22, and the top surface of the first dielectric region 21 is lower than the top surface of the second dielectric region 22. This reduces the height of the top surface of the redistribution layer 3, decreases the distance between the top surface of the redistribution layer 3 and the top surface of the second dielectric region 22 around the opening, and prevents the redistribution layer 3 from being excessively recessed in the opening, providing a flatter surface for subsequent processes. Furthermore, the reduced distance between the top surface of the redistribution layer 3 and the top surface of the second dielectric region 22 reduces the overall thickness of the semiconductor structure, thus reducing the warpage of the semiconductor structure. A flatter surface and lower warpage reduce the risk of poor development in subsequent patterning processes.

[0045] Furthermore, the top surface of the redistribution layer 3 on the first dielectric region 21 around the opening is flush with the top surface of the second dielectric region 22. The resulting overall surface composed of the redistribution layer 3 and the dielectric layer 2 is flatter, reducing the difficulty of subsequent processes.

[0046] Furthermore, the second dielectric region 22 includes a dielectric connection region and a plurality of dielectric surrounding regions, the dielectric surrounding regions surrounding the first dielectric region 21, and the dielectric connection region connecting at least two dielectric surrounding regions. Specifically, the trace portion of the redistribution layer 3 is formed in the dielectric connection region, and the pad portion of the redistribution layer 3 is formed in the dielectric surrounding regions, and the plurality of pads of the redistribution layer 3 are interconnected through the traces of the redistribution layer 3.

[0047] In one embodiment, the included angle between the top surface of the first medium region 21 and the sidewall surface of the second medium region 22 facing the first medium region 21 is 110° to 150°, for example: 110°, 120°, 130°, 140° or 150°; the included angle between the top surface of the first medium region 21 around the opening and the sidewall surface of the opening is 110° to 150°, for example: 110°, 120°, 130°, 140° or 150°. The principle is the same as described in Embodiment 1, and will not be repeated here.

[0048] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The steps include the following: Provide basic infrastructure; A number of spaced pads are formed on the basic structure; A dielectric layer is formed on the basic structure. The dielectric layer includes a first dielectric region and a second dielectric region surrounding the first dielectric region. The first dielectric region has a plurality of spaced openings penetrating the first dielectric region, the openings exposing pads. The thickness of the first dielectric region around the openings is less than the thickness of the second dielectric region. A redistribution layer is formed on the inner wall surface of the opening and the top surface of the first dielectric region; The step of forming the dielectric layer includes: forming an initial dielectric layer covering the pads on the base structure; forming a first photoresist layer on the initial dielectric layer, wherein the first photoresist layer is a positive photoresist; providing a mask, the mask including a second mask region, a third mask region, and a plurality of spaced first mask regions, wherein the second mask region surrounds the plurality of spaced first mask regions, the third mask region surrounds the second mask region, and the transmittance of the second mask region is greater than the transmittance of the third mask region and less than the transmittance of the first mask region; exposing the first photoresist layer using the mask; developing the first photoresist layer after the exposure treatment; and etching the initial dielectric layer using the first photoresist layer as a mask after the development treatment, thereby forming the dielectric layer from the initial dielectric layer. The transmittance of the first mask area is 90%~100%; the transmittance of the second mask area is 50%~80%; and the transmittance of the third mask area is 0%~5%. The included angle between the top surface of the first medium region and the sidewall surface of the second medium region facing the first medium region is 110°~150°; the included angle between the top surface of the first medium region and the sidewall surface of the opening around the opening is 110°~150°; The step of forming the redistribution layer includes: forming a second photoresist layer on the second dielectric region, the second photoresist layer exposing the first dielectric region and the opening; forming a redistribution layer on the inner wall of the opening and the first dielectric region around the opening using the second photoresist layer as a mask; and then removing the second photoresist layer. The step of forming the second photoresist layer includes: forming a second initial photoresist layer on the first dielectric region, the second dielectric region and in the opening; exposing and developing the second initial photoresist layer to form the second photoresist layer; the second initial photoresist layer uses a negative photoresist.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The transmittance of the first mask area is 100%; the transmittance of the second mask area is 50%; and the transmittance of the third mask area is 0%.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second mask region includes a mask connection region and a plurality of mask surrounding regions, wherein the mask surrounding regions surround the first mask region, and the mask connection region connects at least two mask surrounding regions.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The top surface of the redistribution layer on the first dielectric region around the opening is flush with the top surface of the second dielectric region.

5. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1 to 4, comprising: Basic structure; A plurality of spaced pads located in the basic structure; A dielectric layer located on the basic structure, the dielectric layer includes a first dielectric region and a second dielectric region surrounding the first dielectric region, the first dielectric region having a plurality of spaced openings penetrating the first dielectric region, the openings being located on pads, and the thickness of the first dielectric region surrounding the openings being less than the thickness of the second dielectric region; A redistribution layer is located on the inner wall surface of the opening and the top surface of the first dielectric region, and the redistribution layer is electrically connected to the pads. The angle between the top surface of the first medium region and the sidewall surface of the second medium region facing the first medium region is 110°~150°; the angle between the top surface of the first medium region and the sidewall surface of the opening around the opening is 110°~150°.

6. The semiconductor structure according to claim 5, characterized in that, The second medium region includes a medium connection region and a plurality of medium surrounding regions, wherein the medium surrounding regions surround the first medium region, and the medium connection region connects at least two medium surrounding regions.

7. The semiconductor structure according to claim 5, characterized in that, The top surface of the redistribution layer on the first dielectric region around the opening is flush with the top surface of the second dielectric region.

Images