A package substrate structure for implementing inter-chip direct interconnection and a manufacturing method thereof

Abstract

The application relates to a packaging substrate structure for realizing inter-chip direct interconnection, comprising: a substrate; a first dielectric layer; a first chip, the front surface of the chip being embedded in the first dielectric layer, the first chip being provided with a first pad and a second pad with a size larger than the first pad; a second dielectric layer; a first metal through hole penetrating through the second dielectric layer and being electrically connected with the second pad; a second metal through hole penetrating through the second dielectric layer and the first dielectric layer and being electrically connected with a substrate pad; a third dielectric layer; a third metal through hole penetrating through the third dielectric layer and the second dielectric layer and being electrically connected with the first pad; a fourth metal through hole penetrating through the third dielectric layer and being electrically connected with the second metal through hole; wherein the top surfaces of the third metal through hole and the fourth metal through hole and the upper surface of the third dielectric layer are all provided with pads; and a second chip is flip-chip soldered on the pads on the top surface of the third metal through hole and the upper surface of the third dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a packaging substrate structure for realizing direct interconnection between chips and its manufacturing method. Background Technology

[0002] In traditional packaging technologies, interconnection and communication between chips typically require wiring on the packaging substrate or rewiring on an interposer (such as a silicon interposer). On one hand, with the rapid development of artificial intelligence, 5G, and portable mobile communication devices, the I / O density of semiconductor devices such as CPUs, GPUs, HBMs, and FPGAs has increased dramatically, while pad pitch has decreased, making traditional organic packaging substrates insufficient to support the high-density interconnection between these chips. On the other hand, silicon interposer (Si-Interposer) technology, by enabling wiring on Si-Interposers to achieve micron and submicron linewidths and spacings, can meet the requirements for high-density interconnection between multiple heterogeneous chips. The Si-Interposer process involves: first, fabricating TSVs (Through Silicon Vias) and RDLs (Redistribution Layers) on the Si-Interposer; then, mounting multiple chips onto the Si-Interposer using a flip-chip method; and finally, mounting the chip-bearing Si-Interposer onto a substrate, thus completing the interconnection and communication between chips and between chips and the substrate. However, the formation of TSVs on the Si-Interposer is complex and costly, and the yield of forming high aspect ratio TSVs is low, which is a major obstacle to the large-scale adoption of TSV technology.

[0003] In addition, interconnecting and communicating between chips through substrate wiring or adapter board rewiring increases signal delay and loss due to the additional trace length between chips.

[0004] Therefore, how to achieve high-density, low-loss interconnection between chips without an adapter board and without the need for rewiring has become a major problem that urgently needs to be solved. Summary of the Invention

[0005] To address at least some of the problems mentioned above in the prior art, the present invention provides a packaging substrate structure for realizing direct interconnection between chips, comprising:

[0006] A substrate, the front side of which has substrate pads;

[0007] A first dielectric layer is disposed on the front side of the substrate;

[0008] The first chip is embedded in the first dielectric layer with its front side facing upwards. The first chip has a first pad and a second pad with a size larger than the first pad.

[0009] A second dielectric layer covers the first dielectric layer and the first chip;

[0010] A first metal via penetrates the second dielectric layer and is electrically connected to the second pad of the first chip.

[0011] The second metal via penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the substrate pads.

[0012] A third dielectric layer covers the second dielectric layer;

[0013] A third metal via penetrates the third dielectric layer and the second dielectric layer, and is electrically connected to the first pad of the first chip.

[0014] A fourth metal via penetrates the third dielectric layer and is electrically connected to the second metal via; wherein pads are provided on the top surfaces of the third and fourth metal vias and on the upper surface of the third dielectric layer; and

[0015] The second chip is flip-chip bonded to the pads on the top surface of the third metal via and the pads on the upper surface of the third dielectric layer via bumps.

[0016] Furthermore, it also includes:

[0017] A first interconnect layer is disposed on the upper surface of the second dielectric layer and electrically connects the first metal via and the second metal via; and

[0018] The second wiring layer is disposed on the upper surface of the third dielectric layer and electrically connects the first metal via and the second metal via.

[0019] Furthermore, the second chip has a first bump and a second bump that is larger in size than the first bump.

[0020] Furthermore, the size of the first bump matches the size of the third metal via, and the size of the second bump matches the size of the pad on the upper surface of the third dielectric layer.

[0021] Furthermore, the first bump is composed of a copper pillar and a solder ball located at the head of the copper pillar; and / or

[0022] The second protrusion is a solder ball.

[0023] Furthermore, the diameter of the third metal through-hole is smaller than the diameter of the first metal through-hole.

[0024] The present invention also provides a method for fabricating a packaging substrate structure that enables direct interconnection between chips, comprising:

[0025] A first dielectric layer is disposed on the front side of a substrate with substrate pads, and a chip embedding trench is formed in the first dielectric layer.

[0026] The first chip is embedded in the chip embedding groove, and the first chip has a first pad and a second pad with a size larger than the first pad.

[0027] A second dielectric layer is disposed on the first dielectric layer and the first chip;

[0028] A first via is formed in the second dielectric layer to connect to the second pad of the first chip, and a second via is formed in the second dielectric layer and the first dielectric layer to connect to the substrate pad. The first via and the second via are metallized and conductively filled to form a first metal via and a second metal via. A pad is formed on the top surface of the first metal via and the second metal via. A first redistribution layer for electrically connecting the pad is formed on the upper surface of the second dielectric layer.

[0029] A third dielectric layer is disposed on the second dielectric layer;

[0030] A third via is formed in the third dielectric layer and the second dielectric layer to connect to the first pad of the first chip, and a fourth via is formed in the third dielectric layer to connect to the top pad of the second metal via. The third via and the fourth via are metallized and conductively filled to form the third metal via and the fourth metal via. Pads are formed on the top surface of the third metal via and the fourth metal via and on the upper surface of the third dielectric layer in the area where the second chip is to be attached. A second redistribution layer with electrical connection pads is formed on the upper surface of the third dielectric layer.

[0031] The second chip is flip-chip soldered to the pads on the top surface of the third metal via and the pads on the upper surface of the third dielectric layer.

[0032] Furthermore, the second chip has a first bump and a second bump with a size larger than the first bump, the size of the first bump being matched with the size of the third metal via, and the size of the second bump being matched with the size of the pad on the upper surface of the third dielectric layer.

[0033] Furthermore, the first bump is composed of a copper pillar and a solder ball located at the head of the copper pillar; and / or

[0034] The second protrusion is a solder ball.

[0035] Furthermore, the diameter of the third metal through-hole is smaller than the diameter of the first metal through-hole.

[0036] The present invention has at least the following beneficial effects: The present invention discloses a packaging substrate structure and manufacturing method for realizing direct interconnection between chips. The first chip in the packaging substrate structure has two types of chip pads with different sizes and densities. The first pad is a high-density, small-sized pad, and the second pad is larger in size and less dense than the first pad. The first pad is used for interconnection between the first chip and the second chip, and the second pad is used for interconnection between the first chip and the substrate. The shortest distance face-to-face interconnection between the first chip and the second chip is achieved by using metal vias, which can reduce losses and improve electrical performance. In this structure, the interconnection between chips is completed directly through the packaging substrate. There are no wiring, no adapter board, and no TSV technology between chips. The process is simple and the cost is low. Moreover, the face-to-face connection of the chips can also reduce the packaging area. Attached Figure Description

[0037] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0038] Figure 1 A cross-sectional schematic diagram of a packaging substrate structure for implementing indirect chip interconnection according to an embodiment of the present invention is shown; and

[0039] Figures 2A to 2G This diagram illustrates a cross-sectional view of the process of fabricating a packaging substrate structure that enables indirect chip interconnection according to an embodiment of the present invention. Detailed Implementation

[0040] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0041] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0042] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0043] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0044] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0045] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0047] Figure 1 A cross-sectional schematic diagram of a packaging substrate structure for implementing indirect chip interconnection according to an embodiment of the present invention is shown.

[0048] like Figure 1 As shown, a packaging substrate structure for realizing indirect chip interconnection includes a substrate 101, a first dielectric layer 102, a first chip 103, a second dielectric layer 104, a first metal through-hole 105, a second metal through-hole 106, a third dielectric layer 107, a third metal through-hole 108, a fourth metal through-hole 109, and a second chip 110.

[0049] The front side of the substrate 101 has substrate pads.

[0050] The first dielectric layer 102 covers the front side of the substrate 101. The first dielectric layer 102 can be a commonly used dielectric material such as ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric Material).

[0051] A first chip 103 is embedded in a first dielectric layer 102, with its back side connected to the front side of the substrate. The front side with chip pads faces upward and is substantially flush with the upper surface of the first dielectric layer 102. The first chip 103 has two types of chip pads: a first pad that is high-density and small in size, and a second pad that is low-density and large in size, with the second pad being larger than the first pad. The first pad of the first chip is used to achieve electrical interconnection between chips, and the second pad of the first chip is used to achieve electrical interconnection with the substrate. In one embodiment of the invention, the back side of the first chip is attached to the front side of the substrate using a back-side mounting material (such as adhesive).

[0052] The second dielectric layer 104 covers the first dielectric layer 102 and the first chip 103. The second dielectric layer 104 can be a commonly used dielectric material such as ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric Material).

[0053] The first metal via 105 penetrates the second dielectric layer 104 and is electrically connected to the second pad of the first chip 103. A pad is provided on the top surface of the first metal via 105.

[0054] The second metal via 106 penetrates the second dielectric layer 104 and the first dielectric layer 102, and is electrically connected to the substrate pads. A pad is provided on the top surface of the second metal via 106.

[0055] A first redistribution layer (not shown) is disposed on the upper surface of the second dielectric layer 104 and electrically connected to the first metal via 105 and the second metal via 106.

[0056] The third dielectric layer 107 covers the second dielectric layer 104. The third dielectric layer 107 can be a commonly used dielectric material such as ABF (Ajinomoto Built-up Film) or PID (Photo Imageable Dielectric Material).

[0057] The third metal via 108 penetrates the third dielectric layer 107 and the second dielectric layer 104, and is electrically connected to the first pad of the first chip 103. The diameter of the third metal via 108 is smaller than the diameter of the first metal via 105.

[0058] The fourth metal via 109 penetrates the third dielectric layer 107 and is electrically connected to the second metal via 106.

[0059] Pads are provided on the top surfaces of the third metal via 108 and the fourth metal via 109, as well as on the upper surface of the third dielectric layer 107.

[0060] A second rewiring layer (not shown) is disposed on the upper surface of the third dielectric layer 107 and electrically connects the third metal via 108, the fourth metal via 109 and the pads on the upper surface of the third dielectric layer 107.

[0061] The second chip 110 is flip-chip bonded to the pads on the top surface of the third metal via 108 and the pads on the upper surface of the third dielectric layer 107 via bumps. The second chip 110 has two bump specifications: the first bump 111 is a high-density, small-size bump consisting of copper pillars and solder balls at the heads of the copper pillars; the second bump 112 is larger and has a lower density, therefore solder balls are used for the second bump, and its size is larger than that of the first bump 111. The size of the first bump 111 matches the size of the third metal via 108, and the size of the second bump 112 matches the size of the pads on the upper surface of the third dielectric layer. The first bump 111 of the second chip 110 is used for inter-chip electrical interconnection, and the second bump 112 of the second chip 110 is used for electrical interconnection with the substrate. The size and density of the first bump 111 of the second chip 110 are determined based on the different bandwidth requirements between the first chip 103 and the second chip 110, as well as the aperture of the third metal via 108. The first chip 103 and the second chip 110 are directly interconnected through the third metal through-hole 108 to achieve communication.

[0062] In the above-described packaging substrate structure, the first chip 103 is electrically interconnected with the substrate 101 through a first metal via 105, a first redistribution layer, and a second metal via 106, transmitting power signals. The second chip 110 is electrically interconnected with the substrate 101 through a second redistribution layer, a fourth metal via 109, and a second metal via 106, transmitting power signals. The bandwidth of data transmission between the first chip 103 and the second chip 110 determines the size and density of the first pad and the first bump 111, as well as the size and density of the third metal via 108. The small-sized first pad and the first bump 111 achieve signal interconnection between chips through metal vias, realizing the shortest face-to-face interconnection, increasing interconnection density, reducing transmission distance, and minimizing losses. The large-sized second pad and the second bump 112 achieve power interconnection between the first chip and the second chip and the substrate, increasing current carrying capacity.

[0063] Figures 2A to 2G This diagram illustrates a cross-sectional view of the process of fabricating a packaging substrate structure that enables indirect chip interconnection according to an embodiment of the present invention.

[0064] Step 1, as follows Figure 2AAs shown, a first dielectric layer 202 is disposed on the front side of a substrate 201 with substrate pads, and a chip embedding groove 203 is formed in the first dielectric layer 202. The substrate pads are located on the front side of the substrate 201. In one embodiment of the present invention, the first dielectric layer 202 is disposed on the front side of the substrate 201 by a lamination process. The first dielectric layer 202 can be a commonly used dielectric material such as ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric Material). The thickness of the first dielectric layer 202 depends on the thickness of the embedded chip, and the thickness of the first dielectric layer 202 is generally greater than or equal to the thickness of the embedded chip.

[0065] Step 2, as follows Figure 2B As shown, a first chip 204 is mounted and embedded in a chip embedding trench 203. The first chip has two types of chip pads: a first pad 2041, which is a high-density, small-size pad, and a second pad 2042, which is a low-density, large-size pad. The size of the second pad 2042 is larger than that of the first pad 2041. The first pad 2041 of the first chip 204 is used to achieve electrical interconnection between chips, and the second pad 2042 of the first chip 204 is used to achieve electrical interconnection with the substrate. In one embodiment of the invention, the first chip 204 is mounted to the bottom of the chip embedding trench using adhesive.

[0066] Step 3, as follows Figure 2C As shown, a second dielectric layer 205 is disposed on the first dielectric layer 202 and the first chip 204. In one embodiment of the present invention, the second dielectric layer 205 is disposed on the first dielectric layer 202 and the first chip 204 by a lamination process. The second dielectric layer 205 can be a commonly used dielectric material such as ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric Material). The thickness of the second dielectric layer 205 needs to be determined according to the aperture size of the next step of opening the hole.

[0067] Step 4, as follows Figure 2DAs shown, a first via connecting to the second pad of the first chip 204 is formed in the second dielectric layer 205, and a second via connecting to the substrate pad is formed in the second dielectric layer 205 and the first dielectric layer 202. The first and second vias are metallized and conductively filled to form a first metal via 206 and a second metal via 207. Pads are formed on the top surfaces of the first metal via 206 and the second metal via 207. A first redistribution layer (not shown) for electrically connecting the pads is formed on the upper surface of the second dielectric layer. In one embodiment of the invention, the size of the first via is smaller than the size of the second via. In one embodiment of the invention, the first and second vias are formed by photolithography or laser drilling. Preferably, the first via is formed by photolithography and the second via is formed by laser drilling. After this step, the first chip 204 can achieve power signal conduction with the substrate 201.

[0068] Step 5, as follows Figure 2E As shown, a third dielectric layer 208 is disposed on the second dielectric layer 205. In one embodiment of the present invention, the third dielectric layer 208 is disposed on the second dielectric layer 205 by a lamination process. The third dielectric layer 208 can be a commonly used dielectric material such as ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric Material). The thickness of the third dielectric layer 208 needs to be determined according to the aperture size of the hole to be opened in the next step.

[0069] Step 6, as follows Figure 2F As shown, a third via connecting to the first pad of the first chip 204 is formed in the third dielectric layer 208 and the second dielectric layer 205, and a fourth via connecting to the top pad of the second metal via 207 is formed in the third dielectric layer 208. The third and fourth vias are metallized and conductively filled to form a third metal via 209 and a fourth metal via 210. Pads are formed on the top surfaces of the third metal via 209 and the fourth metal via 210 and on the upper surface of the third dielectric layer 208 in the area where the second chip is to be bonded. A second redistribution layer (not shown) electrically connecting the pads is formed on the upper surface of the third dielectric layer 208. The second redistribution layer electrically connects the top pads of the third metal via 209 and the fourth metal via 210 and the pads on the upper surface of the third dielectric layer 208. The diameter of the third metal via 209 is smaller than the diameter of the first metal via 206. In one embodiment of the present invention, the size of the third via is smaller than the size of the fourth via. In one embodiment of the present invention, the third and fourth through holes are formed by photolithography or laser drilling. Preferably, the third through hole is formed by photolithography, and the fourth through hole is formed by laser drilling.

[0070] Step 7, as follows Figure 2GAs shown, the second chip 211 is flip-chip soldered to the pads on the top surface of the third metal via 209 and the pads on the upper surface of the third dielectric layer 208, completing the interconnection between the second chip 211 and the first chip 204 and the substrate 201. The second chip 211 has two types of bumps. The first bump 212 of the second chip 211 is a high-density, small-size bump, consisting of copper pillars and solder balls at the heads of the copper pillars. The second bump 213 of the second chip 211 is larger in size and lower in density; therefore, solder balls are used for the second bump. The size of the second bump 213 of the second chip 211 is larger than the size of the first bump 212. The size of the first bump 212 matches the size of the third metal via 209, and the size of the second bump 213 matches the size of the pads on the upper surface of the third dielectric layer 208. The first bump 212 of the second chip 211 is used for electrical interconnection between chips, and the second bump 213 of the second chip 211 is used for electrical interconnection with the substrate. The size and density of the first bump 212 of the second chip 211 are determined based on the different bandwidth requirements between the first chip 204 and the second chip 211, as well as the aperture of the third metal via 209. The first chip 204 and the second chip 211 are directly interconnected through the third metal via 209 to achieve communication. The first chip 204 is electrically interconnected with the substrate 201 through the first metal via 206, the first redistribution layer, and the second metal via 207 to transmit power signals. The second chip 211 is electrically interconnected with the substrate 201 through the second redistribution layer, the fourth metal via 210, and the second metal via 207 to transmit power signals.

[0071] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A packaging substrate structure for realizing direct interconnection between chips, characterized in that, include: A substrate, the front side of which has substrate pads; A first dielectric layer is disposed on the front side of the substrate; The first chip is embedded in the first dielectric layer with its front side facing upwards. The first chip has a first pad and a second pad with a size larger than the first pad. A second dielectric layer covers the first dielectric layer and the first chip; A first metal via penetrates the second dielectric layer and is electrically connected to the second pad of the first chip. The second metal via penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the substrate pads. A third dielectric layer covers the second dielectric layer; A third metal via penetrates the third dielectric layer and the second dielectric layer, and is electrically connected to the first pad of the first chip. A fourth metal via penetrates the third dielectric layer and is electrically connected to the second metal via; wherein pads are provided on the top surfaces of the third and fourth metal vias and on the upper surface of the third dielectric layer; and The second chip is flip-chip bonded to the pads on the top surface of the third metal via and the pads on the upper surface of the third dielectric layer via bumps.

2. The packaging substrate structure for realizing direct interconnection between chips according to claim 1, characterized in that, Also includes: A first interconnect layer is disposed on the upper surface of the second dielectric layer and electrically connects the first metal via and the second metal via; and A second wiring layer is disposed on the upper surface of the third dielectric layer and electrically connects the first metal via, the second metal via, and the pads on the upper surface of the third dielectric layer.

3. The packaging substrate structure for realizing direct interconnection between chips according to claim 1, characterized in that, The second chip has a first bump and a second bump that is larger than the first bump.

4. The packaging substrate structure for realizing direct interconnection between chips according to claim 3, characterized in that, The size of the first bump matches the size of the third metal via, and the size of the second bump matches the size of the pad on the upper surface of the third dielectric layer.

5. The packaging substrate structure for realizing direct interconnection between chips according to claim 3, characterized in that, The first bump consists of a copper pillar and a solder ball located at the head of the copper pillar; and / or The second protrusion is a solder ball.

6. The packaging substrate structure for realizing direct interconnection between chips according to claim 1, characterized in that, The diameter of the third metal through hole is smaller than the diameter of the first metal through hole.

7. A method for fabricating a packaging substrate structure that enables direct interconnection between chips, characterized in that, include: A first dielectric layer is disposed on the front side of a substrate with substrate pads, and a chip embedding trench is formed in the first dielectric layer. The first chip is embedded in the chip embedding groove, and the first chip has a first pad and a second pad with a size larger than the first pad. A second dielectric layer is disposed on the first dielectric layer and the first chip; A first via is formed in the second dielectric layer to connect to the second pad of the first chip, and a second via is formed in the second dielectric layer and the first dielectric layer to connect to the substrate pad. The first via and the second via are metallized and conductively filled to form a first metal via and a second metal via. A pad is formed on the top surface of the first metal via and the second metal via. A first redistribution layer for electrically connecting the pad is formed on the upper surface of the second dielectric layer. A third dielectric layer is disposed on the second dielectric layer; A third via is formed in the third dielectric layer and the second dielectric layer to connect to the first pad of the first chip, and a fourth via is formed in the third dielectric layer to connect to the top pad of the second metal via. The third via and the fourth via are metallized and conductively filled to form the third metal via and the fourth metal via. Pads are formed on the top surface of the third metal via and the fourth metal via and on the upper surface of the third dielectric layer in the area where the second chip is to be attached. A second redistribution layer with electrical connection pads is formed on the upper surface of the third dielectric layer. The second chip is flip-chip soldered to the pads on the top surface of the third metal via and the pads on the upper surface of the third dielectric layer.

8. The method for fabricating a packaging substrate structure for direct interconnection between chips according to claim 7, characterized in that, The second chip has a first bump and a second bump with a size larger than the first bump. The size of the first bump matches the size of the third metal via, and the size of the second bump matches the size of the pad on the upper surface of the third dielectric layer.

9. The method for fabricating a packaging substrate structure for direct interconnection between chips according to claim 8, characterized in that, The first bump consists of a copper pillar and a solder ball located at the head of the copper pillar; and / or The second protrusion is a solder ball.

10. The method for fabricating a packaging substrate structure for direct interconnection between chips according to claim 7, characterized in that, The diameter of the third metal through hole is smaller than the diameter of the first metal through hole.

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