Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate having a rectangular shape including a side extending in a first direction and another side extending in a second direction. A thermal conductivity of the semiconductor substrate in the first direction is different from a thermal conductivity of the semiconductor substrate in the second direction. The semiconductor substrate is configured to satisfy a mathematical relationship of L1 / L2 = (K1 / K2) 0.5 with a tolerance range of -5% to +5%, where L1 represents a length of the semiconductor substrate in the first direction, L2 represents a length of the semiconductor substrate in the second direction, K1 represents a thermal conductivity of the semiconductor substrate in the first direction, and K2 represents a thermal conductivity of the semiconductor substrate in the second direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor substrates may generate heat during the use of semiconductor devices. The central portion of the semiconductor substrate tends to have a higher temperature than the outer periphery. JP 2007-027440 A discloses a semiconductor substrate with a lower cell density in the central portion than in the outer periphery. Current flows through the cells of the semiconductor substrate. According to the structure disclosed in JP2007-027440 A, the temperature rise in the central portion of the semiconductor substrate can be suppressed. Summary of the Invention

[0003] The thermal conductivity of a semiconductor substrate in a semiconductor device can be anisotropic. In such a semiconductor substrate, if the shape of the semiconductor substrate does not match the anisotropic thermal conductivity, the temperature of the central portion of the semiconductor substrate may easily rise. The object of this disclosure is to provide a semiconductor device that suppresses temperature rise in the central portion of a semiconductor substrate having anisotropic thermal conductivity.

[0004] According to a first aspect of this disclosure, a semiconductor device includes a semiconductor substrate having a rectangular shape when viewed along its thickness direction. The rectangular shape has one side extending in a first direction and another side extending in a second direction. The thermal conductivity of the semiconductor substrate in the first direction differs from its thermal conductivity in the second direction. The semiconductor substrate is configured to satisfy L1 / L2 = (K1 / K2). 0.5 The mathematical relationship is given, where the tolerance range is -5% to +5%, where L1 represents the length of the semiconductor substrate in the first direction, L2 represents the length of the semiconductor substrate in the second direction, K1 represents the thermal conductivity of the semiconductor substrate in the first direction, and K2 represents the thermal conductivity of the semiconductor substrate in the second direction.

[0005] In the aforementioned semiconductor device, the thermal resistance of the path from the central portion of the semiconductor substrate to the end of the semiconductor substrate in the first direction is substantially the same as the thermal resistance of the path from the central portion of the semiconductor substrate to the end of the semiconductor substrate in the second direction. Therefore, heat can be effectively dissipated from the central portion of the semiconductor substrate in both the first and second directions, and the temperature rise of the central portion of the semiconductor substrate can be suppressed. Attached Figure Description

[0006] The above-described objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings.

[0007] Figure 1It is a plan view of the semiconductor chip included in the semiconductor device according to the first embodiment;

[0008] Figure 2 This is a longitudinal cross-sectional view of the semiconductor device according to the first embodiment in the

[010] direction;

[0009] Figure 3 It is a graph showing the relationship between the thermal conductivity of β-type gallium oxide and temperature T;

[0010] Figure 4 It is a plan view of the semiconductor chip included in the semiconductor device according to the second embodiment; and

[0011] Figure 5 This is a longitudinal cross-sectional view of the semiconductor device according to the second embodiment in the

[010] direction. Detailed Implementation

[0012] In the semiconductor device disclosed in this embodiment, the semiconductor substrate may be made of a β-type gallium oxide-based semiconductor. Alternatively, the semiconductor substrate may be made of gallium oxide. Furthermore, the semiconductor substrate may be made of β-type gallium oxide. In this case, the first direction described in this disclosure may be the

[010] direction.

[0013] In the semiconductor device disclosed herein, the semiconductor device may have a top electrode located on a top surface of a semiconductor substrate and a bottom electrode located on a bottom surface of the semiconductor substrate. Current can flow through the semiconductor substrate between the top electrode and the bottom electrode. In this case, a heat sink may be attached to the bottom electrode. The heat sink may have isotropic thermal conductivity. A metal block may be attached to the top electrode. The metal block may have isotropic thermal conductivity.

[0014] The semiconductor device disclosed herein may further include a temperature sensing element for sensing the temperature of a semiconductor substrate. The temperature sensing element may be disposed at the central portion of the top surface of the semiconductor substrate.

[0015] (First Embodiment)

[0016] like Figure 1 , Figure 2 As shown, the semiconductor device 10 according to the first embodiment includes a semiconductor chip 12, a metal block 30, and a heat sink 40. The metal block 30 is fixed to the top surface of the semiconductor chip 12. The heat sink 40 is fixed to the bottom surface of the semiconductor chip 12. In the first embodiment, the semiconductor chip 12 is a Schottky barrier diode.

[0017] Semiconductor chip 12 includes a semiconductor substrate 22, a top electrode 26, and a bottom electrode 28. The semiconductor substrate 22 is made of β-type gallium oxide. The top surface 22a of the semiconductor substrate 22 is formed by the (001) plane of the β-type gallium oxide. The thickness direction of the semiconductor substrate 22 is parallel to the

[001] direction of the β-type gallium oxide. Hereinafter, the thickness of the semiconductor substrate 22 is referred to as thickness D. Figure 1 As shown, when viewed in the thickness direction, the semiconductor substrate 22 has an elongated rectangular shape in the lateral direction. The semiconductor substrate 22 has a long side 23 and a short side 24. When viewed from above, the long side 23 is parallel to the

[010] direction of β-type gallium oxide, and the short side 24 is parallel to the

[100] direction of β-type gallium oxide. In the following text, the length of the long side 23, in other words, the length of the semiconductor substrate 22 in the

[010] direction, is referred to as length L1; and the length of the short side 24, in other words, the length of the semiconductor substrate 22 in the

[100] direction, is referred to as length L2.

[0018] A top electrode 26 covers the top surface of the semiconductor substrate 22 and has a Schottky contact with the semiconductor substrate 22. A bottom electrode 28 covers the bottom surface 22b of the semiconductor substrate 22 and has an ohmic contact with the semiconductor substrate 22. The Schottky barrier diode is formed by the semiconductor substrate 22, the top electrode 26, and the bottom electrode 28. When the potential of the top electrode 26 is higher than the potential of the bottom electrode 28, current flows through the interior of the semiconductor substrate 22 from the top electrode 26 to the bottom electrode 28. When the potential of the top electrode 26 is lower than the potential of the bottom electrode 28, the current flowing through the semiconductor substrate 22 stops.

[0019] The metal block 30 is bonded to the top electrode 26, for example, by solder. Although not shown, a heat sink is bonded to the top surface of the metal block 30, for example, by an insulating layer. The metal block 30 serves as a wiring component allowing current to flow through the semiconductor chip 12 and as a heat dissipation component dissipating heat from the semiconductor chip 12. The metal block 30 is made of a metal such as copper. The metal block 30 has isotropic thermal conductivity. In other words, the thermal conductivity of the metal block 30 is the same in any direction.

[0020] The heat sink 40 is bonded to the bottom electrode 28, for example, by solder. The heat sink 40 serves as a wiring component allowing current to flow through the semiconductor chip 12 and as a heat dissipation component dissipating heat from the semiconductor chip 12. The heat sink 40 is made of a metal such as aluminum. The heat sink 40 has isotropic thermal conductivity. In other words, the thermal conductivity of the heat sink 40 is the same in any direction.

[0021] The semiconductor substrate 22, made of β-type gallium oxide, has anisotropic thermal conductivity. The thermal conductivity of β-type gallium oxide varies depending on the crystal orientation. Figure 3The relationship between the thermal conductivity of β-type gallium oxide and temperature T is shown for each crystal orientation. For example... Figure 3 As shown, in β-type gallium oxide, the thermal conductivity in the

[010] direction is higher than that in other directions. When the semiconductor substrate 22 is viewed in the thickness direction, the long side 23 is parallel to the

[010] direction, and the short side 24 is parallel to the

[100] direction. The thermal conductivity K1 of the semiconductor substrate 22 along the long side 23 is higher than that along the short side 24. For example, at T = 150 degrees Celsius (°C), the thermal conductivity K1 in the

[010] direction is 14.4 W / mK, while at T = 150°C, the thermal conductivity K2 in the

[100] direction is 7.2 W / mK.

[0022] The corresponding lengths L1 and L2 of the semiconductor substrate 22 are set to satisfy the following mathematical relationship (1), with a tolerance range of -5% to +5%. Note that the following mathematical relationship (1) can also be expressed as L1 / L2 = (K1 / K2) 0.5 The mathematical relationship.

[0023]

[0024] Additionally, the mathematical relation (2) below represents the mathematical relation (1) with a tolerance range of -5% to +5%. Note that the mathematical relation (1) below can also be expressed as (K1 / K2). 0.5 ×0.95≤L1 / L2≤(K1 / K2) 0.5 The mathematical relationship is ×1.05.

[0025]

[0026] When the Schottky barrier diode is turned on and current flows through the semiconductor substrate 22, the semiconductor substrate 22 dissipates heat. Because the semiconductor substrate 22 is bonded to the metal block 30 and the heat sink 40 over a wide area of ​​its top surface 22a and bottom surface 22b, the current flows relatively uniformly through the semiconductor substrate 22. Since the semiconductor substrate 22 is bonded to the metal block 30 and the heat sink 40 over a wide area of ​​its top surface 22a and bottom surface 22b, heat is dissipated substantially uniformly throughout the semiconductor substrate 22 via the metal block 30 and the heat sink 40. When the current flows uniformly through the semiconductor substrate 22 and heat is dissipated uniformly throughout the semiconductor substrate 22, the central portion 22c of the semiconductor substrate 22 experiences the highest temperature within the semiconductor substrate 22. In other words, the heat dissipated by the semiconductor substrate 22 moves laterally (in other words, perpendicular to the thickness direction) into the semiconductor substrate 22. Because the central portion 22c of the semiconductor substrate 22 is farther from the outer peripheral end of the semiconductor substrate 22, the central portion 22c of the semiconductor substrate 22 tends to have a higher temperature than the outer peripheral end of the semiconductor substrate 22. The Schottky barrier diode is controlled such that the temperature of the central portion 22c of the semiconductor substrate 22 does not exceed a reference value, in other words, the maximum operating temperature, for example, 150°C set for the Schottky barrier diode. For example, the temperature of the central portion 22c is predicted based on the operating conditions of the Schottky barrier diode, and the current value or conduction time of the Schottky barrier diode is limited so that the temperature of the central portion 22c does not exceed the reference value. In the semiconductor device 10 according to the first embodiment, since the shape of the semiconductor substrate 22 satisfies the mathematical relation (1), the temperature rise of the central portion 22c is suppressed. Details of suppressing the temperature rise of the central portion 22c are described below. The central portion 22c described in this disclosure covers the center of the semiconductor substrate 22 and may also be referred to as the central portion of the semiconductor substrate 22.

[0027] Figure 1 The heat dissipation path 101 shown is a heat dissipation path from the center portion 22c to the short side 24 (in other words, the outer peripheral end face of the semiconductor substrate 22) in the

[010] direction. Figure 1The heat dissipation path 102 in the diagram illustrates a heat dissipation path in the

[100] direction from the central portion 22c to the long side 23 (in other words, the outer peripheral end face of the semiconductor substrate 22). The thermal resistance R of the heat dissipation path is defined by the mathematical relationship R = Lr / (S·K). In this mathematical relationship, the variable lr represents the length of the heat dissipation path; the variable S represents the cross-sectional area of ​​the heat dissipation path; and the variable K represents the thermal conductivity of the heat dissipation path. The cross-sectional area S1 of the heat dissipation path 101 is the product of the length L2 and the thickness D. And the length Lr1 of the heat dissipation path 101 is half the length L1. Therefore, the thermal resistance R1 of the heat dissipation path 101 satisfies the mathematical relationship R1 = Lr1 / (S1·K1) = L1 / (2·L2·D·K1). The cross-sectional area S2 of the heat dissipation path 102 is the product of the length L1 and the thickness D. The length Lr2 of the heat dissipation path is half the length L2. Therefore, the thermal resistance R2 of heat dissipation path 102 satisfies the mathematical relationship R2=Lr2 / (S2·K2)=L2 / (2·L1·D·K2). When the thermal resistance R1 of heat dissipation path 101 is equal to the thermal resistance R2 of heat dissipation path 102, the mathematical relationship L1 / (2·L2·D·K1)=L2 / (2·L1·D·K2) is satisfied. This mathematical relationship is equivalent to mathematical relationship (1). In order to satisfy mathematical relationship (1), the thermal resistance R1 of heat dissipation path 101 is equal to the thermal resistance R2 of heat dissipation path 102.

[0028] As described above, the corresponding lengths L1 and L2 of the semiconductor substrate 22 are set to satisfy mathematical relation (1) and have a tolerance range of -5% to +5%. In the semiconductor substrate 22, the thermal resistance R1 of the heat dissipation path 101 is substantially equal to the thermal resistance R2 of the heat dissipation path 102. When the Schottky barrier diode is operating, heat is dissipated substantially uniformly from the central portion 22c through the heat dissipation paths 101 and 102. Heat dissipation is effectively achieved through the central portion 22c, and the temperature rise of the central portion 22c is suppressed. Even under relatively extreme temperature conditions, the semiconductor device 10 according to the first embodiment can continue to operate.

[0029] like Figure 3 As shown, the thermal conductivity varies with the temperature of the semiconductor substrate. The thermal conductivity at temperatures within the operating temperature range of the semiconductor device can be used as the thermal conductivity K1 and K2 in the mathematical relationship (1). For example, the thermal conductivity at the highest operating temperature of the semiconductor device (e.g., 150°C) can be used as the thermal conductivity K1 and K2.

[0030] (Second Embodiment)

[0031] Figure 4 , Figure 5 Semiconductor devices 110 according to the second embodiment are shown respectively. Figure 4 , Figure 5In this embodiment, the same reference numerals as in the first embodiment are assigned to the portions corresponding to the various parts of the semiconductor device 10 in the first embodiment. In the semiconductor device 110 according to the second embodiment, the semiconductor chip 12 is a metal-oxide-semiconductor field-effect transistor (MOSFET). That is, a MOSFET structure having, for example, a gate electrode, a gate insulating film, a source layer, a body layer, and a drain layer is formed inside the semiconductor substrate 22. In the second embodiment, the top electrode 26 is the source electrode of the MOSFET, and the bottom electrode 28 is the drain electrode of the MOSFET. The top electrode 26 is connected to the metal block 30, and the bottom electrode 28 is connected to the heat sink 40. In the second embodiment, the metal block 30 is arranged to cover the temperature sensing element 90.

[0032] In the second embodiment, a temperature sensing element 90 is disposed on the top surface 22a of the semiconductor substrate 22. The temperature sensing element 90 is a pn diode made of a polycrystalline silicon film disposed on the top surface 22a of the semiconductor substrate 22. The temperature sensing element 90 is insulated from the semiconductor substrate 22 by an interlayer insulating film (not shown). A top electrode 26 is disposed on the top surface 22a to avoid the temperature sensing element 90 and its wiring 91, 92. Signal electrodes 27a to 27c are disposed on the top surface 22a of the semiconductor substrate 22. The signal electrodes 27a to 27c are arranged adjacent to the top electrode 26. The signal electrodes 27a to 27c are respectively connected to terminals (not shown) via wires 94.

[0033] Signal electrode 27c is connected to the gate electrode (not shown) of the MOSFET. When the MOSFET is used, a potential higher than the top electrode 26 (in other words, the source electrode) is applied to the bottom electrode 28 (in other words, the drain electrode). When a predetermined potential is applied to signal electrode 27c (in other words, the gate electrode), the MOSFET is turned on, and current flows from the bottom electrode 28 into the semiconductor substrate 22 and to the top electrode 26. When the potential of signal electrode 27c decreases, the MOSFET is turned off, and current stops flowing.

[0034] Signal electrode 27a is connected to temperature sensing element 90 via wiring 91. Signal electrode 27b is connected to temperature sensing element 90 via wiring 92. A constant current can flow through signal electrodes 27a and 27b to temperature sensing element 90 (in other words, a pn diode). When the temperature of temperature sensing element 90 changes, the forward voltage generated by temperature sensing element 90 decreases. Therefore, the temperature of temperature sensing element 90 can be sensed by sensing the voltage between signal electrodes 27a and 27b. Since temperature sensing element 90 is located at the center of the top surface 22a of semiconductor substrate 22, the temperature of the central portion 22c of semiconductor substrate 22 can be sensed by temperature sensing element 90.

[0035] In the second embodiment, the semiconductor substrate 22 is made of β-type gallium oxide. In the second embodiment, similar to the first embodiment, the long side 23 is parallel to the

[010] direction; and the short side 24 is parallel to the

[100] direction. In the second embodiment, the corresponding lengths L1 and L2 of the semiconductor substrate 22 are set to satisfy mathematical relation (1), with a tolerance range of -5% to +5%.

[0036] In the second embodiment, the semiconductor substrate 22 dissipates heat during the operation of the MOSFET. The temperature of the central portion 22c of the semiconductor substrate 22 is sensed by the temperature sensing element 90 during the operation of the MOSFET. The MOSFET is controlled such that the temperature of the central portion 22c sensed by the temperature sensing element 90 does not exceed a reference value, such as a maximum operating temperature defined for the MOSFET. For example, when the temperature sensed by the temperature sensing element 90 exceeds the reference value, the current flowing through the MOSFET can be suppressed. For example, when the temperature sensed by the temperature sensing element 90 exceeds the reference value, the operating time of the MOSFET can be suppressed. In the second embodiment, similar to the first embodiment, since the corresponding lengths L1 and L2 of the semiconductor substrate 22 are set to satisfy the mathematical relationship (1) with a tolerance range of -5% to +5%, heat dissipation is effectively achieved from the central portion 22c of the semiconductor substrate 22. The temperature rise of the central portion 22c of the semiconductor substrate 22 is suppressed, and the temperature rise sensed by the temperature sensing element 90 is also suppressed. Therefore, the MOSFET can continue to operate even under extreme temperature conditions.

[0037] In the second embodiment, depending on the layout of the MOSFETs in the semiconductor substrate 22, the location with the highest temperature in the semiconductor substrate 22 can be offset from the center portion 22c. In this case, the position of the temperature sensing element 90 can be offset from the center portion 22c.

[0038] In the first and second embodiments, the direction in which the long side 23 extends is the

[010] direction, and the direction in which the short side 24 extends is the

[100] direction. Each of the directions in which the long side 23 extends and the short side 24 extends can be any direction, provided that the thermal conductivity in the direction in which the long side 23 extends is higher than the thermal conductivity in the direction in which the short side 24 extends.

[0039] In the first and second embodiments, the semiconductor substrate 22 may be made of β-type gallium oxide. However, the semiconductor substrate 22 may be made of other types of gallium oxide, or it may be made of an oxide semiconductor different from gallium oxide. Additionally, the semiconductor substrate 22 may be a semiconductor different from an oxide semiconductor. Various types of materials with anisotropic thermal conductivity can be used as the material for the semiconductor substrate 22.

[0040] The

[010] direction described in the embodiments may be, for example, a first direction. The

[100] direction described in the embodiments may be, for example, a second direction. The long side 23 described in the embodiments may be, for example, a side extending in the first direction. The short side 24 described in the embodiments may be, for example, a side extending in the second direction.

[0041] Although embodiments have been described in detail above, these are merely examples and do not limit the scope of this disclosure. The techniques described in this disclosure include various modifications and alterations to the specific examples described above. The technical elements described in this disclosure or the accompanying drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in this disclosure at the time of submission. Furthermore, the techniques shown in this specification or the accompanying drawings achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a rectangular shape when viewed along its thickness direction, the rectangular shape having one side extending in a first direction and another side extending in a second direction. The thermal conductivity of the semiconductor substrate in the first direction is different from the thermal conductivity of the semiconductor substrate in the second direction. The semiconductor substrate is configured to satisfy L1 / L2 = (K1 / K2) 0.5 The mathematical relationship has a tolerance range of -5% to +5%, where L1 represents the length of the semiconductor substrate in the first direction. L2 represents the length of the semiconductor substrate in the second direction. K1 represents the thermal conductivity of the semiconductor substrate in the first direction, and K2 represents the thermal conductivity of the semiconductor substrate in the second direction.

2. The semiconductor device as described in claim 1, The semiconductor substrate is made of oxide semiconductor.

3. The semiconductor device as described in claim 1, The semiconductor substrate is made of gallium oxide.

4. The semiconductor device as described in claim 1, The semiconductor substrate is made of β-type gallium oxide.

5. The semiconductor device as described in claim 4, The first direction is the [010] direction of the β-type gallium oxide.

6. The semiconductor device of claim 1, further comprising: The top electrode is located on the top surface of the semiconductor substrate; as well as The bottom electrode is located on the bottom surface of the semiconductor substrate. The semiconductor substrate is further configured to allow current to flow through the semiconductor substrate between the top electrode and the bottom electrode.

7. The semiconductor device of claim 6, further comprising: A heat sink, which is connected to the bottom electrode.

8. The semiconductor device as claimed in claim 7, The heat sink described herein has isotropic thermal conductivity.

9. The semiconductor device of claim 6, further comprising: A metal block that is attached to the top electrode.

10. The semiconductor device as claimed in claim 9, The metal block described therein has isotropic thermal conductivity.

11. The semiconductor device according to any one of claims 1 to 10, further comprising: A temperature sensing element configured to sense the temperature of the semiconductor substrate.

12. The semiconductor device as claimed in claim 11, in, The temperature sensing element is located at the central portion of the top surface of the semiconductor substrate.

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