An FPGA-based OTFS low-complexity GAMP detection algorithm IP core implementation method

Abstract

This paper discloses an FPGA-based implementation method for an OTFS low-complexity GAMP detection algorithm IP core. First, the advantages of algorithm software simulation are explained in principle, and an OTFS detection algorithm that is easier to implement in hardware is proposed. Secondly, a reasonable hardware implementation architecture is proposed for the algorithm, and hardware module design is performed in sequence. This method uses the Vivado development platform for hardware design and is simulated and verified on an XC7A200T FPGA. This method can accelerate the development of digital baseband links in the early stages of OTFS receiver development and provide a valuable reference for the design of subsequent OTFS prototypes in key 6G technology research.

Description

Technical Field

[0001] The present invention belongs to the field of electronic communication technology, and specifically provides an FPGA-based OTFS low-complexity GAMP detection algorithm IP core implementation method. Background Art

[0002] Orthogonal Time-Frequency-Space (OTFS) modulation, a new two-dimensional modulation technique, effectively mitigates the effects of Doppler shift and multipath on communication systems. Compared to traditional Orthogonal Frequency Division Multiplexing (OFDM), it is more suitable for high-dynamic scenarios. Therefore, studying its performance is crucial. The design of OTFS receivers is currently a hot topic of research.

[0003] For OTFS, the sparsity of its delay-Doppler domain channel provides unique advantages for receiver detection. Many researchers have designed OTFS detection and equalization methods with superior bit error rate performance from a communications perspective. However, hardware implementation still faces challenges such as high complexity and difficulty in system optimization. Furthermore, research on OTFS transmitter and receiver design has so far yielded few promising solutions.

[0004] FPGA devices are a type of semi-custom circuit in application-specific integrated circuits. In wireless communications, FPGAs can handle complex communication protocols and leverage the advantages of their own programmable logic circuits to quickly design and simulate the communication physical layer, as well as achieve a reasonable compromise between algorithm complexity and system performance. Summary of the Invention

[0005] The purpose of the present invention is to provide an FPGA-based OTFS low-complexity GAMP detection algorithm IP core implementation method.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] An FPGA-based OTFS low-complexity GAMP detection algorithm IP core implementation method includes the following steps:

[0008] Step 1: Optimize GAMP detection at the receiving end of the OTFS digital baseband link;

[0009] Step 2: Design the algorithm system architecture;

[0010] Step 3: Channel matrix storage design;

[0011] Step 4: Design the module transmission port;

[0012] Step 5: Design the multiplier and divider module called by the algorithm;

[0013] Step 6: Low-complexity GAMP algorithm IP core interface design.

[0014] Furthermore, step 1 converts the delay-Doppler domain matrix from the complex domain to the real domain, and based on the real symmetry and sparsity of the matrix, further performs matched filtering on the received signal without affecting the bit error rate, thereby enhancing the amplitude of the matrix diagonal elements.

[0015] Furthermore, step 2 subdivides the algorithm into five modules. The top layer is controlled by a state machine to jump to different states. When the termination decision module is reached, the difference between the current output vector and the initial vector is compared with the size of the iterative convergence threshold to determine whether a state cycle jump needs to be performed again.

[0016] Furthermore, the step 2 is specifically as follows:

[0017] Step 2.1: Specific GAMP algorithm module;

[0018] Initialization: When there is no external information input, the detection is in the idle state, that is, the IDLE state, and the detection IP has no operation at this time; when external information is input, the information input valid signal in_valid changes from low level to high level, and the detection of a frame signal begins. The initial probability and mean variance of the symbol point are initialized and assigned. When the assignment is completed, the idle_done signal is output as 1; at this time, the state machine jumps to the observation node update module;

[0019] Observation Node Update Module: This module is responsible for updating the mean and variance values ​​of the observation nodes. When this module completes its work, it pulls the one_done signal high. When the state machine detects this signal is high, it jumps to the variable node update module, and the next module starts working.

[0020] Variable node update module: responsible for updating the mean and variance values ​​of variable nodes. After the update of this module is completed, the two_done signal is pulled high, the state machine jumps to the probability mass function update module, and the next module starts working;

[0021] Probability mass function update module: used to calculate the probability of each initial mapping point. After this module is completed, it outputs the three_done signal as 1 and the updated value of the x signal. The state machine jumps to the termination decision module, and the next module starts working.

[0022] Termination decision module: By comparing the probability information of the symbol points, it determines the output of the final detection x vector; by comparing the difference between the x before and after the update, it determines whether the system iteration has ended. If not, the state machine re-enters the observation node update module to start working; if the detection output conditions are met, it outputs all detection results and the number of error bits, ending the detection of the current frame signal; and jumps to the initialization state, waiting for the next frame signal to enter the detection;

[0023] Step 2.2: The observation node, variable node, and probability mass function module all need to use the channel matrix value information stored in the ROM. Considering resource usage, these three modules send corresponding enable valid signals in turn when using the ROM value;

[0024] Step 2.3: When the state machine jumps to the next state, it outputs an fsm_begin signal. Each module detects the rising edge of the fsm_begin signal to generate the start signal of this module. In the logic control, the enable signal is generated by counting to implement the corresponding internal module calculation.

[0025] Furthermore, step 3 is specifically as follows:

[0026] Step 3.1: Abstract the channel into Indicates that the purpose of the detection algorithm is to receive the signal y r and the channel matrix H r Efficiently detect the transmitted signal x r , the study found that the OTFS channel matrix has a unique sparsity, and the left side of the formula is multiplied by Get a new input and output relationship in

[0027] Step 3.2: Design a reasonable hardware architecture for the GAMP detection algorithm; suppose M = 8, N = 8, then the channel matrix is ​​a 64*64 complex matrix, using the formula Convert it into a real number matrix of size 128*128;

[0028] Step 3.3: Divide the channel matrix parameters into 8 blocks of size 2N*2MN. Expand each new matrix block row by row and extract non-zero values. Then multiply the extracted values ​​by 2^22 to ensure 6 decimal places of accuracy.

[0029] Step 3.4: Store the amplified data in single-port ROMs, corresponding to ROM1 to ROM8 respectively; and implement matrix and vector multiplication by controlling the read order of the ROMs in the program logic.

[0030] Furthermore, step 4 is specifically as follows:

[0031] Step 4.1: Data transmission between different modules is uniformly defined using wire[M*N*2*20-1:0]. After real domain conversion, the length of each vector in the algorithm is M*N*2, and each element is represented by a 20-bit fixed-point number in hardware.

[0032] Step 4.2: Process the number of symbols M and the number of subcarriers N as parameters. All decimals in the software are converted to 20-bit fixed-point numbers in the hardware. For signed numbers, 1 sign bit, 3 integer bits, and 16 decimal bits are defined; for unsigned numbers, 4 integer bits and 16 decimal bits are defined.

[0033] Furthermore, step 5 is specifically as follows:

[0034] Step 5.1: The algorithm involves signed and unsigned vector division. When calling the Xilinx divider IP, select the integer + decimal output mode and define the decimal width as 16 bits. For the signed vector division operation in the algorithm, the sign of the number is first determined at the input, and all operands are positive before the division operation. The sign of the result is adjusted based on the initial determination at the output, and the sign bit of the decimal part is removed from the 0 bit.

[0035] Step 5.2: In matrix-vector and vector-vector multiplication, call Xilinx's own multiplier IP for signed number multiplication, using the area-first two-pipeline mode. Finally, right-shift the output result to retain the 16-bit decimal place.

[0036] Furthermore, in step 6, a simulation stimulus test file is written, and the demodulated data output by the hardware is compared and counted with the input random number, and the final number of erroneous bits is output; when the current state machine enters the iteration termination decision module and the convergence condition is met, the detec_done signal is output as 1 to indicate the end of the detection behavior.

[0037] The beneficial effects of the present invention are:

[0038] The present invention can achieve an effective balance between rate and area, and can further reduce the number of convergence iterations of the GAMP algorithm through matched filtering before detection, so that the hardware resources occupied by the detection algorithm are smaller, the rate is higher, and it has good practicality.

[0039] This paper pioneers a hardware-friendly IP core implementation of the OTFS detection algorithm, featuring a rational design and high configurability. To pioneer hardware resource and performance evaluation of the OTFS detection algorithm, this paper provides a low-complexity IP core implementation of the OTFS generalized approximate message passing algorithm (GAMP). This approach can accelerate the development of digital baseband links in the early stages of OTFS receiver development and provide valuable insights for the design of subsequent OTFS prototypes in key 6G technology research. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is the design architecture diagram of the OTFS low-complexity GAMP detection algorithm IP core of the present invention;

[0041] Figure 2 Schematic diagram of the structure of the OTFS channel matrix after real domain conversion of the present invention;

[0042] Figure 3 The GAMP algorithm simulated by the present invention observes the node information update waveform;

[0043] Figure 4 The GAMP algorithm variable node information update waveform diagram simulated by the present invention;

[0044] Figure 5 This is the waveform diagram of the top-level state machine of the GAMP algorithm simulated by the present invention. DETAILED DESCRIPTION

[0045] The present invention will be further described below with reference to the accompanying drawings.

[0046] Before discussing the embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0047] like Figure 1 As shown, the present invention provides an FPGA-based OTFS low-complexity GAMP detection algorithm IP core design solution, which specifically includes the following steps:

[0048] Step 1: Algorithm preprocessing design;

[0049] First, software simulation of the GAMP detection performance is performed at the receiving end in the OTFS digital baseband link. To facilitate hardware implementation and further reduce the algorithm complexity, the present invention first converts the delay-Doppler domain matrix from the complex domain to the real domain. Based on the real symmetry and sparsity of the matrix, the received signal is further matched filtered to enhance the amplitude of the matrix diagonal elements without affecting the bit error rate. In the simulation, it can be found that performing GAMP detection on the matched filtered signal can further reduce the number of loop iterations, thereby reducing the complexity of the hardware implementation, making the algorithm easier to implement in hardware.

[0050] Step 2: Design the algorithm system architecture;

[0051] The algorithm is subdivided into five modules. The top level is controlled by a state machine to jump to different states. When it reaches the termination decision module, it decides whether to repeat the state cycle by comparing the difference between the current output vector and the initial vector and the size of the iterative convergence threshold.

[0052] Step 2.1: The specific GAMP algorithm module functions are described as follows:

[0053] Initialization: When no external information is input, the detection is in the idle state (IDLE state), and the detection IP is inactive. When external information is input, the in_valid signal goes from low to high, and detection of a frame of signal begins. Initial values ​​for the symbol point probabilities and mean-variance are initialized and assigned. When the assignment is complete, the idle_done signal is output as 1. At this point, the state machine jumps to the observation node update module.

[0054] Observation node update module: responsible for updating the mean and variance values ​​of the observation nodes. When this module completes its work, it pulls the one_done signal high, such as Figure 4 As shown in the figure, the state machine detects that the signal is pulled high and jumps to the variable node update module, and the next module starts working.

[0055] Variable node update module: responsible for updating the mean and variance values ​​of variable nodes. After the update of this module is completed, the two_done signal is pulled high, the state machine jumps to the probability mass function update module, and the next module starts working.

[0056] Probability Mass Function Update Module: This module calculates the probability of each initial mapping point. Upon completion, this module outputs a three_done signal of 1 and an updated value for the x signal. The state machine then jumps to the termination decision module, and the next module begins operation.

[0057] The termination decision module compares the probability information of the symbol points and outputs the final detected x vector. The difference between the updated x values ​​before and after the update is compared to determine whether the system iteration has ended. If not, the state machine re-enters the observation node update module and begins operation. If the detection output conditions are met, all detection results and the number of error bits are output, ending the detection of the current frame. The module then jumps to the initialization state, waiting for the next frame to be detected.

[0058] Step 2.2: The observation node, variable node, and probability mass function module all need to use the channel matrix value information pre-stored in the ROM. Considering the resource occupation issue, these three modules send corresponding enable valid signals in turn when using the ROM value.

[0059] Step 2.3: When the state machine jumps to the next state, it outputs an fsm_begin signal. Each module detects the rising edge of the fsm_begin signal to generate the start signal of this module. In the logic control, the enable signal is generated by counting to implement the corresponding internal module calculation.

[0060] Step 3: Channel matrix storage design;

[0061] Step 3.1: Under the same software simulation conditions, the channel matrix is ​​a 64*64 complex domain matrix. Considering that the algorithm involves a large number of multiplication and division operations, which will bring more complexity and occupy a lot of resources, the algorithm is converted to the real domain through matrix transformation operations for calculation. This not only saves multiplier resources in the FPGA but also reduces the complexity of the operation. Figure 2 As shown, the new matrix size after transformation is 128*128.

[0062] Step 3.2: Considering the excellent parallel processing capabilities of FPGAs and the resource utilization and computational speed of matrix-vector operations, the present invention divides the matrix horizontally into 16*128 matrix blocks. The first and ninth blocks are concatenated into a new matrix, and so on. For a total of eight matrix blocks, each new matrix block is expanded row by row, and non-zero values ​​are extracted and multiplied by 2^22 to ensure six decimal places of accuracy. The amplified data is stored in single-port ROMs, designated ROM1 through ROM8. Matrix and vector multiplication is achieved by controlling the ROM read order in the program logic.

[0063] Step 3.3: In matched filtering, since the matrix square operation is involved and the transformed matrix is ​​a real symmetric matrix, by comparing the characteristics of the elements in the matrix, it can be seen that the elements of the square matrix except the diagonal elements are all less than 10^-8, so they can be treated as 0 in the design. Under the 100MHZ clock simulation excitation, the mean variance information simulation waveform is as follows Figure 3 and Figure 4As shown in Figure 2, it can be seen that for an 8-way parallel computing architecture, the update of a column vector information can be completed in approximately 260 clock cycles.

[0064] Step 4: Data interface design;

[0065] Step 4.1: Data transmission between different modules is uniformly defined using wire[M*N*2*20-1:0]. After real domain conversion, the length of each vector in the algorithm is M*N*2, and each element is represented by a 20-bit fixed-point number in hardware.

[0066] Step 4.2: Because IP core design requires consistent data formats between different modules, it's best to define unified data types at the outset. This invention treats the number of symbols, M, and the number of subcarriers, N, as parameters. All decimals in the software are treated as 20-bit fixed-point numbers in the hardware. Signed numbers are defined with 1 sign bit, 3 integer bits, and 16 decimal bits; unsigned numbers are treated with 4 integer bits and 16 decimal bits. In hardware, 16 bits are sufficient to represent data with 4 decimal places.

[0067] Step 5: Design the multiplier and divider called by the algorithm;

[0068] Step 5.1: The algorithm involves division of signed and unsigned vectors. When calling the Xilinx divider IP, select integer + decimal output mode, and select a 16-bit bit width for the decimal fraction. For the signed vector division operation in the algorithm, the present invention first determines the sign of the signed number at the input, then converts all operands to positive numbers before performing the division operation. The output adjusts the sign of the result based on this initial determination, paying special attention to removing the sign bit of the decimal fraction from the zero position.

[0069] Step 5.2: In matrix-vector and vector-vector multiplication, the present invention calls Xilinx's own multiplier IP for signed number multiplication operations, and finally right-shifts the output result to retain the 16-bit decimal part.

[0070] Step 6: Output the low-complexity GAMP algorithm IP core;

[0071] Write a simulation stimulus test file, compare the demodulated data output by the hardware with the input random number, and output the final number of error bits. Figure 5 As shown, when the current state machine enters the iteration termination decision module and the convergence condition is met, the output detec_done signal is 1 to indicate the end of the detection behavior.

[0072] This invention proposes, for the first time, a hardware implementation method for the low-complexity GAMP detection algorithm for OTFS. By combining the existing characteristics of the OTFS channel matrix with hardware-based matched filtering and real-domain conversion, this method further reduces the complexity of the hardware implementation by reducing the number of convergence iterations of the detection algorithm without reducing the bit error rate. The entire IP core is designed and simulated sequentially from five modules, with a top-level state machine controlling the jump sequence of each module. Furthermore, this invention rationally designs the matrix storage architecture in hardware, providing a reliable IP core design solution for OTFS receiver design, achieving a breakthrough from scratch.

[0073] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for implementing an OTFS low-complexity GAMP detection algorithm IP core based on FPGA, characterized by: Step 1: Optimize GAMP detection at the receiving end of the OTFS digital baseband link; Step 2: Design the algorithm system architecture; The step 2 is specifically as follows: Step 2.1: The GAMP algorithm module includes the following steps; Initialization: When there is no external information input, the detection is in the idle state, that is, the IDLE state, and the detection IP has no operation at this time; when external information is input, the information input valid signal in_valid changes from low level to high level, and the detection of a frame signal begins. The initial probability and mean variance of the symbol point are initialized and assigned. When the assignment is completed, the idle_done signal is output as 1; at this time, the state machine jumps to the observation node update module; Observation node update: Use the observation node update module to update the mean and variance values ​​of the observation nodes. When this module completes its work, it pulls the one_done signal high. After the state machine detects that the signal is pulled high, it jumps to the variable node update module, and the next module starts working. Variable node update: Use the variable node update module to update the mean and variance values ​​of the variable nodes. After the update of this module is completed, the two_done signal is pulled high, the state machine jumps to the probability mass function update module, and the next module starts working; Probability mass function update: Use the probability mass function update module to calculate the probability of each initial mapping point. After this module is completed, it outputs the three_done signal as 1 and the updated value of the x signal. The state machine jumps to the termination decision module, and the next module starts working. Termination decision: The termination decision module compares the probability information of the symbol points and outputs the final detected x vector. The difference between the updated x and the updated x is compared to determine whether the system iteration has ended. If not, the state machine re-enters the observation node update module to start working. If the detection output conditions are met, all detection results and the number of error bits are output, ending the detection of the current frame signal. The system then jumps to the initialization state and waits for the next frame signal to enter the detection state. Step 2.2: The observation node, variable node, and probability mass function modules all need to use the channel matrix value information stored in ROM. Considering resource usage, the observation node update module, variable node update module, and probability mass function update module send corresponding enable valid signals in sequence when using the ROM value; Step 2.3: When the state machine jumps to the next state, it outputs an fsm_begin signal. Each module described in step 2.1 detects the rising edge of the fsm_begin signal to generate the start signal of this module. In the logic control, the enable signal is generated by counting to implement the internal module calculation. Step 3: Channel matrix storage design; Step 3.1: Abstract the channel into Indicates that the purpose of the detection algorithm is to receive the signal y r and the channel matrix H r Efficiently detect the transmitted signal x r , the study found that the OTFS channel matrix has a unique sparsity, and the left side of the formula is multiplied by Get a new input and output relationship in Step 3.2: Design a reasonable hardware architecture for the GAMP detection algorithm; suppose M = 8, N = 8, then the channel matrix is ​​a 64*64 complex matrix, using the formula Convert it into a real number matrix of size 128*128; Step 3.3: Divide the channel matrix parameters into 8 blocks of size 2N*2MN, expand each new matrix block row by row, extract the non-zero value, and then multiply the extracted value by 2 22 times to ensure 6 decimal places of accuracy; Step 3.4: Store the amplified data into single-port ROMs, corresponding to ROM1 to ROM8 respectively; and implement matrix and vector multiplication by controlling the ROM read order in the program logic; Step 4: Design the module transmission port; Step 5: Design the multiplier and divider module called by the algorithm; Step 6: Low-complexity GAMP algorithm IP core interface design.

2. The FPGA-based OTFS low-complexity GAMP detection algorithm IP core implementation method according to claim 1, characterized in that: The step 1 converts the delay-Doppler domain matrix from the complex domain to the real domain. Based on the real symmetry and sparsity of the matrix, the received signal is further matched filtered without affecting the bit error rate, thereby enhancing the amplitude of the matrix diagonal elements.

3. The FPGA-based OTFS low-complexity GAMP detection algorithm IP core implementation method according to claim 1, characterized in that: Step 2 subdivides the algorithm into five modules. The top layer is controlled by a state machine to jump to different states. When the termination decision module is reached, the difference between the current output vector and the initial vector is compared with the size of the iterative convergence threshold to determine whether a state cycle jump needs to be performed again.

4. The method for implementing an FPGA-based OTFS low-complexity GAMP detection algorithm IP core according to claim 1, wherein: Step 4 is as follows: Step 4.1: Data transmission between different modules is uniformly defined using wire[M*N*2*20-1:0]. After real domain conversion, the length of each vector in the algorithm is M*N*2, and each element is represented by a 20-bit fixed-point number in hardware. Step 4.2: Process the number of symbols M and the number of subcarriers N as parameters. All decimals in the software are converted to 20-bit fixed-point numbers in the hardware. For signed numbers, 1 sign bit, 3 integer bits, and 16 decimal bits are defined; for unsigned numbers, 4 integer bits and 16 decimal bits are defined.

5. The method for implementing an FPGA-based OTFS low-complexity GAMP detection algorithm IP core according to claim 1, wherein: Step 5 is as follows: Step 5.1: The algorithm involves signed and unsigned vector division. When calling the Xilinx divider IP, select the integer + decimal output mode and define the decimal width as 16 bits. For the signed vector division operation in the algorithm, the sign of the number is first determined at the input, and all operands are positive before the division operation. The sign of the result is adjusted based on the initial determination at the output, and the sign bit of the decimal part is removed from the 0 bit. Step 5.2: In matrix-vector and vector-vector multiplication, call Xilinx's own multiplier IP for signed number multiplication, using the area-first two-pipeline mode. Finally, right-shift the output result to retain the 16-bit decimal place.

6. The method for implementing an FPGA-based OTFS low-complexity GAMP detection algorithm IP core according to claim 1, wherein: Step 6: Write a simulation stimulus test file, compare the demodulated data output by the hardware with the input random number, and output the final number of error bits; When the current state machine enters the iteration termination decision module and the convergence condition is met, the output detec_done signal is 1 to indicate the end of the detection behavior.

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