Sensing circuit

Abstract

This disclosure discloses a sensing circuit including a first transistor, a second transistor, a third transistor, a photosensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to both the control terminal and the second terminal. The photosensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal.

Description

Technical Field

[0001] This disclosure relates to a sensing circuit, and more particularly to a sensing circuit that improves the amplification factor within a pixel circuit and reduces the effect of threshold voltage drift. Background Technology

[0002] Image sensors primarily use active pixel sensors (APS) as the communication interface between the light-sensing component and the back-end readout system. The pixel circuitry typically uses a source follower to transmit the signal changes generated by the light-sensing component due to illumination to the back-end readout system. If the image sensor is placed in a low-light environment, the signal read by the back-end readout system will be quite weak, necessitating an increased exposure time to complete data processing, which is highly detrimental to the user experience.

[0003] Furthermore, the manufacturing process of thin-film transistors (TFTs) is susceptible to environmental, equipment, and non-ideal effects, causing the TFT's threshold voltage to drift. This results in different pixels receiving the same light intensity signal corresponding to different output voltages, which in turn affects the back-end reading system's image processing and leads to errors. Therefore, it is necessary to optimize the amplification of the sensing signal and reduce the impact of threshold voltage drift. Summary of the Invention

[0004] In view of this, the present invention proposes a sensing circuit, including a first transistor, a second transistor, a third transistor, a photosensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to both the control terminal and the second terminal. The photosensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal. Attached Figure Description

[0005] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1 This is a circuit diagram of a detection circuit according to an embodiment of the present disclosure;

[0007] Figure 2 According to an embodiment of this disclosure Figure 1 Waveform diagram of the detection circuit;

[0008] Figure 3 This is a circuit diagram of a detection circuit according to another embodiment of the present disclosure;

[0009] Figure 4 According to an embodiment of this disclosure Figure 3 Waveform diagram of the detection circuit;

[0010] Figure 5 This is a circuit diagram of a detection circuit according to another embodiment of the present disclosure;

[0011] Figure 6 According to an embodiment of this disclosure Figure 5 Waveform diagram of the detection circuit;

[0012] Figure 7 This is a circuit diagram of a detection circuit according to another embodiment of the present disclosure;

[0013] Figure 8 According to an embodiment of this disclosure Figure 7 Waveform diagram of the detection circuit;

[0014] Figure 9 This is a circuit diagram of a detection circuit according to another embodiment of the present disclosure;

[0015] Figure 10 According to an embodiment of this disclosure Figure 9 Waveform diagram of the detection circuit;

[0016] Figure 11 This is a circuit diagram of a detection circuit according to another embodiment of the present disclosure; and

[0017] Figure 12 According to an embodiment of this disclosure Figure 11 The waveform diagram of the detection circuit.

[0018] Figure 1-12 The annotations in the attached figures are explained as follows:

[0019] 100, 300, 500, 700, 900, 1100: Detection circuit

[0020] 200, 400, 600, 800, 1000, 1200: Waveform diagram

[0021] 110: Compensation circuit

[0022] 510: First Current Mirror

[0023] 710: Second Current Mirror

[0024] CAP: Capacitor

[0025] M1: First transistor

[0026] M2: Second transistor

[0027] M3: Third transistor

[0028] M4: Fourth transistor

[0029] M5: Fifth Transistor

[0030] M6: Sixth Transistor

[0031] M7: Seventh Transistor

[0032] M8: Eighth transistor

[0033] M9: Ninth Transistor

[0034] M10: Tenth Transistor

[0035] M11: Eleventh Transistor

[0036] LS: Light sensor

[0037] IS: Current source

[0038] NA: First node

[0039] NB: Second Node

[0040] TC: Control Terminal

[0041] T1: First end

[0042] T2: Second end

[0043] VCC1: First supply voltage

[0044] VCC2: Second supply voltage

[0045] VCC3: Third supply voltage

[0046] VREF: Reference Voltage

[0047] COMP: Compensation signal

[0048] RST: Reset signal

[0049] RL: Output impedance

[0050] SW: Switch signal

[0051] VOUT: Output voltage

[0052] SOUT: Output signal

[0053] ID: Current

[0054] ID1: First Current

[0055] ID2: Second current

[0056] ID3: Third Current

[0057] ID4: Fourth Current

[0058] -v(t): Sensing signal

[0059] PRST: Reset Time

[0060] PCOMP: Compensation Time

[0061] PEXP: Exposure Time

[0062] PSCN: Read Time Detailed Implementation

[0063] The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be considered as a limitation thereof. The scope of this disclosure is defined by the claims.

[0064] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, constituent parts, regions, layers, and / or portions, these components, constituent parts, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different components, constituent parts, regions, layers, and / or portions. Therefore, a first component, constituent part, region, layer, and / or portion discussed below may be referred to as a second component, constituent part, region, layer, and / or portion without departing from the teachings of some embodiments of this disclosure.

[0065] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific component examples and arrangements described below are merely for briefly illustrating the spirit of this disclosure and are not intended to limit its scope. Furthermore, the same component symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is solely to provide a simplified and clear explanation and is not intended to limit the relationship between the various embodiments and / or configurations discussed below.

[0066] In some embodiments of this disclosure, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

[0067] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, the endpoints of the components on two circuits are connected by a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components, but are not limited thereto.

[0068] Figure 1 This is a circuit diagram of a detection circuit according to an embodiment of the present disclosure. Figure 1 As shown, the detection circuit 100 includes a capacitor CAP, a first transistor M1, a compensation circuit 110, a second transistor M2, a third transistor M3, a light sensor LS, a fourth transistor M4, and a current source IS. The capacitor CAP is coupled between the first node NA and the second node NB.

[0069] The first transistor M1 includes a control terminal TC, a first terminal T1, and a second terminal T2, wherein the control terminal TC is coupled to the second node NB, and the first terminal T1 receives a first supply voltage VCC1. According to one embodiment of this disclosure, the first transistor M1 is a P-type transistor. A compensation circuit 110 is coupled between a reference voltage VREF and a second supply voltage VCC2, and the compensation circuit 110 is controlled by a compensation signal COMP. According to one embodiment of this disclosure, the compensation circuit 110 is used to provide one of the reference voltage VREF and the second supply voltage VCC2 to the first node NA according to the compensation signal COMP.

[0070] The second transistor M2 is coupled between the second node NB and the third supply voltage VCC3, and the second transistor M2 is controlled by the reset signal RST. According to one embodiment of this disclosure, the second transistor M2 is an N-type transistor. According to one embodiment of this disclosure, the first supply voltage VCC1 is greater than the second supply voltage VCC2, and the second supply voltage VCC2 is greater than the third supply voltage VCC3.

[0071] The third transistor M3 is coupled between the control terminal TC of the first transistor M1 and the second terminal T2, and the third transistor M3 is controlled by the compensation signal COMP. The optical sensor LS is coupled between the third supply voltage VCC3 and the second node NB. According to an embodiment of this disclosure, the third transistor M3 is an N-type transistor.

[0072] The fourth transistor M4 is coupled between the second terminal T2 of the first transistor M1 and the current source IS, and the fourth transistor M4 is controlled by the switching signal SW, wherein an output voltage VOUT is generated between the fourth transistor M4 and the current source IS. According to an embodiment of the present disclosure, the fourth transistor M4 is an N-type transistor.

[0073] like Figure 1As shown, the compensation circuit 110 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 is coupled between the second supply voltage VCC2 and the first node NA, and is controlled by the compensation signal COMP. The sixth transistor M6 is coupled between the reference voltage VREF and the first node NA, and is also controlled by the compensation signal COMP. According to an embodiment of this disclosure, the fifth transistor M5 is an N-type transistor, and the sixth transistor M6 is a P-type transistor.

[0074] According to one embodiment of this disclosure, the detection circuit 100 is located in an electronic device. The electronic device may include a display device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-emissive display device or a self-emissive display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasound, but is not limited thereto. Electronic components may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement and combination of the foregoing, but is not limited thereto. The following description uses display devices as electronic devices or splicing devices to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0075] Figure 2 According to an embodiment of this disclosure Figure 1 The waveform diagram of the detection circuit is shown below. Figure 2 The description of waveform diagram 200 will be accompanied by... Figure 1 The detection circuit 100 is described in detail below.

[0076] According to one embodiment of this disclosure, the detection circuit 100 operates at a reset time PRST, a compensation time PCOMP, an exposure time PEXP, and a readout time PSCN. Before the detection circuit 100 operates at the reset time PRST, the reset signal RST, the compensation signal COMP, and the switch signal SW are all at low logic potentials, making the first node NA the reference voltage VREF, and the voltage potential of the second node NB cannot be determined.

[0077] According to one embodiment of the present disclosure, when the detection circuit 100 operates at the reset time PRST, the reset signal RST is at a high logic potential and turns on the second transistor M2, so that the second transistor M2 provides the third supply voltage VCC3 to the second node NB.

[0078] According to another embodiment of this disclosure, when the detection circuit 100 operates at the compensation time PCOMP, the reset signal RST returns to a low logic potential while the compensation signal COMP is a high logic potential. Therefore, the third transistor M3 and the fifth transistor M5 are turned on according to the high logic potential of the compensation signal COMP, while the sixth transistor M6 is not turned on according to the high logic potential of the compensation signal COMP.

[0079] When the detection circuit 100 operates during the compensation time PCOMP, the third transistor M3 couples the second terminal T2 of the first transistor M1 to the control terminal TC, making the voltage at the second node NB VCC1-VTH, where VTH is the threshold voltage of the first transistor M1. The fifth transistor M5 then provides the second supply voltage VCC2 to the first node NA, making the voltage at the first node NA the second supply voltage VCC2. According to an embodiment of this disclosure, the threshold voltage VTH of the first transistor M1 is stored in the capacitor CAP during the compensation time PCOMP.

[0080] According to another embodiment of this disclosure, when the detection circuit 100 operates at the exposure time PEXP, the compensation signal COMP returns to a low logic potential, causing the third transistor M3 and the fifth transistor M5 to be de-conducted, and the sixth transistor M6 to be turned on. The sixth transistor M6 provides the reference voltage VREF to the first node NA, making the voltage of the first node NA equal to the reference voltage VREF. Since the capacitor CAP stores voltage during the compensation time PCOMP, the voltage of the second node VB is as shown in Formula 1:

[0081] VCC1-VTH-VCC2+VREF (Formula 1)

[0082] At this time, the current ID flowing through the first transistor M1 is as shown in Formula 2:

[0083] ID=k(VCC1-(VCC1-VTH-VCC2+VREF)-VTH) 2 (Formula 2)

[0084] After simplifying Formula 2, the current ID flowing through the first transistor M1 is shown in Formula 3:

[0085] ID = k(VCC2 - VREF) 2 (Formula 3)

[0086] As shown in Formula 3, after the compensation time PCOMP stores the threshold voltage VTH of the first transistor M1 in the capacitor CAP, the current ID flowing through the first transistor M1 is no longer related to the threshold voltage VTH. Therefore, the drift of the threshold voltage VTH no longer affects the current ID flowing through the first transistor M1.

[0087] Assuming the first transistor M1 is an ideal component, its second terminal T2 has an output impedance RL, the transconductance gm of the first transistor M1 and the output impedance is equal to the AC voltage gain AV of the first transistor M1, where the AC voltage gain AV is as shown in Equation 4:

[0088] A V =g m ×RL (Formula 4)

[0089] According to one embodiment of this disclosure, since the transconductance gm of the first transistor M1 is positively correlated with the current ID flowing through the first transistor M1 (as shown in Formula 3), and since the current ID flowing through the first transistor M1 is no longer affected by the threshold voltage VTH, the AC voltage gain AV is not affected by the threshold voltage VTH of the first transistor M1, and the AC voltage gain AV is much greater than 1.

[0090] According to one embodiment of this disclosure, during the exposure time PEXP, after the light sensor LS senses the light, it generates a sensing signal -v(t) at the second node NB, such that the current ID flowing through the first transistor M1 is as shown in Formula 5:

[0091] ID = k(VCC2 - VREF - v(t)) 2 (Formula 5)

[0092] According to another embodiment of this disclosure, when the detection circuit 100 operates at the readout time PSCN, the switch signal SW is at a high logic level, causing the fourth transistor M4 to turn on. Then, the fourth transistor M4 amplifies the sensing signal -v(t) sensed by the optical sensor LS through an AC voltage gain AV, and outputs the output voltage VOUT.

[0093] Figure 3 This is a circuit diagram of a detection circuit according to another embodiment of this disclosure. Figure 3 The detection circuit 300 and Figure 2 Compared to the detection circuit 200, the third transistor M3 of the detection circuit 300 is a P-type transistor, the fifth transistor M5 is coupled between the reference voltage VREF and the first node NA, and the sixth transistor M6 is coupled between the first node NA and the second supply voltage VCC2.

[0094] Figure 4 According to an embodiment of this disclosure Figure 3The waveform diagram of the detection circuit. Figure 4 Waveform diagram 400 and Figure 2 Compared to waveform 200, since the third transistor M3 of the detection circuit 300 is a P-type transistor, the compensation signal COMP is at a low logic potential during the compensation time PCOMP and at a high logic potential at other times.

[0095] Figure 5 This is a circuit diagram of a detection circuit according to another embodiment of this disclosure. Figure 5 Detection circuit 500 and Figure 2 Compared to the detection circuit 200, the fourth transistor M4 of the detection circuit 500 is coupled to the ground terminal, and the detection circuit 500 further includes a first current mirror 510, wherein the first current mirror 510 is coupled to the first terminal T1 of the first transistor M1.

[0096] like Figure 5 As shown, the first current mirror 510 includes a seventh transistor M7 and an eighth transistor M8, both of which are P-type transistors. The seventh transistor M7 is coupled as a diode and is connected between the first supply voltage VCC1 and the first terminal T1 of the first transistor M1. The control terminal of the eighth transistor M8 is coupled to the first terminal T1 of the first transistor M1 and the control terminal of the seventh transistor M7. The first terminal of the eighth transistor M8 is coupled to the first supply voltage VCC1, and the second terminal of the eighth transistor M8 generates an output signal SOUT.

[0097] According to one embodiment of this disclosure, the aspect ratio of the eighth transistor M8 is N times that of the seventh transistor M7. Therefore, the second current ID2 flowing through the eighth transistor M8 is N times the first current ID1 flowing through the seventh transistor M7. In other words, the first current ID1 generated by the first transistor M1 can be amplified by N times to generate a second current ID2 through the first current mirror 510, and the output is the output signal SOUT.

[0098] Figure 6 According to an embodiment of this disclosure Figure 5 The waveform diagram of the detection circuit. Figure 6 Waveform diagram 600 and Figure 2 Since waveform 600 is the same as waveform 200, it will not be described again here.

[0099] Figure 7 This is a circuit diagram of a detection circuit according to another embodiment of this disclosure. Figure 7 The detection circuit 700 and Figure 2Compared to the detection circuit 200, the first terminal T1 of the first transistor M1 receives the first supply voltage VCC1, and the detection circuit 700 further includes a second current mirror 710 and an eleventh transistor M11, wherein the fourth transistor M4 is coupled to the second current mirror 710.

[0100] like Figure 7 As shown, the second current mirror 710 includes a ninth transistor M9 and a tenth transistor M10, both of which are N-type transistors. The ninth transistor M9 is coupled as a diode and is connected between the fourth transistor M4 and ground. The control terminal of the tenth transistor M10 is coupled to the control terminals of the fourth transistor M4 and the ninth transistor M9. The first terminal of the tenth transistor M10 is coupled to the first supply voltage VCC1, and the second terminal of the tenth transistor M10 generates an output voltage VOUT.

[0101] The eleventh transistor M11 is coupled as a diode and is connected between the output voltage VOUT and ground. According to one embodiment of this disclosure, the eleventh transistor M11 is an N-type transistor. According to another embodiment of this disclosure, the aspect ratio of the ninth transistor M9 is M times that of the tenth transistor M10; therefore, the third current ID3 flowing through the ninth transistor M9 is N times the fourth current ID4 flowing through the tenth transistor M10. In other words, the third current ID3 generated by the first transistor M1 can be amplified by M times through the second current mirror 710 to generate a fourth current ID4 that flows through the eleventh transistor M11, thus producing the output voltage VOUT.

[0102] Figure 8 According to an embodiment of this disclosure Figure 7 The waveform diagram of the detection circuit. Figure 8 Waveform diagram 800 and Figure 2 Since waveform diagram 800 is the same as waveform diagram 200, it will not be described again here.

[0103] Figure 9 This is a circuit diagram of a detection circuit according to another embodiment of this disclosure. For example... Figure 9 As shown, the detection circuit 900 includes a capacitor CAP, a first transistor M1, a second transistor M2, a third transistor M3, a light sensor LS, a fourth transistor M4, and a first current mirror 510. The capacitor CAP is coupled between a third node NC and a control signal SC. According to one embodiment of this disclosure, the control signal SC switches between a third supply voltage VCC3 and a reference voltage VREF. According to one embodiment of this disclosure, the reference voltage VREF is greater than the third supply voltage VCC3.

[0104] The first transistor M1 includes a control terminal TC, a first terminal T1, and a second terminal T2, wherein the control terminal TC is coupled to a third node NC. According to one embodiment of this disclosure, the first transistor M1 is a P-type transistor. The second transistor M2 is coupled between a second supply voltage VCC2 and the third node NC, and the second transistor M2 is controlled by a reset signal RST. According to one embodiment of this disclosure, the second transistor M2 is an N-type transistor.

[0105] The third transistor M3 is coupled between the control terminal TC and the second terminal T2 of the first transistor M1, and is controlled by the compensation signal COMP. The optical sensor LS is coupled between the third supply voltage VCC3 and the third node NC. According to one embodiment of this disclosure, the third transistor M3 is an N-type transistor. The fourth transistor M4 is coupled between the second terminal T2 of the first transistor M1 and the ground terminal, and is controlled by the switching signal SW. According to one embodiment of this disclosure, the fourth transistor M4 is an N-type transistor.

[0106] The first current mirror 510 is coupled between the first supply voltage VCC1 and the first terminal T1 of the first transistor M1, and is used to amplify the first current ID1 flowing through the first transistor M1 by N times to become a second current ID2, and output the second current ID2 as the output signal SOUT. The first current mirror 510 is used to... Figure 5 The details are described in the description and will not be repeated here. According to one embodiment of this disclosure, the first supply voltage VCC1 is greater than the second supply voltage VCC2, and the second supply voltage VCC2 is greater than the third supply voltage VCC3.

[0107] Figure 10 According to an embodiment of this disclosure Figure 9 The waveform diagram of the detection circuit is shown below. Figure 10 The description of waveform diagram 1000 will be paired with... Figure 9 The detection circuit 900 is described in detail below.

[0108] According to one embodiment of this disclosure, before the detection circuit 900 operates, the reset signal RST, the compensation signal COMP, and the switch signal SW are at low logic potentials, and the control signal SC is at the third supply voltage VCC3. Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all not turned on, and the voltage potential of the third node NC cannot be determined.

[0109] According to one embodiment of this disclosure, when the detection circuit 900 operates at the reset time PRST, the reset signal RST is at a high logic level, turning on the second transistor M2, causing the second transistor M2 to provide the second supply voltage VCC2 to the third node NC. In other words, at the reset time PRST, the voltage of the third node NC is the second supply voltage VCC2.

[0110] According to another embodiment of this disclosure, when the detection circuit 900 operates during the compensation time PCOMP, the reset signal RST returns to a low logic potential while the compensation signal COMP is at a high logic potential. Therefore, the third transistor M3 is turned on based on the high logic potential of the compensation signal COMP. The third transistor M3 couples the second terminal T2 of the first transistor M1 to the control terminal TC, such that the voltage at the third node NC is VCC1-VTH, where VTH is the threshold voltage of the first transistor M1. According to one embodiment of this disclosure, the threshold voltage VTH of the first transistor M1 is stored in the capacitor CAP during the compensation time PCOMP.

[0111] According to another embodiment of this disclosure, when the detection circuit 900 operates at the exposure time PEXP, the compensation signal COMP returns to a low logic potential, causing the third transistor M3 to de-conduct, and the control signal SC is converted from the third supply voltage VCC3 to the reference voltage VREF. Since the capacitor CAP stores voltage during the compensation time PCOMP, the voltage of the third node VC during the exposure time PEXP is as shown in Equation 6:

[0112] VCC1-VTH-VCC3+VREF (Formula 6)

[0113] At this point, the first current ID1 flowing through the first transistor M1, after being simplified, is as shown in Formula 7:

[0114] ID1 = k(VCC3 - VREF) 2 (Formula 7)

[0115] As shown in Formula 7, after the compensation time PCOMP stores the threshold voltage VTH of the first transistor M1 in the capacitor CAP, the first current ID1 flowing through the first transistor M1 is no longer related to the threshold voltage VTH. Therefore, the drift of the threshold voltage VTH no longer affects the first current ID1 flowing through the first transistor M1.

[0116] According to one embodiment of this disclosure, during the exposure time PEXP, after the light sensor LS senses the light, it generates a sensing signal -v(t) at the third node NC, causing the first current ID1 flowing through the first transistor M1 to be as shown in Formula 8:

[0117] ID1 = k(VCC3 - VREF - v(t)) 2(Formula 8)

[0118] According to another embodiment of this disclosure, when the detection circuit 900 operates at the readout time PSCN, the switch signal SW is at a high logic level, causing the fourth transistor M4 to turn on. Then, the first current mirror 510 amplifies the first current ID1 by a factor of N to become the second current ID2, and outputs the second current ID2 as the output signal SOUT. Therefore, the current generated at the third node NC is also amplified.

[0119] According to one embodiment of this disclosure, since the detection circuit 900 has a smaller number of transistors, the pixel density of the pixel circuit, i.e., pixels per inch (PPI), can be increased.

[0120] Figure 11 This is a circuit diagram of a detection circuit according to another embodiment of this disclosure. Figure 11 The detection circuit 1100 and Figure 9 Compared to the detection circuit 900, the first current mirror 510 of the detection circuit 900 is replaced by a second current mirror 710, and the second current mirror 710 is coupled to the fourth transistor M4, while the first terminal T1 of the first transistor M1 is coupled to the first supply voltage VCC1. The second current mirror 710 has already been... Figure 7 The details are explained in the description, and will not be repeated here.

[0121] like Figure 11 As shown, the second current mirror 710 amplifies the third current ID3 flowing through the first transistor M1 by a factor of M to become the fourth current ID4, and outputs the fourth current ID4 as the output signal SOUT.

[0122] Figure 12 According to an embodiment of this disclosure Figure 11 The waveform diagram of the detection circuit. Figure 12 Waveform diagram 1200 and Figure 10 Since waveform 1200 is the same as waveform 1000, it will not be described again here.

[0123] This invention proposes a detection circuit that uses a capacitor to store the threshold voltage of the transistor to eliminate the influence of the threshold voltage on the current flowing through the transistor and the AC voltage gain. Furthermore, this invention optimizes the transistors in the detection circuit to reduce the number of transistors and helps to improve pixel density.

[0124] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing processes, material compositions, apparatuses, methods, and steps described in the specific embodiments of this specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed processes, machines, manufacturing processes, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing processes, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments.

Claims

1. A sensing circuit, comprising: A first transistor has a control terminal, a first terminal, and a second terminal; A second transistor is coupled to the control terminal; A third transistor is coupled to the control terminal and the second terminal; An optical sensor is coupled to the control terminal; A capacitor is coupled to the control terminal; A fourth transistor is coupled to the second terminal; as well as A compensation circuit is coupled to the capacitor. The compensation circuit includes a fifth transistor and a sixth transistor. The control terminals of the fifth transistor and the sixth transistor are coupled to each other, and a first terminal of the fifth transistor and a second terminal of the sixth transistor are coupled to the capacitor.

2. The sensing circuit as described in claim 1, characterized in that, The first transistor is a P-type transistor.

3. The sensing circuit as described in claim 1, characterized in that, The third transistor is a P-type transistor.

4. The sensing circuit as described in claim 1, characterized in that, The third transistor is an N-type transistor.

5. The sensing circuit as described in claim 1, characterized in that, The fifth transistor is an N-type transistor, and the sixth transistor is a P-type transistor.

6. The sensing circuit as claimed in claim 1, further comprising: A current mirror is coupled to the first terminal of the first transistor.

7. The sensing circuit as claimed in claim 1, further comprising: A current mirror is coupled to the second terminal of the fourth transistor.

8. The sensing circuit as described in claim 1, characterized in that, The capacitor is coupled to a control signal that switches between a supply voltage and a reference voltage, wherein the reference voltage is greater than the supply voltage.

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