Variable gain amplifier

Abstract

A variable gain amplifier for amplifying an input voltage and providing an amplified output voltage includes an input stage including two differential transistor pairs, the input stage coupled to an input of the amplifier. The variable gain amplifier also includes an output stage including a transistor quad and an additional transistor pair, the output stage coupled to an output of the amplifier, the transistor quad including a terminal for receiving a gain control. The variable gain amplifier also includes coupling outputs of the two differential transistor pairs of the input stage to inputs of the transistor quad and additional transistor pair of the output stage to provide a variable gain path and a fixed gain path, respectively. The variable gain amplifier exhibits improved dynamic range of gain variability, lower complexity, and better noise performance.

Description

Technical Field

[0001] This invention generally relates to the field of amplifiers; more specifically, it relates to variable gain amplifiers for enhancing the performance of radio frequency (RF) or analog integrated circuits (ICs) used for signal data processing. Background Technology

[0002] A variable gain amplifier (VGA) is typically defined as an amplifier with adjustable gain. The gain of a VGA is adjusted by controlling either the voltage or the current. VGAs are used when a signal amplification chain requires a gain control mechanism.

[0003] Currently, several topologies have been proposed for variable gain amplifiers, such as the traditional four-quadrant multiplier variable gain amplifier (VGA), the traditional two-stage variable gain amplifier, and the traditional multi-input variable gain amplifier. Each topology of a variable gain amplifier has its own characteristics and limitations. The traditional four-quadrant multiplier VGA consists of an input stage and a quad-core group stage (also known as a Gilbert cell). The gain variability is provided by the quad-core group stage, which consists of a set of four transistor devices (also denoted as Q). a Q b Q' a Q' b The input stage uses a differential input voltage signal and an input transistor pair (also denoted as Q). in+ and Q in- The transconductance gain of the quadrant multiplier is increased, and a differential current signal is generated, which is further controlled by the four-core group stage. In this way, the four-core group stage provides gain variability in the current domain. However, conventional four-quadrant multiplier variable gain amplifiers exhibit limited gain range and various design problems affecting gain range accuracy, control voltage, and noise performance. In the example of the minimum gain configuration, the gain range of the conventional four-quadrant multiplier variable gain amplifier is limited by the four-core group (i.e., Q... a and Q b The effects of offset and mismatch between the four-core pairs. This is because each impairment in the four-core pair results in a limited accuracy of the differential input shunt ratio, which in turn leads to a limited accuracy of the gain range of a conventional four-quadrant multiplier variable gain amplifier. The generation of a stable and controlled voltage is another limitation in achieving high accuracy over the gain range of a conventional four-quadrant multiplier variable gain amplifier. In another example of the maximum gain configuration, due to the inflow transistor (i.e., Q...) bThe gain reduction due to the current generated by the input signal current and the current generated by the control current significantly reduces the noise performance of the conventional four-quadrant multiplier variable gain amplifier. To overcome the limitations of the conventional four-quadrant multiplier variable gain amplifier, a conventional two-stage variable gain amplifier (VGA) and a conventional multi-input variable gain amplifier are proposed. The conventional two-stage variable gain amplifier includes two different input stages, such as a high gain input stage and a low gain input stage. The high gain input stage includes Q1p / n transistors and Re_hg as a degeneration resistor to provide a high gain. The low gain input stage includes Q2p / n transistors and Re_lg as a degeneration resistor and provides a relatively lower gain than the high gain input stage. A plurality of (Q3p / n) transistors form an analog multiplier that works with the high gain and low gain input stages. The plurality of (Q3p / n) transistors are driven by a differential gain control signal (also denoted as Vgcp_h-Vgcn_h, Vgcp_l-Vgcn_l). Depending on the differential gain control signal value, the signal currents generated by the two input stages are mixed in different proportions and provided to a load resistor (e.g., RL), thus, the gain variability is achieved in the conventional two-stage variable gain amplifier. Similarly, the conventional multi-input variable gain amplifier includes n weighted input stages with fixed gains that are combined with a four-core group stage and are driven by n voltage controls derived from Vcontrol. The conventional multi-input variable gain amplifier still exhibits some limitations related to gain range accuracy, control voltage, and noise performance. In the conventional multi-input variable gain amplifier, due to the multi-input stages, the total gain range is obtained by mixing each individual gain range using appropriate control voltages, which is complex and has a lower gain accuracy. Further, a complex circuit is required to generate the plurality of control voltages. From the noise perspective, the transistors in the four-core group stage (or gain variable stage) create multiple paths to the output for various noise sources (such as shot noise, base resistance, etc.) of the active elements and result in gain reduction. Thus, the gain reduction reduces the noise performance of the conventional multi-input variable gain amplifier. Therefore, there is a technical problem of an inefficient variable gain amplifier that exhibits a limited gain range, high complexity, and poor noise performance.

[0004] Therefore, in view of the above discussion, there is a need to overcome the above-mentioned drawbacks associated with the conventional antenna device. SUMMARY

[0005] The present invention seeks to provide an improved variable gain amplifier exhibiting an improved dynamic range of gain variability, lower complexity and improved noise performance. The present invention seeks to provide a solution to the existing problems of inefficient variable gain amplifiers exhibiting a limited range of gain, complexity and poor noise performance. It is an object of the present invention to provide a solution which at least partially overcomes problems encountered in the prior art and to provide an improved variable gain amplifier exhibiting an improved dynamic range of gain variability, lower complexity and improved noise performance.

[0006] The objects of the present invention are achieved by the solutions provided in the independent claims. Advantageous implementations of the present invention are further defined in the dependent claims.

[0007] In one aspect, the present invention provides a variable gain amplifier for amplifying an input voltage and providing an amplified output voltage, comprising:

[0008] an input stage comprising two differential transistor pairs, the input stage being coupled to an input of the amplifier;

[0009] an output stage comprising a transistor quad and an additional transistor pair, the output stage being coupled to an output of the amplifier, the transistor quad comprising a terminal for receiving a gain control signal;

[0010] an output of a first of the differential transistor pairs of the input stage being coupled to an input of the output stage quad to provide a variable gain path between the input of the amplifier and the output of the amplifier controllable by the gain control signal;

[0011] an output of a second of the differential transistor pairs of the input stage being coupled to an input of the additional transistor pair to provide a fixed gain path between the input of the amplifier and the output of the amplifier, the fixed gain path having a gain independent of the gain control signal.

[0012] The variable gain amplifier of the present invention provides a precise gain range by applying the addition or subtraction of the transconductance gain of two differential transistor pairs. The disclosed variable gain amplifier is resilient to any mismatch or damage of the four core set of transistors. The precise gain range provided by the disclosed variable gain amplifier is independent of the absolute value of the gain control signal (or control voltage). Furthermore, in the maximum or minimum gain configuration of the variable gain amplifier, the current steering transistor pair (i.e. the transistor four core set) is completely unbalanced, one of the two devices is turned off. Therefore, in these configurations, the transistor four core set does not contribute to the output noise and makes the noise performance of the variable gain amplifier better. The better noise performance substantially helps to extend the dynamic range of the gain variability of the disclosed variable gain amplifier compared to the conventional four-quadrant multiplier variable gain amplifier. Due to the improved dynamic range of the gain variability, the disclosed variable gain amplifier is suitable for use in a receiver or transmitter of a wired or optical communication system. The disclosed variable gain amplifier also finds practical applications in a transceiver for wireless (e.g. millimeter wave) communication or an analog device with gain variable features.

[0013] In one implementation, the amplifier input is coupled to a control terminal of each transistor in a second one of the differential transistor pairs of the input stage.

[0014] Amplification is obtained at the amplifier input by coupling the amplifier input to a control terminal of each transistor in a second one of the differential transistor pairs of the input stage.

[0015] In another implementation, a control terminal of one of the transistors in a first one of the differential transistor pairs of the input stage is coupled to a control terminal of one of the transistors in a second one of the differential transistor pairs of the input stage, and a control terminal of another of the transistors in the first one of the differential transistor pairs of the input stage is coupled to a control terminal of another of the transistors in the second one of the differential transistor pairs of the input stage.

[0016] Amplification is obtained at the amplifier input by coupling the amplifier input to a control terminal of each transistor in a second one of the differential transistor pairs of the input stage.

[0017] In another implementation, a first current terminal of one of the transistors in a first one of the differential transistor pairs of the input stage is coupled to a first current terminal of another of the transistors in the first one of the differential transistor pairs of the input stage through a first pair of resistive elements.

[0018] A first current terminal of one of the transistors in the first pair of differential transistor pairs of the input stage is coupled through a first pair of resistive elements to a first current terminal of the other transistor in the first pair of differential transistor pairs of the input stage, which provides each transistor in the first differential transistor pair with an amount of automatic biasing required to operate in a common emitter configuration.

[0019] In another implementation, a first current terminal of one of the transistors in the second pair of differential transistor pairs of the input stage is coupled through a second pair of resistive elements to a first current terminal of the other transistor in the second pair of differential transistor pairs of the input stage.

[0020] A first current terminal of one of the transistors in the second pair of differential transistor pairs of the input stage is coupled through a second pair of resistive elements to a first current terminal of the other transistor in the second pair of differential transistor pairs of the input stage, which provides each transistor in the second differential transistor pair with an amount of automatic biasing required to operate in a common emitter configuration.

[0021] In another implementation, a current source is connected between each pair of resistive elements.

[0022] The current source is used to maintain a constant current flow in the circuit of the disclosed variable gain amplifier.

[0023] In another implementation, a bias voltage is used to be applied on the control terminals of the additional transistor pairs of the output stage.

[0024] The bias voltage applied on the control terminals of the additional transistor pairs of the output stage supports the input signal to have a large signal range.

[0025] In another implementation, the transistors are bipolar devices and each transistor of the additional transistor pairs of the output stage has an emitter coupled to a collector of a respective one of the second pair of differential transistor pairs of the input stage.

[0026] It is advantageous to have the transistors as bipolar junction transistors as they facilitate the variable gain amplifier to work in high bandwidth applications. Furthermore, the coupling of each transistor of the additional transistor pairs of the output stage to each transistor of the second pair of differential transistor pairs of the input stage provides a fixed gain path.

[0027] In another implementation, the transistors are field effect devices and each transistor of the additional transistor pairs of the output stage has a source coupled to a drain of a respective one of the second pair of differential transistor pairs of the input stage.

[0028] It is advantageous to use transistors as field effect devices because their infinite input impedance further helps the variable gain amplifier achieve high amplification. In addition, the coupling of each transistor of an additional pair of transistors of the output stage to each transistor of a second pair of differential transistors of the input stage provides a fixed gain path.

[0029] In another implementation, the transistors are bipolar devices, the collector electrodes of the transistor quad of the output stage are coupled together in pairs, one pair of coupled collector electrodes is coupled to the collector electrode of one of the transistors of the additional pair of the output stage, and the other pair of coupled collector electrodes is coupled to the collector electrode of the other transistor of the additional pair of the output stage.

[0030] The collector electrodes of the transistor quad of the output stage are coupled to the collector electrodes of each transistor of the additional pair of the output stage, which provides an amplified output voltage at the pair of output terminals of the variable gain amplifier.

[0031] In another implementation, the transistors are field effect devices, the drain electrodes of the transistor quad of the output stage are coupled together in pairs, one pair of coupled drain electrodes is coupled to the drain electrode of one of the transistors of the additional pair of the output stage, and the other pair of coupled drain electrodes is coupled to the drain electrode of the other transistor of the additional pair of the output stage.

[0032] The drain electrodes of the transistor quad of the output stage are coupled to the drain electrodes of each transistor of the additional pair of the output stage, which provides an amplified output voltage at the pair of output terminals of the variable gain amplifier.

[0033] In another aspect, the present application provides a method of controlling the gain of a variable gain amplifier having a pair of input terminals for receiving a signal to be amplified and a pair of output terminals for providing an amplified output signal. The method includes providing an input signal on the pair of input terminals of the input stage of the amplifier. The method also includes amplifying the input signal using a fixed gain amplification path between the pair of input terminals and the pair of output terminals to provide a fixed gain component of the amplified output signal at the pair of output terminals. The method further includes amplifying the input signal using a variable gain amplification path between the pair of input terminals and the pair of output terminals to provide a variable gain component of the amplified output signal at the pair of output terminals. The method also includes applying a varying gain control signal to the output stage of the variable gain amplifier to vary the gain of the variable gain path to control the size of the amplified output signal.

[0034] The method of the present aspect achieves all the advantages and effects of the variable gain amplifier.

[0035] All steps performed by the various entities described in this application, as well as the functions to be performed by the various entities described, are intended for the respective entities to perform the respective steps and functions. It is understood that the features of this invention are readily combined in various combinations without departing from the scope of the invention as defined by the appended claims.

[0036] Additional aspects, advantages, features, and objects of the invention will become apparent from the accompanying drawings and the detailed description of illustrative implementations as explained in conjunction with the appended claims. Attached Figure Description

[0037] The above-described invention and the following detailed description of illustrative embodiments can be better understood when read in conjunction with the accompanying drawings. Exemplary structures of the invention are shown in the drawings to illustrate the invention. However, the invention is not limited to the specific methods and tools disclosed herein. Where possible, like elements are indicated by like numbers.

[0038] The following figures will now be used as examples to describe embodiments of the present invention.

[0039] Figure 1A This is a circuit diagram of a variable gain amplifier according to an embodiment of the present invention.

[0040] Figure 1B This illustrates an embodiment of the invention. Figure 1A A partial circuit diagram of the operation of a variable gain amplifier in its maximum gain configuration.

[0041] Figure 1C This illustrates an embodiment of the invention. Figure 1A A partial circuit diagram of the operation of a variable gain amplifier in its minimum gain configuration.

[0042] Figure 2 This is a graphical representation of the change in output current of a variable gain amplifier relative to a gain control signal according to an embodiment of the present invention.

[0043] Figure 3 This is a circuit diagram of a variable gain amplifier according to another embodiment of the present invention.

[0044] Figure 4 This is a flowchart of a method for controlling the gain of a variable gain amplifier according to an embodiment of the present invention.

[0045] In the accompanying diagrams, underlined numbers indicate the item in which the underlined number appears or the item adjacent to the underlined number. Ununderlined numbers relate to the item identified by the line that associates the ununderlined number with the item. When a number is ununderlined and has an associated arrow, the ununderlined number is used to identify the general item that the arrow points to. Detailed Implementation

[0046] The following detailed description illustrates embodiments of the application and methods through which can be made and used. Although several modes for carrying out the application have been disclosed, those skilled in the art will recognize that other embodiments of the application can be made and used.

[0047] Figure 1A is a circuit diagram of a variable gain amplifier according to an embodiment of the application. Referring to Figure 1A , a circuit architecture of a variable gain amplifier 100A is shown that includes an input stage 102 and an output stage 104. The input stage 102 includes a first differential transistor pair 106 and a second differential transistor pair 108. The first differential transistor pair 106 includes a first transistor 110 and a second transistor 112. The second differential transistor pair 108 includes a first transistor 114 and a second transistor 116. The input stage 102 receives an input voltage signal 118. The output stage 104 includes a transistor quaternary 120 and an additional transistor pair 122. The transistor quaternary 120 includes a first transistor 124, a second transistor 126, a third transistor 128, and a fourth transistor 130. The additional transistor pair 122 includes a first transistor 132 and a second transistor 134. The output stage 104 provides an output voltage signal 136 on a pair of output terminals 180 and receives a gain control signal 138 (Vagc+ to two terminals, Vagc- to the other terminal). Also shown are a fixed gain path 140, a variable gain path 142, a first pair of resistive elements 144, a second pair of resistive elements 146, a current source 148, and a bias voltage signal 150. The first differential transistor pair 106, the second differential transistor pair 108 of the input stage 102, the transistor quaternary 120, the additional transistor pair 122 of the output stage 104, the first pair of resistive elements 144, the second pair of resistive elements 146 are represented by dashed portions that are for illustration purposes only and do not constitute part of the circuit.

[0048] The variable gain amplifier 100A for amplifying the input voltage signal 118 and providing the amplified output voltage signal 136 includes an input stage 102 that includes two differential transistor pairs, the input stage 102 coupled to the input 118 of the amplifier 100A. The input stage 102 includes a first differential transistor pair 106 and a second differential transistor pair 108 that operate in parallel or anti-parallel together depending on the configuration of the transistor quaternary 120 of the output stage 104. The first differential transistor pair 106 includes a first transistor 110 and a second transistor 112 (also denoted by Q in2+ and Q in2- , respectively). The first transistor 110 and the second transistor 112 in the first differential transistor pair 106 (i.e., Q in2+ and Q in2-Each of these is an npn transistor with three terminals (i.e., base, emitter, and collector). Similarly, the first transistor 114 and the second transistor 116 in the second differential transistor pair 108 (also respectively composed of Q) in1+ and Q in1- (Indicated by) is an npn transistor, which has three terminals: base, emitter, and collector. The input voltage signal is 118 (also represented by V). in (Indicated) is applied to input stage 102. In one implementation, input voltage signal 118 (i.e., V) in ) is a positive amplitude (e.g., V) in / 2 ) and negative amplitude (e.g., -V) in / 2 AC voltage signal. Positive amplitude (i.e., V) in / 2 The negative amplitude (i.e., -V) is applied to the base terminals of the first transistors 110 and 114 in the two differential transistor pairs 106 and 108, respectively. Similarly, the negative amplitude (i.e., -V) is applied to the base terminals of the first transistors 110 and 114 in the two differential transistor pairs 106 and 108. in / 2 The energy is applied to the base terminals of the second transistors 112 and 116 in the two differential transistor pairs that are the first differential transistor pair 106 and the second differential transistor pair 108.

[0049] The variable gain amplifier 100A also includes an output stage 104, which includes a transistor quad 120 and an additional transistor pair 122. The output stage 104 is coupled to the output terminal 136 of the amplifier 100A. The transistor quad 120 includes a terminal for receiving a gain control signal 138. The transistor quad 120 includes a current-guiding section made of a first transistor 124, a second transistor 126, a third transistor 128, and a fourth transistor 130. The first transistor 124 and the fourth transistor 130 (also referred to as Q...) a (represented by), second transistor 126 and third transistor 128 (also referred to as Q). b (Indicated) operates together with additional transistor pair 122 to provide a fixed input-to-output path. Additional transistor pair 122 includes a first transistor 132 and a second transistor 134 (also referred to as Q). c (This is indicated). Thus, output stage 104 becomes a six-device stage, and each transistor in the transistor quad-core 120 and the additional transistor pair 122 is an npn transistor with three terminals (i.e., base, emitter, and collector). Output stage 104 receives gain control signal 138 (also from V). AGC (Representation). Has a positive part (e.g., V). AGC+ The gain control signal 138 is applied to the first transistor 124 and the fourth transistor 130 (i.e., Q). a The base extreme of ). Similarly, those with a negative part (e.g., V) AGC-gain control signal 138 is applied to the base terminals of the second transistor 126 and the third transistor 128 (i.e., Q b The output stage 104 provides an amplified output voltage signal 136.

[0050] In the variable gain amplifier 100A, the output of the first one of the differential transistor pairs of the input stage 102 is coupled to the input of the transistor quad 120 of the output stage to provide a variable gain path 142 between the amplifier input 118 and the amplifier output 136 that is controllable by the gain control signal 138. The output of the first differential transistor pair 106 (i.e., Q in2+ and Q in2- ) of the input stage 102 is coupled as the input of the transistor quad 120 (i.e., Q a and Q b ) of the output stage 104 to provide the variable gain path 142 that is controlled by the gain control signal 138 (i.e., V AGC ). The variable gain path 142 provides a current contribution to the output that is weighted by the gain control signal 138 (i.e., V AGC ). The current contribution provided by the variable gain path 142 is represented by the following equation (Equation 1)

[0051]

[0052] where i in2 is the current contribution provided by the variable gain path 142, g m2 is the transconductance gain of the first differential transistor pair 106 (i.e., Q in2+ and Q in2- ), R deg2 is the degeneration resistance pair, such as the first pair of resistance elements 144 of the first differential transistor pair 106, and V in is the input voltage signal 118.

[0053] In the variable gain amplifier 100A, the output of the second one of the differential transistor pairs of the input stage 102 is coupled to the input of the additional transistor pair 122 to provide a fixed gain path 140 between the amplifier input 118 and the amplifier output 136 that has a gain that is independent of the gain control signal 138. The output of the second differential transistor pair 108 (i.e., Q in1+ and Q in1- ) of the input stage 102 is coupled as the input of the additional transistor pair 122 (i.e., Q c ) of the output stage 104 to provide the fixed gain path 140. The fixed gain path 140 provides a current contribution to the output that is independent of the gain control signal 138 (i.e., V AGC) independent current contribution. The current contribution provided by the fixed gain path 140 is represented by the following equation (Equation 2)

[0054]

[0055] where i in1 is the current contribution provided by the fixed gain path 140, g m1 is the transconductance gain of the second differential transistor pair 108 (i.e., Q in1+ and Q in1- ), R deg1 is the degeneration resistance pair, e.g., the second pair of resistance elements 146 of the second differential transistor pair 108, V in is the input voltage signal 118.

[0056] According to an embodiment, the amplifier input 118 is coupled to the control terminal (base) of each transistor in the second one of the differential transistor pairs of the input stage 102. In one implementation, the input voltage signal 118 (i.e., V in ) is an alternating voltage signal having a positive amplitude (e.g., V in / 2 ) and a negative amplitude (e.g., -V in / 2 ). The positive amplitude (i.e., V in / 2 ) is applied to the control terminal (base) of the first transistor 114 (i.e., Q in1+ ) in the second differential transistor pair 108 of the input stage 102. Similarly, the negative amplitude (i.e., -V in / 2 ) is applied to the control terminal (base) of the second transistor 116 (i.e., Q in1- ) in the second differential transistor pair 108 of the input stage 102.

[0057] According to an embodiment, the control terminal (base) of one of the transistors in the first one 106 of the differential transistor pairs of the input stage 102 is coupled to the control terminal (base) of one of the transistors in the second one 108 of the differential transistor pairs of the input stage 102, and the control terminal (base) of the other transistor in the first one of the differential transistor pairs of the input stage 102 is coupled to the control terminal (base) of the other transistor in the second one of the differential transistor pairs of the input stage 102. In this embodiment, the control terminal (i.e., base terminal) of the first transistor 110 (i.e., Q in2+ ) in the first differential transistor pair 106 is coupled to the control terminal (i.e., base terminal) of the first transistor 114 (i.e., Q in1+ ) in the second differential transistor pair 108. Similarly, the control terminal (i.e., base terminal) of the second transistor 112 (i.e., Q in2- ) in the first differential transistor pair 106 is coupled to the control terminal (i.e., base terminal) of the second transistor 116 (i.e., Q in1-) of the first differential transistor pair 106 (i.e. Q

[0058] According to an embodiment, the first current terminal (emitter) of one of the transistors in the first one of the differential transistor pairs of the input stage 102 is coupled to the first current terminal (emitter) of the other transistor in the first one of the differential transistor pairs of the input stage 102 through a first pair of resistive elements 144. The first current terminal (i.e. emitter terminal) of the first transistor 110 (i.e. Q in2+ ) in the first differential transistor pair 106 of the input stage 102 is coupled to the first current terminal (i.e. emitter terminal) of the second transistor 112 (i.e. Q deg2 ) in the first differential transistor pair 106 of the input stage 102 through the first pair of resistive elements 144 (also denoted by R in2- ) in the first differential transistor pair 106 of the input stage 102 is directly coupled to the first current terminal (i.e. emitter terminal) of the second transistor 112 (i.e. Q in2+ ) in the first differential transistor pair 106 of the input stage 102 in the absence of the first pair of resistive elements 144 (i.e. R deg2 ) in the first differential transistor pair 106 of the input stage 102 is directly coupled to the first current terminal (i.e. emitter terminal) of the second transistor 112 (i.e. Q in2- ) in the first differential transistor pair 106 of the input stage 102.

[0059] According to an embodiment, the first current terminal of one of the transistors in the second one of the differential transistor pairs of the input stage 102 is coupled to the first current terminal of the other transistor in the second one of the differential transistor pairs of the input stage 102 through a second pair of resistive elements 146. The first current terminal (i.e. emitter terminal) of the first transistor 114 (i.e. Q in1+ ) in the second differential transistor pair 108 of the input stage 102 is coupled to the first current terminal (i.e. emitter terminal) of the second transistor 116 (i.e. Q in1- ) in the second differential transistor pair 108 of the input stage 102 through the second pair of resistive elements 146 (also denoted by R deg1 ) in the second differential transistor pair 108 of the input stage 102 is directly coupled to the first current terminal (i.e. emitter terminal) of the second transistor 116 (i.e. Q in1+ ) in the second differential transistor pair 108 of the input stage 102 in the absence of the second pair of resistive elements 146 (i.e. R deg1 ) in the second differential transistor pair 108 of the input stage 102 is directly coupled to the first current terminal (i.e. emitter terminal) of the second transistor 116 (i.e. Q in1-a first current terminal (i.e., an emitter terminal) of the first pair of resistive elements (i.e., R

[0060] According to an embodiment, a current source 148 is connected between each pair of resistive elements. The current source 148 is connected between the first pair of resistive elements 144 (i.e., R deg2 ) and the second pair of resistive elements 146 (i.e., R deg1 ) of the input stage 102 to maintain a constant current throughout the variable gain amplifier 100A. The current source 148 can also be referred to as a constant current source.

[0061] According to an embodiment, a bias voltage 150 is for application on the control terminals of the additional transistor pair 122 of the output stage 104. The bias voltage 150 (also denoted by V bias ) is applied to the control terminals (i.e., base terminals) of the first transistor 132 (i.e., Q c ) and the second transistor 134 (i.e., Q c ) of the additional transistor pair 122 of the output stage 104, respectively.

[0062] According to an embodiment, the transistors are bipolar devices, and each of the additional transistor pair 122 of the output stage 104 has an emitter coupled to the collector of a respective one of the second pair of the differential transistor pair of the input stage 102. In this embodiment, each transistor is a bipolar junction transistor (BJT) or a bipolar device, having three terminals, namely a base, an emitter, and a collector, respectively. The emitter terminal of each of the first transistor 132 (i.e., Q c ) and the second transistor 134 (i.e., Q c ) of the additional transistor pair 122 of the output stage 104 is coupled to the collector terminal of each of the first transistor 114 (i.e., Q in1+ ) and the second transistor 116 (i.e., Q in1- ) of the second differential transistor pair 108 of the input stage 102, respectively.

[0063] According to an embodiment, the transistors are field effect devices, and each of the additional transistor pairs 122 of the output stage 104 has a source coupled to a drain of a respective one of the second differential transistor pair of the input stage 102. In another embodiment, each transistor is a field effect transistor (FET) or field effect device. The field effect transistor (FET) is a junction field effect transistor (JFET) or a metal oxide semiconductor field effect transistor (MOSFET). The field effect transistor (FET) is a three-terminal device having a gate, source, and drain terminal. The source terminal of each of the first transistor 132 (i.e., Q c ) and the second transistor 134 (i.e., Q c ) of the additional transistor pairs 122 of the output stage 104 is coupled to the drain terminal of each of the first transistor 114 (i.e., Q in1+ ) and the second transistor 116 (i.e., Q in1- ) of the second differential transistor pair 108 of the input stage 102, respectively.

[0064] According to an embodiment, the transistors are bipolar devices, and the collector terminals of the transistor quad 120 of the output stage 104 are coupled together in pairs, one pair of coupled collectors being coupled to the collector of one of the transistors of the additional pair 122 of the output stage 104, and another pair of coupled collectors being coupled to the collector of the other transistor of the additional pair 122 of the output stage 104. The transistors of the transistor quad 120 and the additional transistor pairs 122 of the output stage 104 are coupled together. For example, the collector terminals of the first transistor 124 (i.e., Q a ) and the third transistor 128 (i.e., Q b ) of the transistor quad 120 are coupled together and further coupled to the collector terminal of the first transistor 132 (i.e., Q c ) of the additional transistor pair 122 of the output stage 104. Similarly, the collector terminals of the second transistor 126 (i.e., Q b ) and the fourth transistor 130 (i.e., Q a ) of the transistor quad 120 are coupled together and further coupled to the collector terminal of the second transistor 134 (i.e., Q c ) of the additional transistor pair 122 of the output stage 104.

[0065] According to an embodiment, the transistors are field effect devices, and the drains of the transistor quads 120 of the output stage 104 are coupled together in pairs, one pair of coupled drains coupled to the drain of one of the transistors in the additional pair 122 of the output stage 104, and the other pair of coupled drains coupled to the drain of the other transistor in the additional pair 122 of the output stage 104. In another embodiment, each transistor of the transistor quads 120 and the additional pair of transistors 122 of the output stage 104 are field effect devices. The transistors of the transistor quads 120 and the additional pair of transistors 122 of the output stage 104 are coupled together. For example, the drain terminals of the first transistor 124 (i.e., Q a ) and the third transistor 128 (i.e., Q b ) of the transistor quads 120 are coupled together and further coupled to the drain terminal of the first transistor 132 (i.e., Q c ) of the additional pair of transistors 122 of the output stage 104. Similarly, the drain terminals of the second transistor 126 (i.e., Q b ) and the fourth transistor 130 (i.e., Q a ) of the transistor quads 120 are coupled together and further coupled to the drain terminal of the second transistor 134 (i.e., Q c ) of the additional pair of transistors 122 of the output stage 104.

[0066] Accordingly, due to the pairing of the transistor quads 120 and the additional pair of transistors 122 of the input stage 102 and the output stage 104 of the variable gain amplifier 100A, the gain variability is obtained as a combination of the variable gain path 142 and the fixed gain path 140. The gain variability of the variable gain amplifier 100A varies from a maximum value to a minimum value, for example, shown in FIGS. Figure 1B and Figure 1C respectively. In this way, the variable gain amplifier 100A provides an improved dynamic range of gain variability compared to conventional four-quadrant multiplier variable gain amplifiers. Furthermore, the variable gain amplifier 100A provides a precise range of gain by applying the sum or difference of the transconductance gains of the two differential transistor pairs of the input stage 102. The variable gain amplifier 100A is resilient to any mismatch or damage of the quads transistors (i.e., Q a and Q b ). The precise range of gain provided by the variable gain amplifier 100A is independent of the absolute value of the gain control signal 138 (i.e., V AGC ). Furthermore, in the case of the maximum or minimum gain configuration of the variable gain amplifier 100A, the current steering transistor pairs (i.e., the transistor quads 120) are completely unbalanced, and both devices (i.e., Q a and Q b) is turned off. Thus, in these configurations, the transistor quaternary 120 does not affect the output noise and makes the noise performance of the variable gain amplifier 100A better. The better noise performance essentially helps to extend the dynamic range of the gain variability of the variable gain amplifier 100A. Thus, the variable gain amplifier 100A is suitable for use in wired or optical communication systems. The variable gain amplifier 100A can be used in receivers (e.g., transimpedance amplifiers (TIAs)) and transmitters (e.g., drivers) of wired or optical communication systems. Moreover, the variable gain amplifier 100A can be used in transceivers for wireless or millimetre wave (mmW) applications, analog devices including gain- variable features, and the like.

[0067] Figure 1B is a partial circuit diagram showing the operation in the maximum gain configuration of the variable gain amplifier according to an embodiment of the present application. Figure 1A The elements of Figure 1A are described in conjunction with Figure 1B . Referring to Figure 1B , the circuit architecture 100B of the maximum gain configuration of the variable gain amplifier 100A is shown. Figure 1A

[0068] The maximum gain of the variable gain amplifier 100A is represented by the following equation (Equation 3)

[0069]

[0070] In the maximum gain configuration of the variable gain amplifier 100A, the second transistor 126 and the third transistor 128 (i.e., Q b ) of the transistor quaternary 120 of the output stage 104 are completely turned off, and the signal current i in2 generated by the variable gain path 142 flows through the first transistor 124 and the fourth transistor 130 (i.e., Q a ). According to Equation (Equation 4), the output current (also denoted by I out a ) of the variable gain amplifier 100A corresponds to the signal current i a in2

[0071] I out a = i in2 (4)

[0072] The second transistor 126 and the third transistor 128 (i.e., Q b ) of the transistor quaternary 120 are connected to the gain control signal 138 (i.e., V AGC- ​​The low value of ). Therefore, when the gain control signal 138 (i.e., V) AGC+ When ) is high, the first transistor 124 and the fourth transistor 130 (i.e., Q) a Both transistors 126 and 128 (i.e., Q) are in the ON state. b Because it is connected to the gain control signal 138 (i.e., V) AGC- The output current is low and therefore in the off state. Thus, the zero output current (also determined by I) is zero. out b (This indicates that) according to equation (Equation 5), the current flows through the second transistor 126 and the third transistor 128 (i.e., Q). b )

[0073] I out b =0 (5)

[0074] Figure 1C This illustrates an embodiment of the invention. Figure 1A A circuit diagram illustrating the operation of a variable gain amplifier in its minimum gain configuration. Combined with... Figure 1A and Figure 1B Component description Figure 1C . refer to Figure 1C , showed Figure 1A The efficient circuit architecture 100C for the minimum gain condition of the variable gain amplifier 100A.

[0075] The minimum gain of the variable gain amplifier 100A is expressed by the following equation (Equation 6).

[0076]

[0077] In the minimum gain configuration of the variable gain amplifier 100A, the first transistor 124 and the fourth transistor 130 (i.e., Q) of the transistor quad-core group 120 of the output stage 104 a Completely turned off, the signal current i generated by the variable gain path 142 in2 The current flows through the second transistor 126 and the third transistor 128 (i.e., Q). b According to equation (Equation 7), the output current of the variable gain amplifier 100A (also determined by I) out b (Indicated) corresponds to the current flowing through the second transistor 126 and the third transistor 128 (i.e., Q). b ) signal current i in2

[0078] I out b =i in2 (7)

[0079] However, zero output current (also by I)out a represents) flowing through the first transistor 124 and the fourth transistor 130 (i.e., Q a )

[0080] I out a = 0 (8)

[0081] Figure 2 is a graphical representation of the variation of the output current of a variable gain amplifier according to an embodiment of the application with respect to a gain control signal. The elements of Figure 1A , Figure 1B and Figure 1C are described in connection with Figure 2 . Referring to Figure 2 , a graphical representation 200 is shown, including a first graphical representation 200A, a second graphical representation 200B, and a third graphical representation 200C.

[0082] The first graphical representation 200A includes an X-axis 202A and a Y-axis 202B, the X-axis 202A representing a gain control signal, such as the gain control signal 138 (i.e., V AGC ) of Figure 1A , the Y-axis 202B representing a current contribution provided by the fixed gain path 140 of Figure 1A . In the first graphical representation 200A, a first line 204 represents that the current contribution (i.e., i in1 ) provided by the fixed gain path 140 is independent of the gain control signal 138 (i.e., V AGC ). The current contribution (i.e., i in1 ) is independent of positive and negative values of the gain control signal 138 (i.e., V AGC ).

[0083] The second graphical representation 200B includes an X-axis 206A and a Y-axis 206B, the X-axis 206A representing a gain control signal, such as the gain control signal 138 (i.e., V AGC ) of Figure 1A , the Y-axis 206B representing a current contribution provided by the variable gain path 142 of Figure 1A . In the second graphical representation 200B, a first line 208 represents that the current contribution (i.e., i in2 ) provided by the variable gain path 142 is weighted by the gain control signal 138 (i.e., V AGC ) to the output. The current contribution (i.e., i in2 ) provided by the variable gain path 142 varies linearly with respect to the gain control signal 138 (i.e., V AGC ), but after a certain point represented by a second line 210, the current contribution (i.e., i in2 ) varies non-linearly with respect to the gain control signal 138 (i.e., V AGCThe current contribution (i.e., i) provided by the variable gain path 142 becomes saturated. in2 ) Follows the gain control signal 138 (i.e., V) AGC The same behavior for positive and negative values ​​of ).

[0084] The third graphic represents 200C, including representations. Figure 1A Gain control signal 138 (i.e., V) AGC The X-axis represents 212A, and the total output current of the variable gain amplifier 100A is also represented by i. out The Y-axis 212B is represented by the variable gain amplifier 100A. In the third graphic representation 200C, the first line 214 represents the total output current (i.e., i) of the variable gain amplifier 100A. out ) relative to the gain control signal 138 (i.e., V) AGC The total output current (i.e., i) changes linearly until a certain point. out ) is represented by the current distribution provided by the fixed gain path 140 and the variable gain path 142, respectively (i.e., i in1 i in2 The sum or difference of ) . The total output current of the variable gain path 142 (i.e., i out ) relative to the gain control signal 138 (i.e., V) AGC The total output current (i.e., i) changes linearly, but after a certain point represented by the second line 210, the total output current (i.e., i) changes linearly. out ) relative to the gain control signal 138 (i.e., V) AGC It becomes saturated.

[0085] Thus, graphic representation 200 shows the gain control signal 138 (i.e., V) AGC The total output current (i.e., i) is a function of ) out The variation of ) is considered by taking into account the current contribution (i.e., i) provided by the fixed gain path 140 and the variable gain path 142. in1 i in2 Equations (Equations 1 and 2) prove that the gain of the variable gain amplifier 100A varies from its maximum value to its minimum value as expressed by equations (Equations 3 and 6).

[0086] Figure 3 This is a circuit diagram of a variable gain amplifier according to another embodiment of the present invention. (Combined with...) Figure 1A Component description Figure 3 . refer to Figure 3The circuit architecture of a variable gain amplifier 300, including an input stage 302 and an output stage 304, is shown. The input stage 302 includes a first differential transistor pair 306 and a second differential transistor pair 308. The first differential transistor pair 306 includes a first transistor 310 and a second transistor 312. The second differential transistor pair 308 includes a first transistor 314 and a second transistor 316. The input stage 302 also includes an input voltage signal 318. The output stage 304 includes a transistor quad 320 and an additional transistor pair 322. The transistor quad 320 includes a first transistor 324, a second transistor 326, a third transistor 328, and a fourth transistor 330. The additional transistor pair 322 includes a first transistor 332 and a second transistor 334. The output stage 304 also includes an output voltage signal 336 and a gain control signal 338. A current source 340 and a bias voltage signal 342 are also shown. The first differential transistor pair 306 and the second differential transistor pair 308 of the input stage 302, the transistor quad 320 of the output stage 304, and the additional transistor pair 322 are represented by dashed lines. These dashed lines are for illustrative purposes only and do not constitute part of the circuit.

[0087] The variable gain amplifier 300 corresponds to the variable gain amplifier 100A, the difference being that in the variable gain amplifier 300, each transistor (e.g., M) of the input stage 302 and the output stage 304... in2+ M in2- M in1+ M in1- M a M b M c ( ) is a complementary metal-oxide-semiconductor (CMOS) transistor, which has three terminals: gate, source, and drain. However, in ( Figure 1A In the variable gain amplifier 100A, each transistor (e.g., Q) in the input stage 102 and output stage 104 in2+ Q in2- Q in1+ Q in1- Q a Q b Q c It is a bipolar junction transistor (BJT), which has three terminals: base, emitter, and collector. The variable gain amplifier 300 is (…). Figure 1A An alternative implementation of the variable gain amplifier 100A. In the variable gain amplifier 300, each transistor (e.g., M) is a CMOS transistor. in2+ M in2-, M in1+ , M in1- , M a , M b , M c ) have infinite input impedance, which results in high amplification of the input voltage signal 318. Complementary metal oxide semiconductor (CMOS) transistors include P-channel (PMOS) and N-channel (NMOS) transistors. The term MOS in CMOS is an abbreviation for MOSFET (i.e., metal oxide semiconductor field effect transistor). A P-channel MOSFET includes P-type source and drain, both of which are diffused on an N-type substrate, with holes being the majority charge carriers. Similarly, an N-channel MOSFET includes N-type source and drain, both of which are diffused on a P-type substrate, with electrons being the majority charge carriers. In another embodiment, each transistor (e.g., M in2+ , M in2- , M in1+ , M in1- , M a , M b , M c ) of the input stage 302 and the output stage 304 of the variable gain amplifier 300 are bipolar CMOS (BiCMOS) transistors, each having three terminals, namely gate, source, and drain.

[0088] The operation and connection of each transistor (e.g., M in2+ , M in2- , M in1+ , M in1- , M a , M b , M c ) of the input stage 302 and the output stage 304 of the variable gain amplifier 300 are the same as described in detail, for example, in Figure 1A , and therefore are omitted here for brevity.

[0089] Figure 4 is a flowchart of a method of controlling a gain of a variable gain amplifier according to an embodiment of the application. The elements of Figure 1A and Figure 3 are described in conjunction with Figure 4 . Referring to Figure 4 , a method 400 of controlling a gain of a variable gain amplifier (e.g., the variable gain amplifier 100A of Figure 1A or the amplifier 300A of Figure 3 ) is shown. For example, the method 400 is performed by the variable gain amplifier 100A or 300A. The method 400 includes steps 402-408.

[0090] The variable gain amplifier 100A includes a pair of input terminals for receiving a signal to be amplified (e.g., the input voltage signal 118) and a pair of output terminals 180 for providing an amplified output signal, e.g., the output voltage signal 136.

[0091] At step 402, the method 400 includes providing an input signal on a pair of input terminals of an input stage of an amplifier. In the variable gain amplifier 100A, the first differential transistor pair 106 and the second differential transistor pair 108 of the input stage 102 are used to receive the input signal, e.g., the input voltage signal 118.

[0092] At step 404, the method 400 also includes amplifying the input signal using a fixed gain amplification path between the pair of input terminals and a pair of output terminals to provide a fixed gain component of the amplified output signal at the pair of output terminals. In the variable gain amplifier 100A, the second differential transistor pair 108 of the input stage 102 is coupled to the additional transistor pair 122 of the output stage 104 to provide the fixed gain path 140. The fixed gain path 140 provides a current contribution (i in1 ) in amplifying the output signal, e.g., the output voltage signal 136.

[0093] At step 406, the method 400 also includes amplifying the input signal using a variable gain amplification path between the pair of input terminals and the pair of output terminals 180 to provide a variable gain component of the amplified output signal at the pair of output terminals. In the variable gain amplifier 100A, the first differential transistor pair 106 of the input stage 102 is coupled to the transistor quad set 120 of the output stage 104 to provide the variable gain path 142. The variable gain path 142 provides a current contribution (i in2 ) in amplifying the output signal, e.g., the output voltage signal 136.

[0094] At step 408, the method 400 also includes applying a varying gain control signal to an output stage of the variable gain amplifier to vary a gain of the variable gain path to control a size of the amplified output signal. In the variable gain amplifier 100A, the output stage 104 includes the gain control signal 138 used to vary the gain of the variable gain path 142 and further control the amplified output signal 136.

[0095] Steps 402-408 are merely illustrative, and other alternatives can also be provided where one or more steps are added, one or more steps are deleted, or one or more steps are provided in an order different from that described herein without departing from the scope of the claims herein.

[0096] Modifications can be made to the embodiments of the application described above without departing from the scope of the application as defined in the appended claims. Expressions such as "including", "containing", "comprising", "having", "including", "involved in", "may have", "may involve", "comprising", and the like are to be construed to be aptly interpreted in a non-exclusive manner, i.e., allowing for items, components or elements not explicitly described to also be present. References to a single item also should be construed in the plural. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. The word "may" is used herein to mean "can" and "shall." The word "optionally" is used herein to mean "may or can not" and "some embodiments provide and some embodiments do not provide." It will be appreciated that certain features of the application described in the context of separate embodiments can also be provided in combination in a single embodiment. Conversely, various features of the application described in the context of a single embodiment can also be provided separately or in any appropriate sub-combination.

Claims

1. A variable gain amplifier (100A, 300) for amplifying an input voltage (118, 318) and providing an amplified output voltage (136, 336), characterized by, comprises two differential transistor pairs (106, 306, 108, 308), the input stage (102, 302) being coupled to an input (118, 318) of the amplifier (100A, 300); an output stage (104, 304) comprising a transistor quad (120, 320) and an additional transistor pair (122, 322), the output stage (104, 304) being coupled to an output (180, 380) of the amplifier (100A, 300), the transistor quad (120, 320) comprising a terminal for receiving a gain control signal (138, 338); an output of a first one (106, 306) of the differential transistor pairs of the input stage (102, 302) is coupled to an input of the output stage quad (120, 320) to provide a variable gain path (142) between the amplifier input (118, 318) and the amplifier output (136, 336) controllable by the gain control signal (138, 338); an output of a second one (108, 308) of the differential transistor pairs of the input stage (102, 302) is coupled to an input of the additional transistor pair (122, 322) to provide a fixed gain path (140) between the amplifier input (118, 318) and the amplifier output (180, 380) independent of a gain of the gain control signal (138, 338); the transistors are bipolar devices and each of the additional transistor pairs (122, 322) of the output stage (104, 304) has an emitter coupled to a collector of a respective one of the second ones of the differential transistor pairs of the input stage (102, 302); or, the transistors are field effect devices and each of the additional transistor pairs (122, 322) of the output stage (104, 304) has a source coupled to a drain of a respective one of the second ones of the differential transistor pairs of the input stage (102, 302). the amplifier input (118, 318) is coupled to a control terminal of each of the second ones (108, 308) of the differential transistor pairs of the input stage (102, 302).

2. The variable gain amplifier (100A, 300) of claim 1, characterized by a control terminal of one of the first ones (106, 306) of the differential transistor pairs of the input stage (102, 302) is coupled to a control terminal of one of the second ones (108, 308) of the differential transistor pairs of the input stage (102, 302), a control terminal of another of the first ones of the differential transistor pairs of the input stage (102, 302) is coupled to a control terminal of another of the second ones of the differential transistor pairs of the input stage (102, 302).

3. The variable gain amplifier (100A, 300) of claim 2, characterized by ​ 4. The variable gain amplifier (100A, 300) of claim 1, characterized by A first current terminal of one of the transistors in the first pair (106, 306) of the differential transistor pairs of the input stage (102, 302) is coupled to a first current terminal of the other transistor in the first pair of the differential transistor pairs of the input stage (102, 302) by a first pair of resistive elements (144).

5. The variable gain amplifier (100A, 300) of claim 1, characterized by A first current terminal of one of the transistors in the second pair (108, 308) of the differential transistor pairs of the input stage (102, 302) is coupled to a first current terminal of the other transistor in the second pair of the differential transistor pairs of the input stage (102, 302) by a second pair of resistive elements (146).

6. The variable gain amplifier (100A, 300) according to claim 4 or 5, characterized by A current source (148, 340) is connected between each pair of resistive elements.

7. The variable gain amplifier (100A, 300) according to any one of claims 1 to 5, characterized in that A bias voltage (150, 342) is applied to the control terminals of the additional pair (122, 322) of transistors of the output stage (104, 304).

8. The variable gain amplifier (100A, 300) according to any one of claims 1 to 5, characterized in that The transistors are bipolar devices, the collector terminals of the transistor quad (120, 320) of the output stage (104, 304) are coupled together in pairs, one pair of coupled collector terminals being coupled to the collector terminal of one of the transistors in the additional pair (122, 322) of the output stage (104, 304), the other pair of coupled collector terminals being coupled to the collector terminal of the other transistor in the additional pair (122, 322) of the output stage (104, 304).

9. The variable gain amplifier (100A, 300) according to any one of claims 1 to 5, characterized in that The transistors are field effect devices, the drain terminals of the transistor quad (120, 320) of the output stage (104, 304) are coupled together in pairs, one pair of coupled drain terminals being coupled to the drain terminal of one of the transistors in the additional pair (122, 322) of the output stage (104, 304), the other pair of coupled drain terminals being coupled to the drain terminal of the other transistor in the additional pair (122, 322) of the output stage (104, 304).

10. A method (400) of controlling the gain of a variable gain amplifier (100A, 300) according to any one of claims 1 to 9, characterized by, The variable gain amplifier (100A, 300) has a pair of input terminals for receiving a signal (118, 318) to be amplified and a pair of output terminals for providing an amplified output signal (136, 336), the method (400) comprising: providing an input signal (118, 318) at a pair of input terminals of an input stage (102, 302) of the amplifier (100A, 300); amplifying the input signal (118, 318) using a fixed gain amplification path (140) between the pair of input terminals and the pair of output terminals to provide a fixed gain component of the amplified output signal (136, 336) at the pair of output terminals; amplifying the input signal (118, 318) using a variable gain amplification path (142) between the pair of input terminals and the pair of output terminals to provide a variable gain component of the amplified output signal (136, 336) at the pair of output terminals (180, 380); A varying gain control signal is applied to an output stage (104, 304) of the variable gain amplifier (100A, 300) to vary the gain of the variable gain path (142) to control the size of the amplified output signal (136, 336).

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