Ultra-low pass filter and corresponding low dropout linear regulator

Abstract

The present invention belongs to the technical field of power management, and specifically discloses an ultra-low pass filter and a corresponding low dropout linear regulator; among them, the ultra-low pass filter is composed of an RC circuit, a current bias circuit, an enable-controlled operational amplifier, and a timing control circuit for controlling the on / off of the operational amplifier. The present invention also discloses a low dropout linear regulator including the above ultra-low pass filter. The present invention combines an operational amplifier with a traditional RC noise reduction circuit, solves the contradiction between the transient characteristics and the noise reduction ability of the traditional RC noise reduction circuit, and this structure can be applied to various power management chips to reduce the voltage output noise.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management, and relates to an ultra-low pass filter and a corresponding low dropout linear regulator. Background Art

[0002] A low dropout linear regulator (LDO), as an important component of a power management chip, can stabilize the output voltage, suppress the ripple voltage, and eliminate the AC noise generated by the power supply when the AC power supply voltage or the load changes. At the same time, the level of the output noise of the low dropout linear regulator is particularly critical for the frequency of the voltage controlled oscillator (VCO), the phase noise of the frequency source, and the performance of the RF link. Therefore, the low dropout linear regulator with low noise has become a hot research direction for researchers.

[0003] At present, the low dropout linear regulator with low noise designed by the RC noise reduction technology is widely used in electronic communication products. In the RC noise reduction technology, using a large resistor and a large capacitor can filter out the noise with a sufficiently low frequency, which can ensure that the low dropout linear regulator has a low noise output, so that it can be applied to occasions with high noise requirements such as VCO, frequency source circuit, and RF circuit.

[0004] When using RC noise reduction, a field effect transistor (MOS transistor) can be considered as a large resistor and a large capacitor as a noise reduction measure to reduce the noise output. The resistance value of the MOS transistor operating in the deep linear region can reach the G ohm level, and a channel can be formed at the interface between the silicon oxide and silicon of the MOS transistor, thereby exhibiting capacitance characteristics. This technology is widely used in silicon-based integrated circuits. However, simply using a large resistor and a large capacitor for noise reduction will introduce a large time constant, resulting in very poor transient characteristics of the low dropout linear regulator.

[0005] Based on the above situation, someone proposed an RC noise reduction technology with a comparator for speed improvement. For example, "Design of a Low-Noise LDO Integrated in a RF Chip" published by Cai Weicheng in 2017 and included in CNKI publicly introduced the implementation method of a large resistor and a large capacitor, and at the same time used a comparator to improve the response speed, thereby achieving a low noise output on the premise of ensuring the transient characteristics.

[0006] However, the above-mentioned RC noise reduction technology based on the comparator scheme has the following problems: 1. Since the comparator has a flip threshold voltage, process fluctuations between different chips will cause the threshold voltage to fluctuate, so the output voltages between different chips will be different; this phenomenon is particularly obvious under high and low temperature changes, so it is not conducive to the mass production of products; 2. Since the two input voltages of the comparator are equal after the circuit is stable, when there is noise disturbance at one end, it will bring large fluctuations, causing the other end to fluctuate accordingly, affecting the final output voltage, that is, there is a risk of oscillation; 3. The input pair transistors of the comparator have offset voltages. When the circuit is stable, it is reflected that there is a deviation between the two input voltages of the comparator. Similarly, this deviation is particularly prominent under high and low temperatures; 4. Before the output voltage rises to the pre-adjusted voltage, the bias circuit needs to provide a high current to quickly increase the potential of the field effect transistor. After the circuit is stable, the comparator has static power consumption, which is not conducive to the low-power design of the circuit. Summary of the Invention

[0007] An object of the present invention is to provide an ultra-low pass filter, which adopts a stable and low-power RC ultra-low pass filter noise reduction technology, and can reduce the cut-off frequency to filter out ultra-low frequency noise on the premise of ensuring the response speed;

[0008] Another object of the present invention is to provide a low dropout linear regulator including the above ultra-low pass filter.

[0009] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0010] An ultra-low pass filter, characterized in that it is composed of four parts: an RC circuit, a current bias circuit, an enable-controlled operational amplifier, and a timing control circuit for controlling the on and off of the operational amplifier;

[0011] The RC circuit is composed of a large MOS capacitor and a large MOS resistor operating in the deep linear region in series. The source and drain of the MOS transistor used to form the large MOS capacitor are connected together to form one end of the large MOS capacitor, and the gate is used as the other end of the large MOS capacitor;

[0012] The gate of the large MOS resistor is connected to the output end of the current bias circuit; either the source or the drain of the large MOS resistor is connected to the non-inverting input terminal of the operational amplifier, and the other terminal is grounded through the large MOS capacitor;

[0013] The common terminal of the large MOS capacitor and the large MOS resistor is connected to the inverting input terminal of the operational amplifier;

[0014] The non-inverting input terminal of the operational amplifier serves as the input terminal of the ultra-low pass filter, and the inverting input terminal of the operational amplifier serves as the output terminal of the ultra-low pass filter;

[0015] The timing control circuit enables and disables the operational amplifier with single-gain connection;

[0016] When the ultra-low pass filter starts to work, the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier itself; when the input voltage of the ultra-low pass filter is equal to the output voltage, the timing control circuit turns off the operational amplifier, thereby cutting off the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier itself.

[0017] As a limitation, the cut-off frequency of the RC circuit where C represents the equivalent capacitance of the large capacitance of the MOS transistor, and R represents the equivalent resistance of the large resistance of the MOS transistor.

[0018] As a second limitation, the current bias circuit is composed of three or more cascaded current mirror circuits with decreasing mirror current, and the output current of the current bias circuit is an nA-level current.

[0019] As a third limitation, the operational amplifier adopts a two-stage amplification structure; the first-stage amplification structure is a five-transistor operational amplifier structure; the second-stage amplification structure is a common-source amplification structure.

[0020] As a further limitation, the first-stage amplification structure is a five-transistor operational amplifier structure composed of the first MOS transistor to the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor, where the first MOS transistor and the second MOS transistor form an active current mirror; the transconductances of the third MOS transistor and the fourth MOS transistor are equal and serve as differential input pair transistors, the gate of the third MOS transistor is the inverting input terminal of the operational amplifier, and the gate of the fourth MOS transistor is the non-inverting input terminal of the operational amplifier; the sixth MOS transistor and the eighth MOS transistor are connected in series to form a tail current transistor, the drain of the sixth MOS transistor is connected to the source of the third MOS transistor and the source of the fourth MOS transistor, the source of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, and the source of the eighth MOS transistor is grounded;

[0021] The second-stage amplification structure is a common-source amplification structure composed of the fifth MOS transistor, the seventh MOS transistor, and the ninth MOS transistor. The gate of the fifth MOS transistor is connected to the drain of the second MOS transistor. The drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor and serves as the output terminal of the operational amplifier. The source of the seventh MOS transistor is connected to the drain of the ninth MOS transistor, and the source of the ninth MOS transistor is grounded;

[0022] The gates of the sixth MOS transistor and the seventh MOS transistor are connected and connected to the output terminal of the timing control circuit;

[0023] The small-signal voltage gain of the first-stage amplification structure is:

[0024] A V1 = g m3,4 *(R O2 / / R O4 );

[0025] The small-signal voltage gain of the second-stage amplification structure is:

[0026] A V2 = g m5 *(R O5 / / R O9 );

[0027] The voltage gain of the overall operational amplifier is:

[0028] A V = A V1 * A V2 = g m3,4 * g m5 *(R O2 / / R O4 )*(R O5 / / R O9 );

[0029] Where g m3,4 is the transconductance of the third MOS transistor or the fourth MOS transistor, g m5 is the transconductance of the fifth MOS transistor, R O2 is the equivalent output impedance of the second MOS transistor, R O4 is the equivalent output impedance of the fourth MOS transistor, R O5 is the equivalent output impedance of the fifth MOS transistor, R O9 is the equivalent output impedance of the ninth MOS transistor.

[0030] As a fourth limitation, the timing control circuit includes two-stage current charging structures. The output end of the first-stage current charging structure is connected to the input end of the second-stage current charging structure through a first inverter. The timing control circuit controls the charging time of the two-stage current charging structures through current, and enables and disables the operation amplifier connected with negative feedback single gain through the output end of the second-stage charging structure.

[0031] As a further limitation to the timing control circuit, the first-stage current charging structure is composed of the twenty-first MOS transistor and the twenty-fourth MOS transistor, and the second-stage current charging structure is composed of the twenty-second MOS transistor, the twenty-third MOS transistor and the twenty-fifth MOS transistor;

[0032] The gate of the twenty-fourth MOS transistor serves as the output terminal of the first-stage current charging structure, and the gate of the twenty-third MOS transistor serves as the input terminal of the second-stage current charging structure and, at the same time, as the output terminal of the timing control circuit;

[0033] When the ultra-low pass filter starts to work, the output terminal of the timing control circuit outputs a high level, and the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier itself; when the gate voltage of the twenty-fourth MOS transistor is charged to a high level, a low level is output to the gate of the twenty-third MOS transistor through the first inverter, thereby turning on the second-stage current charging structure and, at the same time, outputting a low level to cut off the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier itself.

[0034] The present invention also discloses a low dropout linear regulator, which includes the above-mentioned ultra-low pass filter.

[0035] As a limitation, it further includes a bandgap reference circuit, an error amplifier, a thirtieth MOS transistor, and a current source.

[0036] The bandgap reference circuit is connected to the input terminal of the ultra-low pass filter, the output terminal of the ultra-low pass filter is connected to the inverting input terminal of the error amplifier, the output terminal of the error amplifier is connected to the gate of the thirtieth MOS transistor, the source of the thirtieth MOS transistor serves as the input terminal of the low dropout linear regulator, and the drain of the thirtieth MOS transistor is connected to the non-inverting input terminal of the error amplifier on the one hand and grounded through the current source on the other hand;

[0037] The common terminal of the thirtieth MOS transistor and the error amplifier serves as the output terminal of the low dropout linear regulator.

[0038] Due to the adoption of the above technical solution, compared with the prior art, the technical progress achieved by the present invention lies in:

[0039] (1) The ultra-low pass filter provided by the present invention can reduce its cut-off frequency on the premise of ensuring the response speed to filter out ultra-low frequency noise;

[0040] (2) Under the same noise reduction condition, the circuit response time without using an operational amplifier to speed up is close to the s level, while the response time using the ultra-low pass filter provided by the present invention is in the us order of magnitude;

[0041] (3) Comparing the output noise conditions with and without a noise reduction circuit, when there is no noise reduction circuit, the voltage output noise in the 10 Hz - 100 KHz frequency band is in the mVrms order of magnitude, while after using the ultra-low pass filter provided by the present invention, the voltage output noise in the 10 Hz - 100 KHz frequency band is in the uVrms order of magnitude;

[0042] (4) The present invention adopts a timing control circuit to control the turn-on and turn-off of the operational amplifier at different time periods, so as to improve the transient characteristics on the basis of ensuring the good noise reduction ability of the ultra-low pass filter noise reduction circuit;

[0043] (5) In the present invention, the current bias circuit adopts more than three cascaded current mirror circuits with mirror current reduction, which can gradually reduce the biased current to obtain the required nA-level current. Gradually reducing the current ratio in proportion to reduce the current at one time has the advantage of higher accuracy;

[0044] (6) The present invention combines an operational amplifier with a traditional RC noise reduction circuit and solves the contradiction between the transient characteristics and the noise reduction ability of the traditional RC noise reduction circuit. This structure can be applied to various power management chips to reduce the voltage output noise. Specifically, in the ultra-low pass filter, first, the operational amplifier connected in single-gain negative feedback works, so that the input voltage and the output voltage are equal in a short time; then the operational amplifier is turned off, and only the path passing through the large resistor and the large capacitor is retained for the input and output, thus solving the contradiction between the response speed and the noise of the traditional RC filter;

[0045] (7) For the ultra-low pass filter provided by the present invention, after the output voltage is stable, the tail current bias of the operational amplifier is turned off, which can reduce the power consumption of the overall circuit;

[0046] (8) The low-dropout linear regulator provided by the present invention can be made into a separate chip or integrated as an independent part into a power management chip with high noise requirements, and has a wide range of applications.

[0047] The present invention belongs to the technical field of power management and can reduce the cut-off frequency on the premise of ensuring the response speed to filter out ultra-low frequency noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention.

[0049] In the drawings:

[0050] Figure 1 is the circuit schematic diagram of Embodiment 1 of the present invention;

[0051] Figure 2 a is the circuit schematic diagram of the MOS transistor large resistor of Embodiment 1 of the present invention;

[0052] Figure 2 b is the circuit schematic diagram of the MOS transistor large capacitor of Embodiment 1 of the present invention;

[0053] Figure 3Schematic diagram of the operational amplifier according to Embodiment 1 of the present invention;

[0054] Figure 4 Simplified diagram of the nA-level current bias circuit according to Embodiment 1 of the present invention;

[0055] Figure 5 Schematic diagram of the nA current bias circuit according to Embodiment 1 of the present invention;

[0056] Figure 6 Schematic diagram of the timing control circuit according to Embodiment 1 of the present invention;

[0057] Figure 7 Transient characteristic diagram of the ultra-low pass filter according to Embodiment 1 of the present invention;

[0058] Figure 8 Transient characteristic diagram of the ordinary RC filter circuit according to Embodiment 1 of the present invention;

[0059] Figure 9 Schematic diagram of the circuit according to Embodiment 2 of the present invention;

[0060] Figure 10 Output noise comparison diagram of the low dropout linear regulator with and without the ultra-low pass filter noise reduction circuit according to Embodiment 2 of the present invention. Detailed implementation manners

[0061] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for explaining and illustrating the present invention, and are not used to limit the present invention.

[0062] Embodiment 1 An ultra-low pass filter

[0063] As Figure 1 shown, this embodiment consists of four parts: an RC circuit, a current bias circuit, an enableable operational amplifier, and a timing control circuit for controlling the turn-on and turn-off of the operational amplifier. In the figure, the BIAS module represents the current bias circuit, the OP represents the operational amplifier, and the CTRL represents the timing control circuit.

[0064] The RC circuit is composed of a large MOS capacitor and a large MOS resistor operating in the deep linear region. In order to filter out low-frequency noise in the Hz range, the cut-off frequency of the ultra-low pass filter needs to be low enough, so a large resistor and a large capacitor are required to form the RC circuit. If the resistors and capacitors in the process library are used, the above-mentioned large resistor and large capacitor require a large area. Therefore, in this embodiment, MOS transistors operating in the deep linear region are used to implement resistors in the GHz range, as Figure 2 a shows the schematic diagram of the large MOS resistor in this embodiment; MOS capacitors are used to increase the capacitance per unit area, as Figure 2As shown in Figure b, the circuit schematic diagram of the large capacitor of the MOS transistor in this embodiment is used. The source and drain of the MOS transistor used to form the large capacitor of the MOS transistor are connected together to form one end of the large capacitor of the MOS transistor, and the gate is used as the other end of the large capacitor of the MOS transistor. By changing the voltage of VGS, the size of the large capacitor of the MOS transistor can be changed.

[0065] Combined with Figure 1 and Figure 2 it can be known that the two ends of the large resistor of the MOS transistor are the source and drain of the MOS transistor respectively. Only by controlling the gate voltage of the MOS transistor can the resistance value of the equivalent resistor be changed. By adjusting the gate voltage, the large resistor of the MOS transistor can reach the required GHz level.

[0066] In this embodiment, the cut-off frequency of the RC circuit where C represents the equivalent capacitance of the large capacitor of the MOS transistor, and R represents the equivalent resistance of the large resistor of the MOS transistor.

[0067] The gate of the large resistor of the MOS transistor is connected to the output end of the current bias circuit; either the source or the drain of the large resistor of the MOS transistor is connected to the non-inverting input end of the operational amplifier, and the other end is grounded through the large capacitor of the MOS transistor.

[0068] As Figure 1 shown, the common end of the large capacitor of the MOS transistor and the large resistor of the MOS transistor is connected to the inverting input end of the operational amplifier; the connection and disconnection between the output end of the operational amplifier and its own inverting input end are enabled and controlled by the timing control circuit; the non-inverting input end of the operational amplifier is used as the input end of the ultra-low pass filter, and the inverting input end of the operational amplifier is used as the output end of the ultra-low pass filter.

[0069] In this embodiment, the operational amplifier adopts a two-stage amplification structure as Figure 3 shown; the first-stage amplification structure is a five-transistor operational amplifier structure; the second-stage amplification structure is a common-source amplification structure. The main function of the operational amplifier is to make the output voltage quickly equal to the input voltage to ensure that the entire circuit has good transient characteristics. Its specific internal circuit is as follows Figure 3 shown. Among them, X1 is the enable control part. When X1 is at a high level, the operational amplifier works normally; when X1 is at a low level, the operational amplifier is turned off.

[0070] As Figure 3As shown, the first-stage amplification structure is a five-transistor operational amplifier structure composed of the first MOS transistor to the fourth MOS transistors M1 to M4, the sixth MOS transistor M6, and the eighth MOS transistor M8. Among them, the first MOS transistor M1 and the second MOS transistor M2 form an active current mirror; the transconductances of the third MOS transistor M3 and the fourth MOS transistor M4 are equal and serve as differential input pair transistors. The gate of the third MOS transistor M3 is the inverting input terminal of the operational amplifier, and the gate of the fourth MOS transistor M4 is the non-inverting input terminal of the operational amplifier; the sixth MOS transistor M6 and the eighth MOS transistor M8 are connected in series to form a tail current transistor. The drain of the sixth MOS transistor M6 is connected to the sources of the third MOS transistor M3 and the fourth MOS transistor M4. The source of the sixth MOS transistor M6 is connected to the drain of the eighth MOS transistor M8, and the source of the eighth MOS transistor M8 is grounded.

[0071] The second-stage amplification structure is a common-source amplification structure composed of the fifth MOS transistor M5, the seventh MOS transistor M7, and the ninth MOS transistor M9. The gate of the fifth MOS transistor M5 is connected to the drain of the second MOS transistor M2. The drain of the fifth MOS transistor M5 is connected to the drain of the seventh MOS transistor M7 and serves as the output terminal of the operational amplifier. The source of the seventh MOS transistor M7 is connected to the drain of the ninth MOS transistor M9, and the source of the ninth MOS transistor M9 is grounded. The gates of the sixth MOS transistor M6 and the seventh MOS transistor M7 are connected and connected to the output terminal of the timing control circuit.

[0072] The small-signal voltage gain of the first-stage amplification structure is: A V1 = g m3,4 *(R O2 / / R O4 ); The small-signal voltage gain of the second-stage amplification structure is: A V2 = g m5 *(R O5 / / R O9 ); The overall voltage gain of the operational amplifier is: A V = A V1 * A V2 = g m3,4 * g m5 *(R O2 / / R O4 )*(R O5 / / R O9 ); where g m3,4 is the transconductance of the third MOS transistor M3 or the fourth MOS transistor M4, g m5 is the transconductance of the fifth MOS transistor M5, R O2 is the equivalent output impedance of the second MOS transistor M2, R O4 is the equivalent output impedance of the fourth MOS transistor M4, R O5 is the equivalent output impedance of the fifth MOS transistor M5, R O9is the equivalent output impedance of the ninth MOS transistor M9.

[0073] In this embodiment, a step-by-step mirror current reduction is achieved through a proportional current mirror to provide a bias for the large resistance of the MOS transistor operating in the deep linear region and ensure its operating state. Specifically, the current bias circuit is composed of three cascaded current mirror circuits with mirror current reduction, and the output current of the current bias circuit is an nA-level current. As Figure 4 shown is a simplified diagram of the nA-level current bias circuit. As Figure 5 shown is the circuit schematic diagram of the nA-level current bias circuit.

[0074] Figure 5 In it, VB_P is the bias voltage. The twelfth MOS transistor M12 and the thirteenth MOS transistor M13, the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15, and the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 respectively form current mirrors. By setting the aspect ratio of the twelfth MOS transistor M12 to be greater than that of the thirteenth MOS transistor M13, the aspect ratio of the fourteenth MOS transistor M14 to be greater than that of the fifteenth MOS transistor M15, and the aspect ratio of the sixteenth MOS transistor M16 to be greater than that of the seventeenth MOS transistor M17, the current of the eleventh MOS transistor M11 biased by VB_P can be gradually reduced to obtain the required nA-level current. The multi-stage step-by-step proportional reduction of the current ratio has the advantage of higher precision compared to a large aspect ratio reduction of the current at once. This embodiment only takes three cascaded current mirror circuits with mirror current reduction as an example. In actual circuit design, the number of current mirror circuits with mirror current reduction can be changed according to actual situations, as long as the resulting current is an nA-level.

[0075] As Figure 6 shown is the circuit schematic diagram of the timing control circuit of this embodiment. Its function is to control the turn-on and turn-off of the operational amplifier at different time periods to improve the transient characteristics on the basis of ensuring that the low-pass filter has good noise reduction ability. The gate voltages of the twenty-first MOS transistor M21 and the twenty-second MOS transistor M22 are VB_P. When working normally, they provide corresponding currents to charge the twenty-fourth MOS capacitor M24 and the twenty-fifth MOS capacitor M25 respectively. When the overall circuit is not powered on, the output of X1 is at a low level; then after the power is turned on, the circuit starts to work. When the twenty-first MOS transistor M21 charges the twenty-fourth MOS capacitor M24 until the input voltage of the first inverter N1 is high, a low level is output after passing through the first inverter N1, turning on the twenty-third MOS transistor M23. Thus, the twenty-second MOS transistor M22 charges the twenty-fifth MOS capacitor M25, so X1 is first at a high level and then at a low level. Since X1 controls the turn-on and turn-off of the single-gain-connected operational amplifier, the operational amplifier first works and then disconnects.

[0076] AsFigure 7 This is the transient characteristic diagram of the ultra-low pass filter in this embodiment. Figure 8 This is the transient characteristic of a general RC filter circuit with the same noise reduction effect. Among them, the input ends of both use the same input signal, that is, the signal shown by the IN curve in the figure, and the time for the power-on from 0V to 3.3V is 20us. It can be seen from the output results that the power-on time of the ultra-low pass filter provided in this embodiment is approximately 80us, while the power-on time of the general RC filter circuit is about 500ms. Therefore, under the same conditions, the output of the ultra-low pass filter provided in this embodiment can respond quickly.

[0077] Embodiment 2 A low dropout linear regulator

[0078] As Figure 9 shown, this embodiment includes the ultra-low pass filter shown in Embodiment 1, and also includes a bandgap reference circuit, an error amplifier, the thirtieth MOS transistor M30, and a current source. In the figure, NL represents the ultra-low pass filter, BG represents the bandgap reference circuit, and EA represents the error amplifier.

[0079] The bandgap reference circuit is connected to the input end of the ultra-low pass filter. The output end of the ultra-low pass filter is connected to the inverting input end of the error amplifier. The output end of the error amplifier is connected to the gate of the thirtieth MOS transistor M30. The source of the thirtieth MOS transistor M30 serves as the input end of the low dropout linear regulator. The drain of the thirtieth MOS transistor M30 is connected to the non-inverting input end of the error amplifier on the one hand, and is grounded through the current source on the other hand. The common end of the thirtieth MOS transistor M30 and the error amplifier serves as the output end of the low dropout linear regulator.

[0080] Figure 10 The noise output results of the low dropout linear regulator with and without the ultra-low pass filter noise reduction circuit are compared. Among them, the NOISE_wi_NL curve is the noise result using the ultra-low pass filter noise reduction circuit, and the NOISE_wo_NL curve is the noise result without the ultra-low pass filter noise reduction circuit. It can be seen from the comparison that the role of the ultra-low pass filter noise reduction circuit is obvious, and it has good suppression of noise in the frequency band of 10 - 100KHz.

[0081] Table 1 compares the phase noise values of a frequency source at key frequency points when two low dropout linear regulators with and without the ultra-low pass filter noise reduction circuit supply power to the same frequency source.

[0082] Table 1

[0083]

[0084] As can be seen from Table 1, at key frequency points such as 1KHz, the low-dropout linear regulator with an ultra-low pass filter noise reduction circuit design supplies power to the PLL, and the phase noise of its output is optimized by nearly 30dB compared to the PLL powered by the low-dropout linear regulator without the ultra-low pass filter noise reduction circuit. This also indicates that the cut-off frequency of the ultra-low pass filter noise reduction circuit is low enough to filter out most of the noise; the low-dropout linear regulator designed with it has good noise performance, and this structure can be widely applied to other power management chips to obtain good noise output.

Claims

1. An ultra-low pass filter, characterized in that, it consists of four parts: an RC circuit, a current biasing circuit, an enable-controlled operational amplifier, and a timing control circuit for controlling the on / off of the operational amplifier; The RC circuit is composed of a large MOS capacitor and a large MOS resistor operating in the deep linear region connected in series. The source and drain of the MOS transistor forming the large MOS capacitor are connected together to form one end of the large MOS capacitor, and the gate serves as the other end of the large MOS capacitor; The gate of the large MOS resistor is connected to the output terminal of the current biasing circuit; either the source or the drain of the large MOS resistor is connected to the non-inverting input terminal of the operational amplifier, and the other terminal is grounded through the large MOS capacitor; The common terminal of the large MOS capacitor and the large MOS resistor is connected to the inverting input terminal of the operational amplifier; The non-inverting input terminal of the operational amplifier serves as the input terminal of the ultra-low pass filter, and the inverting input terminal of the operational amplifier serves as the output terminal of the ultra-low pass filter; The timing control circuit enables and controls the on and off of the single-gain-connected operational amplifier; When the ultra-low pass filter starts to work, the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier itself; when the input voltage of the ultra-low pass filter is equal to the output voltage, the timing control circuit turns off the operational amplifier, thereby cutting off the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier itself.

2. The ultra-low pass filter according to claim 1, characterized in that, The cut-off frequency of the RC circuit where C represents the equivalent capacitance of the large capacitance of the MOS transistor, and R represents the equivalent resistance of the large resistance of the MOS transistor.

3. The ultra-low pass filter according to claim 1 or 2, characterized in that, The current biasing circuit is composed of three or more cascaded current mirror circuits with mirror current reduction, and the output current of the current biasing circuit is an nA-level current.

4. The ultra-low pass filter according to claim 1 or 2, characterized in that, The operational amplifier adopts a two-stage amplification structure; the first-stage amplification structure is a five-transistor operational amplifier structure; the second-stage amplification structure is a common-source amplification structure.

5. The ultra-low pass filter according to claim 4, characterized in that, The first-stage amplification structure is a five-transistor operational amplifier structure composed of the first MOS transistor to the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor. Among them, the first MOS transistor and the second MOS transistor form an active current mirror; the transconductances of the third MOS transistor and the fourth MOS transistor are equal and serve as differential input pair transistors. The gate of the third MOS transistor is the inverting input terminal of the operational amplifier, and the gate of the fourth MOS transistor is the non-inverting input terminal of the operational amplifier; the sixth MOS transistor and the eighth MOS transistor are connected in series to form a tail current transistor. The drain of the sixth MOS transistor is connected to the sources of the third MOS transistor and the fourth MOS transistor. The source of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, and the source of the eighth MOS transistor is grounded; The second-stage amplification structure is a common-source amplification structure composed of the fifth MOS transistor, the seventh MOS transistor, and the ninth MOS transistor. The gate of the fifth MOS transistor is connected to the drain of the second MOS transistor. The drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor and serves as the output terminal of the operational amplifier. The source of the seventh MOS transistor is connected to the drain of the ninth MOS transistor, and the source of the ninth MOS transistor is grounded; The gates of the sixth MOS transistor and the seventh MOS transistor are connected and are connected to the output terminal of the timing control circuit; The small-signal voltage gain of the first-stage amplification structure is: A V1 = g m3,4 *(R O2 / / R O4 ); The small-signal voltage gain of the second-stage amplification structure is: A V2 = g m5 *(R O5 / / R O9 ); The voltage gain of the overall operational amplifier is: A V = A V1 * A V2 = g m3,4 * g m5 *(R O2 / / R O4 )*(R O5 / / R O9 ); where g m3,4 is the transconductance of the third or fourth MOS transistor, and g m5 is the transconductance of the fifth MOS transistor, R O2 is the equivalent output impedance of the second MOS transistor, R O4 is the equivalent output impedance of the fourth MOS transistor, R O5 is the equivalent output impedance of the fifth MOS transistor, R O9 is the equivalent output impedance of the ninth MOS transistor.

6. The ultra-low pass filter according to claim 1 or 2, characterized in that the timing control circuit includes two-stage current charging structures. The output terminal of the first-stage current charging structure is connected to the input terminal of the second-stage current charging structure through a first inverter. The timing control circuit controls the charging time of the two-stage current charging structures through current and enables the on and off of the operational amplifier with negative feedback single gain connection through the output terminal of the second-stage charging structure.

7. The ultra-low pass filter according to claim 6, characterized in that: The first-stage current charging structure is composed of the twenty-first MOS transistor and the twenty-fourth MOS transistor, and the second-stage current charging structure is composed of the twenty-second MOS transistor, the twenty-third MOS transistor, and the twenty-fifth MOS transistor; The gate of the twenty-fourth MOS transistor serves as the output terminal of the first-stage current charging structure, and the gate of the twenty-third MOS transistor serves as the input terminal of the second-stage current charging structure and at the same time serves as the output terminal of the timing control circuit; When the ultra-low pass filter starts to work, the output terminal of the timing control circuit outputs a high level, and the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier itself; when the gate voltage of the twenty-fourth MOS transistor is charged to a high level, a low level is output through the first inverter to the gate of the twenty-third MOS transistor, thereby turning on the second-stage current charging structure and at the same time outputting a low level to cut off the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier itself.

8. A low dropout linear regulator, characterized in that it includes the ultra-low pass filter according to any one of claims 1-7.

9. The low dropout linear regulator according to claim 8, characterized in that it further includes a bandgap reference circuit, an error amplifier, a thirtieth MOS transistor, and a current source; The bandgap reference circuit is connected to the input terminal of the ultra-low pass filter. The output terminal of the ultra-low pass filter is connected to the inverting input terminal of the error amplifier. The output terminal of the error amplifier is connected to the gate of the thirtieth MOS transistor. The source of the thirtieth MOS transistor serves as the input terminal of the low dropout linear regulator. The drain of the thirtieth MOS transistor is connected to the non-inverting input terminal of the error amplifier on the one hand and is grounded through a current source on the other hand; The common terminal of the thirtieth MOS transistor and the error amplifier serves as the output terminal of the low dropout linear regulator.

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