Gate drive circuit and display device

Abstract

The present application relates to a gate driving circuit and a display device. According to embodiments of the present disclosure, the gate driving circuit and the display device can include four buffer groups for driving 4k scan lines, two common logic units for controlling the four buffer groups, and a common sensing circuit for controlling output of a sensing driving scan signal to at least one of the 4k scan lines. Thus, the gate driving circuit can be allowed to have a low area structure, and a bezel area of the display device can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the disclosure relate to a gate driving circuit and a display device. BACKGROUND

[0002] As the information society develops, the demand for display devices for displaying images is growing in various forms. In recent years, various display devices (e.g., liquid crystal display devices and organic light emitting display devices) have been utilized.

[0003] For image display, a display device can include a display panel in which a plurality of data lines and a plurality of gate lines are disposed, a data driving circuit that outputs a data signal to the plurality of data lines, and a gate driving circuit that outputs a gate signal to the plurality of gate lines.

[0004] When the size of the display panel or the number and type of the gate lines increase due to various reasons, the size of the gate driving circuit can increase.

[0005] In the display field, the size of the display panel or the number and type of the gate lines increase due to various reasons, and thus the size of the gate driving circuit increases. When the gate driving circuit is embedded in the display panel, the size of the bezel of the display device can increase. Accordingly, the inventors of the disclosure have invented a gate driving circuit and a display device that can be designed in a small area while having a normal driving function. SUMMARY

[0006] Accordingly, embodiments of the disclosure can provide a gate driving circuit and a display device including the same, the gate driving circuit having a low-area structure.

[0007] Embodiments of the disclosure can provide a gate driving circuit and a display device including the same, the gate driving circuit having a low-area structure while normally performing a gate driving operation for sensing mobility of a driving transistor in a sub-pixel.

[0008] According to an embodiment of the disclosure, a gate driving circuit can include: a first scan driving circuit for outputting an n-th scan signal to an n+k-1-th scan signal to n-th scan lines to n+k-1-th scan lines; a second scan driving circuit for outputting an n+k-th scan signal to an n+2k-1-th scan signal to n+k-th scan lines to n+2k-1-th scan lines; a third scan driving circuit for outputting an n+2k-th scan signal to an n+3k-1-th scan signal to n+2k-th scan lines to n+3k-1-th scan lines; a fourth scan driving circuit for outputting an n+3k-th scan signal to an n+4k-1-th scan signal to n+3k-th scan lines to n+4k-1-th scan lines; and a common sensing circuit COM_RTS commonly connected with the first scan driving circuit, the second scan driving circuit, the third scan driving circuit, and the fourth scan driving circuit, and receiving a line selection signal to output a first common control signal and a second common control signal to the first scan driving circuit to the fourth scan driving circuit.

[0009] According to an embodiment of the disclosure, in the gate driving circuit, n can be a natural number of 1 or more, and k can be a natural number of 2 or more. During a sensing driving period, after an input reset signal, one of the first scan driving circuit to the fourth scan driving circuit can output a scan signal to a corresponding scan line of the 4k scan lines.

[0010] According to an embodiment of the disclosure, a display device can include: a display panel including a plurality of scan lines and a plurality of sub-pixels; and a gate driving circuit disposed in a non-display area of the display panel and driving the plurality of scan lines.

[0011] According to an embodiment of the disclosure, a gate driving circuit can include: a first scan driving circuit for outputting an n-th scan signal to an n+k-1-th scan signal to n-th scan lines to n+k-1-th scan lines; a second scan driving circuit for outputting an n+k-th scan signal to an n+2k-1-th scan signal to n+k-th scan lines to n+2k-1-th scan lines; a third scan driving circuit for outputting an n+2k-th scan signal to an n+3k-1-th scan signal to n+2k-th scan lines to n+3k-1-th scan lines; a fourth scan driving circuit for outputting an n+3k-th scan signal to an n+4k-1-th scan signal to n+3k-th scan lines to n+4k-1-th scan lines; and a common sensing circuit COM_RTS commonly connected with the first scan driving circuit, the second scan driving circuit, the third scan driving circuit, and the fourth scan driving circuit, receiving a line selection signal, and outputting a first common control signal and a second common control signal to the first scan driving circuit to the fourth scan driving circuit.

[0012] According to an embodiment of the disclosure, in the gate driving circuit, n can be a natural number of 1 or more, and k can be a natural number of 2 or more. During a sensing driving period, after an input reset signal, one of the first scan driving circuit to the fourth scan driving circuit can output a scan signal to a corresponding scan line of the 4k scan lines.

[0013] According to an embodiment of the disclosure, a gate driving circuit can include: four buffer groups for driving 4k scan lines; two common logic units for controlling the four buffer groups; and a common sensing circuit for controlling output of a sensing driving scan signal to at least one scan line of the 4k scan lines.

[0014] According to an embodiment of the disclosure, a gate driving circuit and a display device including the same can be provided, the gate driving circuit having a low area structure.

[0015] According to an embodiment of the disclosure, a gate driving circuit and a display device including the same can be provided, the gate driving circuit having a low area structure while normally performing a gate driving operation for sensing mobility of a driving transistor in a sub-pixel. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1is a view showing a configuration of a display device according to an embodiment of the present disclosure;

[0018] Figure 2A and Figure 2B is an equivalent circuit diagram showing a sub-pixel of a display device according to an embodiment of the present disclosure;

[0019] Figure 3 is a view showing a system of a display device according to an embodiment of the present disclosure;

[0020] Figure 4 is a view showing a compensation circuit of a display device according to an embodiment of the present disclosure;

[0021] Figure 5A is a diagram showing a first sensing mode of a display device according to an embodiment of the present disclosure;

[0022] Figure 5B is a diagram showing a second sensing mode of a display device according to an embodiment of the present disclosure;

[0023] Figure 6 is a view showing various sensing timings in a display device according to an embodiment of the present disclosure;

[0024] Figure 7 is a diagram schematically showing a gate drive circuit of a display device according to an embodiment of the present disclosure;

[0025] Figure 8 is a view showing a display panel provided with a gate drive circuit in a display device according to an embodiment of the present disclosure;

[0026] Figure 9 and Figure 10 is a block diagram showing a gate drive circuit having a low area structure according to an embodiment of the present disclosure;

[0027] Figure 11 is a view showing a common sensing circuit included in a gate drive circuit having a low area structure according to an embodiment of the present disclosure;

[0028] Figure 12 is a view showing a first scan drive circuit included in a gate drive circuit having a low area structure according to an embodiment of the present disclosure;

[0029] Figure 13 is a view showing a second scan drive circuit included in a gate drive circuit having a low area structure according to an embodiment of the present disclosure;

[0030] Figure 14 is a view showing a third scan drive circuit included in a gate drive circuit having a low area structure according to an embodiment of the present disclosure;

[0031] Figure 15 is a view illustrating a fourth scan driving circuit included in a gate driving circuit having a low area structure according to an embodiment of the present disclosure;

[0032] Figure 16 is a first driving timing diagram of a gate driving circuit having a low area structure according to an embodiment of the present disclosure; and

[0033] Figure 17 is a second driving timing diagram of a gate driving circuit having a low area structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In the following description of examples or embodiments of the present application, reference will be made to the accompanying drawings in which specific examples or embodiments that can be implemented are shown by way of illustration and in which the same reference numerals and symbols can be used to denote the same or similar components even though these components are shown in different drawings from each other. Also, in the following description of examples or embodiments of the present application, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that such descriptions can make the subject matter of some embodiments of the present application rather unclear. Terms such as "include", "have", "contain", "comprise", "consist of", and "consist in" used herein are generally intended to allow addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0035] Terms such as "first", "second", "A", "B", "(A)", or "(B)" can be used herein to describe elements of the present application. Each of these terms is not used to limit the nature, order, sequence, or number of elements, etc., but is used only to distinguish the corresponding element from other elements.

[0036] When it is mentioned that a first element is "connected or coupled" with a second element, "in contact or overlap" with the second element, etc., it should be interpreted that not only the first element can be "directly connected or coupled" or "in direct contact or overlap" with the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled" or "in contact or overlap" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" or "in contact or overlap" with each other.

[0037] When time-related terms such as "after," "subsequently," "next," "before," or the like are used in describing a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacturing, these terms can be used to describe non-continuous or non-sequential processes or operations, unless the terms "directly" or "immediately" are used.

[0038] Furthermore, when any dimensions, relative sizes, and the like are mentioned, it should be considered that the numerical values or corresponding information of elements or features (e.g., horizontal, range, etc.) include a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external impacts, noise, etc.), even if the relevant description is not indicated. In addition, the term "may" completely includes all the meanings of the term "can."

[0039] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a view showing a configuration of a display device 100 according to an embodiment of the present disclosure.

[0041] Referring to Figure 1 The display device 100 according to an embodiment of the present disclosure can include a display panel 110 and a driving circuit for driving the display panel 110.

[0042] The driving circuit can include a data driving circuit 120 and a gate driving circuit 130. The display device 100 can further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

[0043] The display panel 110 can include a substrate SUB and signal lines (e.g., a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate SUB). The display panel 110 can include a plurality of sub-pixels SP connected to the plurality of data lines DL and the plurality of gate lines GL.

[0044] The display panel 110 can include a display area DA in which an image is displayed and a non-display area NDA in which an image is not displayed. In the display panel 110, a plurality of sub-pixels SP for displaying an image can be disposed in the display area DA, and the driving circuit 120, 130 and the controller 140 can be electrically connected or disposed in the non-display area NDA. In addition, a pad unit for connecting an integrated circuit or a printed circuit can be disposed in the non-display area NDA.

[0045] The data driving circuit 120 is a circuit for driving the plurality of data lines DL and can supply data signals to the plurality of data lines DL. The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL and can supply gate signals to the plurality of gate lines GL. The controller 140 can supply a data control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 can supply a gate control signal GCS to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0046] The controller 140 can start scanning according to the timing implemented in each frame, convert input image data input from the outside into image data Data in a format suitable for use in the data driving circuit 120, supply the image data Data to the data driving circuit 120, and control the data driving at an appropriate time suitable for scanning.

[0047] The controller 140 receives various timing signals (including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal) as well as input image data from the outside (e.g., a host system 150).

[0048] To control the data driving circuit 120 and the gate driving circuit 130, the controller 140 receives timing signals (e.g., a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK), generates various control signals DCS and GCS, and outputs the control signals to the data driving circuit 120 and the gate driving circuit 130.

[0049] As an example, to control the gate driving circuit 130, the controller 140 outputs various gate control signals GCS, including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal (GOE).

[0050] To control the data driving circuit 120, the controller 140 outputs various data control signals DCS, including, for example, a source start pulse SSP, a source sampling clock SSC, and a source output enable signal (SOE).

[0051] The controller 140 can be implemented as a component separate from the data driving circuit 120, or the controller 140 can be implemented together with the data driving circuit 120 as an integrated circuit.

[0052] The data driving circuit 120 receives image data Data from the controller 140 and supplies data voltages to the plurality of data lines DL, thereby driving the plurality of data lines DL. The data driving circuit 120 is also referred to as a "source driving circuit".

[0053] The data driving circuit 120 can include one or more source driver integrated circuits (SDICs).

[0054] Each source driver integrated circuit (SDIC) can include a shift register, a latch circuit, a digital-to-analog converter (DAC), and an output buffer. In some cases, each source driver integrated circuit (SDIC) can also include an analog-to-digital converter ADC.

[0055] For example, each source driver integrated circuit (SDIC) can be connected with the display panel 110 through a tape automated bonding (TAB) method, or connected with bonding pads of the display panel 110 through a chip on glass (COG) or chip on board (COP) method, or can be implemented through a chip on film (COF) method and connected with the display panel 110.

[0056] The gate driving circuit 130 can output a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the controller 140. The gate driving circuit 130 can sequentially drive the plurality of gate lines GL by sequentially supplying the gate signal of the on-level voltage to the plurality of gate lines GL.

[0057] The gate driving circuit 130 can be connected with the display panel 110 through a TAB method, or connected with bonding pads of the display panel 110 through a COG or COP method, or can be connected with the display panel 110 according to a COF method. Alternatively, the gate driving circuit 130 can be formed in a gate-in-panel (GIP) type in the non-display area NDA of the display panel 110. The gate driving circuit 130 can be disposed on the substrate SUB or can be connected to the substrate SUB. In other words, the gate driving circuit 130 of the GIP type can be disposed in the non-display area NDA of the substrate SUB. The gate driving circuit 130 of a chip on glass (COG) type or a chip on film (COF) type can be connected to the substrate SUB.

[0058] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 can be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 can be disposed not to overlap with the sub-pixel SP, or to overlap with all or some of the sub-pixels SP. But embodiments of the present disclosure are not limited thereto. For example, both of the data driving circuit 120 and the gate driving circuit 130 can be disposed outside the display area DA.

[0059] When a specific gate line GL is turned on by the gate driving circuit 130, the data driving circuit 120 can convert image data Data received from the controller 140 into an analog data voltage and supply the same to a plurality of data lines DL.

[0060] The data driving circuit 120 can be connected to one side (for example, an upper side or a lower side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the data driving circuit 120 can be connected to both sides (for example, an upper side and a lower side) of the display panel 110, or to two or more sides among four sides of the display panel 110.

[0061] The gate driving circuit 130 can be connected to one side (for example, a left side or a right side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the gate driving circuit 130 can be connected to both sides (for example, a left side and a right side) of the display panel 110, or to two or more sides among four sides of the display panel 110.

[0062] The controller 140 can be a timing controller used in typical display technology, a control device that can perform the function of the timing controller and other control functions, or a control device other than the timing controller, or can be a circuit in the control device. The controller 140 can be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a processor.

[0063] The controller 140 can be mounted on a printed circuit board or a flexible printed circuit, and can be electrically connected with the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit.

[0064] The controller 140 can transmit or receive a signal to or from the data driving circuit 120 according to one or more predetermined interfaces. The interface, for example, can include a low-voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0065] The controller 140 can include a storage medium such as one or more registers.

[0066] The display device 100 according to the embodiment of the disclosure can be a display (for example, a liquid crystal display) including a backlight unit, or can be a self-emissive display (for example, an organic light-emitting diode (OLED) display, a quantum dot display, or a micro light-emitting diode (LED) display).

[0067] If the display device 100 according to the embodiment of the disclosure is an OLED display, each sub-pixel SP can include an organic light emitting diode (OLED) that emits light by itself as a light emitting element. If the display device 100 according to the embodiment of the disclosure is a quantum dot display, each sub-pixel SP can include a light emitting element formed of a quantum dot that is a self-emitting semiconductor crystal. If the display device 100 according to the embodiment of the disclosure is a micro LED display, each sub-pixel SP can include a micro LED that emits light by itself and is formed of an inorganic material as a light emitting element.

[0068] Figure 2A and Figure 2B is an equivalent circuit diagram showing a sub-pixel SP of the display device 100 according to the embodiment of the disclosure.

[0069] Referring to Figure 2A , each of the plurality of sub-pixels SP provided on the display panel 110 of the display device 100 according to the embodiment of the disclosure can include a light emitting element ED, a driving transistor DRT, a scan transistor SCT, and a storage capacitor Cst.

[0070] Referring to Figure 2A , the light emitting element ED can include a pixel electrode PE and a common electrode CE, and can include a light emitting layer EL positioned between the pixel electrode PE and the common electrode CE.

[0071] The pixel electrode PE of the light emitting element ED can be an electrode provided in each sub-pixel SP, and the common electrode CE can be an electrode commonly provided in all sub-pixels SP. Here, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Or conversely, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0072] For example, the light emitting element ED can be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting element.

[0073] The driving transistor DRT is a transistor for driving the light emitting element ED, and can include a first node N1, a second node N2, and a third node N3.

[0074] The first node N1 of the driving transistor DRT can be a gate node of the driving transistor DRT, and can be electrically connected with a source node or a drain node of the scan transistor SCT. The second node N2 of the driving transistor DRT can be a source node or a drain node of the driving transistor DRT, and can be electrically connected with the pixel electrode PE of the light emitting element ED. The third node N3 of the driving transistor DRT can be electrically connected with a driving voltage line DVL that provides a driving voltage EVDD.

[0075] The scan transistor SCT can be controlled by a scan signal SC which is a kind of gate signal, and can be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scan transistor SCT can be turned on or off according to the scan signal SC provided from a scan line SCL which is a kind of gate line, to control the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0076] The scan transistor SCT can be turned on by the scan signal SC having an on-level voltage, and transmit a data voltage Vdata provided from the data line DL to the first node N1 of the driving transistor DRT.

[0077] If the scan transistor SCT is an n-type transistor, the on-level voltage of the scan signal SC can be a high-level voltage. If the scan transistor SCT is a p-type transistor, the on-level voltage of the scan signal SC can be a low-level voltage.

[0078] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of electric charge corresponding to a voltage difference between both ends thereof, and functions to maintain the voltage difference between both ends for a predetermined frame time. Accordingly, during the predetermined frame time, the corresponding sub-pixel SP can emit light.

[0079] Referring to Figure 2B Each of the plurality of sub-pixels SP provided on the display panel 110 of the display apparatus 100 according to the embodiment of the disclosure can further include a sensing transistor SENT.

[0080] The sensing transistor SENT can be controlled by a sensing signal SE which is a kind of gate signal, and can be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. In other words, the sensing transistor SENT can be turned on or off according to the sensing signal SE provided from a sensing signal line SENL which is another type of gate line, to control the connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0081] The sensing transistor SENT can be turned on by the sensing signal SE having an on-level voltage, and transmit a reference voltage Vref provided from the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0082] The sensing transistor SENT can be turned on by the sensing signal SE having an on-level voltage, and transmit a reference voltage Vref provided from the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0083] If the sensing transistor SENT is an n-type transistor, the on-level voltage of the sensing signal SE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-level voltage of the sensing signal SE can be a low-level voltage.

[0084] The function of the sensing transistor SENT to transfer the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used when driving to sense the characteristic value of the sub-pixel SP. In this case, the voltage transferred to the reference voltage line RVL can be a voltage for calculating the characteristic value of the sub-pixel SP or a voltage reflecting the characteristic value of the sub-pixel SP.

[0085] In the disclosure, the characteristic value of the sub-pixel SP can be a characteristic value of the driving transistor DRT or the light emitting element ED. The characteristic value of the driving transistor DRT can include a threshold voltage and mobility of the driving transistor DRT. The characteristic value of the light emitting element ED can include a threshold voltage of the light emitting element ED.

[0086] Each of the driving transistor DRT, the scan transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In the disclosure, for convenience of description, each of the driving transistor DRT, the scan transistor SCT, and the sensing transistor SENT is an n-type transistor.

[0087] The storage capacitor Cst is not a parasitic capacitor (for example, Cgs or Cgd) that is an internal capacitor existing between the gate node and the source node (or the drain node) of the driving transistor DRT, but can be an external capacitor intentionally designed outside the driving transistor DRT.

[0088] The scan line SCL and the sensing signal line SENL can be different gate lines GL. In this case, the scan signal SC and the sensing signal SE can be separate gate signals, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be independent. In other words, the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be the same or different.

[0089] Alternatively, the scan line SCL and the sensing signal line SENL can be the same gate line GL. In other words, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP can be connected to one gate line GL. In this case, the scan signal SC and the sensing signal SE can be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP can be the same.

[0090] Figure 2A and Figure 2B The structure of the sub-pixel SP shown is merely an example, and various changes can be made thereto, for example, including one or more transistors or one or more capacitors.

[0091] Although the display device 100 is assumed to be a self-emissive display device, the sub-pixel structure will be described in connection with Figure 2A and Figure 2B However, if the display device 100 is a liquid crystal display, each sub-pixel SP can include a transistor and a pixel electrode.

[0092] Figure 3 is a view showing a system of the display device 100 according to an embodiment of the disclosure.

[0093] Referring to Figure 3 , the display panel 110 can include a display area DA in which an image is displayed and a non-display area NDA in which an image is not displayed.

[0094] Referring to Figure 3 When the data driving circuit 120 includes one or more source driver integrated circuits SDIC and is implemented in a chip on film (COF) type, each source driver integrated circuit SDIC can be mounted on a circuit film SF connected to the non-display area NDA of the display panel 110.

[0095] Referring to Figure 3 , the gate driving circuit 130 can be implemented in a gate in panel (GIP) type. In this case, the gate driving circuit 130 can be formed in the non-display area NDA of the display panel 110. Unlike Figure 3 , the gate driving circuit 130 can be implemented in a chip on film (COF) type.

[0096] The display device 100 can include at least one source printed circuit board SPCB for circuit connection between the one or more source driver integrated circuits SDIC and other devices, and a control printed circuit board CPCB for mounting control components and various electronic devices.

[0097] The source driver integrated circuit SDIC packaging film SF can be connected to the at least one source printed circuit board SPCB. In other words, one side of the source driver integrated circuit SDIC packaging film SF can be electrically connected with the display panel 110, and the opposite side thereof can be electrically connected with the source printed circuit board SPCB.

[0098] The controller 140 and a power management integrated circuit (PMIC) 310 can be mounted on a control printed circuit board CPCB. The controller 140 can perform an overall control function related to driving of the display panel 110, and can control operations of the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 310 can supply various voltages or currents to the data driving circuit 120 and the gate driving circuit 130, or can control various voltages or currents to be supplied thereto.

[0099] The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be electrically connected by at least one connection cable CBL. Here, the connection cable CBL can be, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC).

[0100] The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be integrated into one printed circuit board.

[0101] The display device 100 according to the embodiment of the disclosure can further include a level shifter 300 for adjusting a voltage level. For example, the level shifter 300 can be disposed on the control printed circuit board CPCB or the source printed circuit board SP CB.

[0102] Specifically, in the display device 100 according to the embodiment of the disclosure, the level shifter 300 can supply a signal required for gate driving to the gate driving circuit 130. For example, the level shifter 300 can supply a plurality of clock signals to the gate driving circuit 130. Accordingly, the gate driving circuit 130 can output a plurality of gate signals to a plurality of gate lines GL based on the plurality of clock signals input from the level shifter 300. The plurality of gate lines GL can transmit the plurality of gate signals to the sub-pixels SP disposed in the display area DA of the substrate SUB.

[0103] Figure 4 FIG. 4 is a view illustrating a compensation circuit of the display device 100 according to the embodiment of the disclosure.

[0104] Referring to Figure 4 The compensation circuit is a circuit capable of sensing and compensating for characteristic values of circuit elements in the sub-pixel SP.

[0105] The compensation circuit can be connected to the sub-pixel SP, and can include a power switch SPRE, a sampling switch SAM, an analog-to-digital converter ADC, and a compensator 400.

[0106] The power switch SPRE can control connection between the reference voltage line RVL and the reference voltage supply node Nref. The reference voltage Vref output from the power supply can be provided to the reference voltage supply node Nref, and the reference voltage Vref provided to the reference voltage supply node Nref can be applied to the reference voltage line RVL through the power switch SPRE.

[0107] The sampling switch SAM can control connection between the analog-digital converter ADC and the reference voltage line RVL. If connected to the reference voltage line RVL through the sampling switch SAM, the analog-digital converter ADC can convert the voltage (analog voltage) of the connected reference voltage line RVL into a sensing value corresponding to a digital value.

[0108] The line capacitor Crvl can be formed between the reference voltage line RVL and the ground GND. The voltage of the reference voltage line RVL can correspond to the amount of charge of the line capacitor Crvl.

[0109] The analog-digital converter ADC can provide sensing data including the sensing value to the compensator 400.

[0110] The compensator 400 can find out a characteristic value of the light emitting element ED or the driving transistor DRT included in the corresponding sub-pixel SP based on the sensing data, calculate a compensation value, and store it in the memory 410.

[0111] For example, the compensation value is information for reducing a characteristic value deviation between the light emitting elements ED or a characteristic value deviation between the driving transistors DRT, and can include an offset and a gain value for data change.

[0112] The display controller 140 can change the image data using the compensation value stored in the memory 410, and can provide the changed image data to the data driving circuit 120.

[0113] The data driving circuit 120 can convert the changed image data into a data voltage Vdata corresponding to an analog voltage using a digital-analog converter DAC, and output the data voltage Vdata. Accordingly, compensation can be implemented.

[0114] Referring Figure 4 , the analog-digital converter ADC, the power switch SPRE, and the sampling switch SAM can be included in a source driver integrated circuit SDIC included in the data driving circuit 120. The compensator 400 can be included in the display controller 140.

[0115] As described above, the display apparatus 100 according to the embodiment of the disclosure can perform a compensation process to reduce a characteristic value deviation between the driving transistors DRT. To perform the compensation process, the display apparatus 100 can perform a sensing drive to detect the characteristic value deviation between the driving transistors DRT.

[0116] The display device 100 according to the embodiment of the disclosure can perform the sensing driving in two modes (fast mode and slow mode). Hereinafter, the sensing driving in the two modes (fast mode and slow mode) is described with reference to Figure 5A and Figure 5B .

[0117] Figure 5A is a diagram illustrating a first sensing mode S-Mode of the display device 100 according to the embodiment of the disclosure. Figure 5B is a diagram illustrating a second sensing mode F-Mode of the display device 100 according to the embodiment of the disclosure.

[0118] Referring to Figure 5A , the first sensing mode S-Mode is a sensing driving mode for slowly sensing a characteristic value (e.g., threshold voltage) that requires a longer driving time among characteristic values (e.g., threshold voltage and mobility) of the driving transistor DRT. The first sensing mode S-Mode can also be referred to as a slow mode or a threshold voltage sensing mode.

[0119] Referring to Figure 5B , the second sensing mode F-Mode is a sensing driving mode for quickly sensing a characteristic value (e.g., mobility) that requires a shorter driving time among characteristic values (e.g., threshold voltage and mobility) of the driving transistor DRT. The second sensing mode F-Mode can also be referred to as a fast mode or a mobility sensing mode.

[0120] Referring to Figure 5A and Figure 5B , the sensing driving period of the first sensing mode S-Mode and the sensing driving period of the second sensing mode F-Mode can each include an initialization period Tinit, a tracking period Ttrack, and a sampling period Tsam. Hereinafter, the first sensing mode S-Mode and the second sensing mode F-Mode are described separately.

[0121] Hereinafter, the sensing driving period of the first sensing mode S-Mode of the display device 100 is described with reference to Figure 5A .

[0122] Referring to Figure 5A , the initialization period Tinit of the sensing driving period of the first sensing mode S-Mode is a period for initializing the first node N1 and the second node N2 of the driving transistor DRT.

[0123] During the initialization period Tinit, the voltage V1 of the first node N1 of the drive transistor DRT can be initialized to the sense drive data voltage Vdata_SEN, and the voltage V2 of the second node N2 of the drive transistor DRT can be initialized to the sense drive reference voltage Vref.

[0124] During the initialization period Tinit, the scan transistor SCT and the sense transistor SENT can be turned on, and the power switch SPRE can be turned on.

[0125] Referring to Figure 5A The tracking period Ttrack of the sense drive period of the first sense mode S-Mode is a period for tracking the voltage V2 of the second node N2 of the drive transistor DRT reflecting the threshold voltage Vth of the drive transistor DRT or a change thereof.

[0126] During the tracking period Ttrack, the power switch SPRE can be turned off, or the sense transistor SENT can be turned off.

[0127] Therefore, during the tracking period Ttrack, the first node N1 of the drive transistor DRT is in a constant voltage state with the sense drive data voltage Vdata_SEN, but the second node N2 of the drive transistor DRT can be in an electrically floating state. Therefore, during the tracking period Ttrack, the voltage V2 of the second node N2 of the drive transistor DRT can vary.

[0128] During the tracking period Ttrack, the voltage V2 of the second node N2 of the drive transistor DRT can increase until the voltage V2 of the second node N2 of the drive transistor DRT reflects the threshold voltage Vth of the drive transistor DRT.

[0129] During the initialization period Tinit, the voltage difference between the initialized first node N1 and the second node N2 of the drive transistor DRT can be the threshold voltage Vth of the drive transistor DRT or more. Therefore, when the tracking period Ttrack starts, the drive transistor DRT is in an on state and conducts current. Therefore, if the tracking period Ttrack starts, the voltage V2 of the second node N2 of the drive transistor DRT can increase.

[0130] During the tracking period Ttrack, the voltage V2 of the second node N2 of the drive transistor DRT increases unstably.

[0131] At the end of the tracking period Ttrack, the voltage increase of the second node N2 of the drive transistor DRT can decrease, and as a result, the voltage V2 of the second node N2 of the drive transistor DRT can saturate.

[0132] The voltage V2 of the second node N2 of the driving transistor DRT saturated can correspond to a difference Vdata_SEN-Vth between the data voltage Vdata_SEN and the threshold voltage Vth or a difference Vdata_SEN-ΔVth between the data voltage Vdata_SEN and the threshold voltage deviation ΔVth. Here, the threshold voltage Vth can be a negative threshold voltage (Negative Vth) or a positive threshold voltage (Positive Vth).

[0133] If the voltage V2 of the second node N2 of the driving transistor DRT is saturated, the sampling period Tsam of the sensing driving period of the first sensing mode S-Mode can be started.

[0134] Referring to Figure 5A , the sampling period Tsam of the sensing driving period of the first sensing mode S-Mode is a period for measuring a voltage (Vdata_SEN-Vth, Vdata_SEN-ΔVth) reflecting the threshold voltage Vth of the driving transistor DRT or a change thereof.

[0135] The sampling period Tsam of the sensing driving period of the first sensing mode S-Mode is a step of sensing a voltage of a reference voltage line RVL of an analog-digital converter ADC. The voltage of the reference voltage line RVL can correspond to the voltage V2 of the second node N2 of the driving transistor DRT, and to a charging voltage of a line capacitor Crvl formed in the reference voltage line RVL.

[0136] During the sampling period Tsam, the voltage Vsen sensed by the analog-digital converter ADC is a voltage Vdata_SEN-Vth as the data voltage Vdata_SEN minus the threshold voltage Vth, or a voltage Vdata_SEN-ΔVth as the data voltage Vdata_SEN minus the threshold voltage deviation ΔVth. Here, Vth can be a positive threshold voltage or a negative threshold voltage.

[0137] Referring to Figure 5A , during the tracking period Ttrack of the sensing driving period of the first sensing mode S-Mode, the saturation time Tsat used for the voltage V2 of the second node N2 of the driving transistor DRT to increase and saturate can be a time length of the tracking period Ttrack of the sensing driving period of the first sensing mode S-Mode, and can be a time used for the threshold voltage Vth of the driving transistor DRT or a change thereof to be reflected to the voltage V2 of the second node N2 of the driving transistor DRT (V2=Vdata_SEN-Vth).

[0138] The saturation time Tsat can occupy a large portion of the total length of the sensing driving period of the first sensing mode S-Mode. In the first sensing mode S-Mode, the voltage V2 of the second node N2 of the driving transistor DRT increases and saturation can take a considerable amount of time (saturation time: Tsat).

[0139] As described above, the sensing driving scheme for sensing the threshold voltage of the driving transistor DRT requires a long saturation time Tsat until the voltage state of the second node N2 of the driving transistor DRT indicates the threshold voltage of the driving transistor DRT, and thus is called a slow mode (first sensing mode S-Mode).

[0140] Referring to Figure 5B A sensing driving period of a second sensing mode F-Mode of the display apparatus 100 is described.

[0141] Referring to Figure 5B The initialization period Tinit of the sensing driving period of the second sensing mode F-Mode is a period for initializing the first node N1 and the second node N2 of the driving transistor DRT.

[0142] During the initialization period Tinit, the scan transistor SCT and the sensing transistor SENT can be turned on, and the power switch SPRE can be turned on.

[0143] During the initialization period Tinit, the voltage V1 of the first node N1 of the driving transistor DRT can be initialized to the sensing driving data voltage Vdata_SEN, and the voltage V2 of the second node N2 of the driving transistor DRT can be initialized to the sensing driving reference voltage Vref.

[0144] Referring to Figure 5B The tracking period Ttrack of the sensing driving period of the second sensing mode F-Mode is a period during which the voltage V2 of the second node N2 of the driving transistor DRT is changed within a preset tracking time Δt until the voltage V2 of the second node N2 of the driving transistor DRT becomes a voltage state reflecting the mobility or mobility variation of the driving transistor DRT.

[0145] During the tracking period Ttrack, the preset tracking time Δt can be set to be short. Thus, during the short tracking time Δt, the voltage V2 of the second node N2 of the driving transistor DRT can hardly reflect the threshold voltage Vth. However, during the short tracking time Δt, the voltage V2 of the second node N2 of the driving transistor DRT can be changed to an extent that the mobility of the driving transistor DRT can be calculated.

[0146] Accordingly, the second sensing mode F-Mode is a sense drive scheme for sensing mobility of the drive transistor DRT.

[0147] In the tracking period Ttrack, the second node N2 of the drive transistor DRT can become electrically floating as the power switch SPRE is turned off or the sense transistor SENT is turned off.

[0148] During the tracking period Ttrack, the scan transistor SCT can be in an off state by the scan signal SC of the turn-off level voltage, and the first node N1 of the drive transistor DRT can be in a floating state.

[0149] During the initialization period Tinit, the voltage difference between the first node N1 and the second node N2 of the initialized drive transistor DRT can be the threshold voltage Vth of the drive transistor DRT or more. Accordingly, when the tracking period Ttrack starts, the drive transistor DRT is in an on state and conducts current.

[0150] If the first node N1 and the second node N2 of the drive transistor DRT are a gate node and a source node, respectively, the voltage difference between the first node N1 and the second node N2 of the drive transistor DRT becomes Vgs.

[0151] Accordingly, during the tracking period Ttrack, the voltage V2 of the second node N2 of the drive transistor DRT can increase. In this case, the voltage V1 of the first node N1 of the drive transistor DRT can also increase.

[0152] During the tracking period Ttrack, the growth rate of the voltage V2 of the second node N2 of the drive transistor DRT varies depending on the current capability (i.e., mobility) of the drive transistor DRT. As the current capability (mobility) of the drive transistor DRT increases, the voltage V2 of the second node N2 of the drive transistor DRT can further sharply increase.

[0153] After the tracking period Ttrack proceeds for a preset tracking time Δt (i.e., after the voltage V2 of the second node N2 of the drive transistor DRT rises during the preset tracking time Δt), a sampling period Tsam can be performed.

[0154] During the tracking period Ttrack, the growth rate of the voltage V2 of the second node N2 of the drive transistor DRT corresponds to the voltage change ΔV of the second node N2 of the drive transistor DRT during the preset tracking time Δt. The voltage change ΔV of the second node N2 of the drive transistor DRT can correspond to the voltage change of the reference voltage line RVL.

[0155] Referring to Figure 5BAfter the preset tracking time Δt is performed in the tracking period Ttrack, a sampling period Tsam can be started. During the sampling period Tsam, the sampling switch sam can be turned on so that the reference voltage line RVL and the analog-to-digital converter ADC can be electrically connected to each other.

[0156] The analog-to-digital converter ADC can sense the voltage of the reference voltage line RVL. The voltage Vsen sensed by the analog-to-digital converter ADC can be a voltage Vref+ΔV that is the reference voltage Vref plus an increment (i.e., a voltage change ΔV) during the preset tracking time Δt.

[0157] The voltage Vsen sensed by the analog-to-digital converter ADC can be the voltage of the reference voltage line RVL and can be the voltage of the second node N2 to which the sensing transistor SENT is electrically connected to the reference voltage line RVL.

[0158] Referring to Figure 5B In the sampling period Tsam of the sensing driving period of the second sensing mode F-Mode, the voltage Vsen sensed by the analog-to-digital converter ADC can vary depending on the mobility of the driving transistor DRT. As the mobility of the driving transistor DRT increases, the sensing voltage Vsen increases. As the mobility of the driving transistor DRT decreases, the sensing voltage Vsen decreases.

[0159] As described above, the sensing driving scheme for sensing the mobility of the driving transistor DRT can change the voltage of the second node N2 of the driving transistor DRT only for a short time Δt, and thus is referred to as a fast mode (second sensing mode F-Mode).

[0160] Referring to Figure 5A According to the display device 100 of the embodiment of the disclosure, the threshold voltage Vth or a change thereof of the driving transistor DRT in the corresponding sub-pixel SP can be calculated based on the voltage Vsen sensed through the first sensing mode S-Mode, a threshold voltage compensation value that reduces or eliminates the threshold voltage deviation between the driving transistors DRT can be calculated, and the calculated threshold voltage compensation value can be stored in the memory 410.

[0161] Referring to Figure 5B According to the display device 100 of the embodiment of the disclosure, the mobility or a change thereof of the driving transistor DRT in the corresponding sub-pixel SP can be calculated based on the voltage Vsen sensed through the second sensing mode F-Mode, a mobility compensation value that reduces or eliminates the mobility deviation between the driving transistors DRT can be calculated, and the calculated mobility compensation value can be stored in the memory 410.

[0162] When a data voltage Vdata for display driving is provided to a corresponding sub-pixel SP, the display device 100 can provide the data voltage Vdata changed based on the threshold voltage compensation value and the mobility compensation value.

[0163] According to the foregoing description, since the threshold voltage sensing requires a long sensing time, the threshold voltage sensing can be performed in the first sensing mode S-Mode, and since the mobility sensing requires a short sensing time, the mobility sensing can be performed in the second sensing mode F-Mode.

[0164] Figure 6 FIG. 1 is a view illustrating a display device 100 according to an embodiment of the disclosure.

[0165] Referring to FIG. 1, the display device 100 according to an embodiment of the disclosure can include a display panel 110, a data driver 120, a gate driver 130, and a controller 140. Figure 6 If the power-on signal is generated, the display device 100 according to an embodiment of the disclosure can sense a characteristic value of a driving transistor DRT in each sub-pixel SP provided in the display panel 110. This sensing process is referred to as a "power-on sensing process".

[0166] Referring to FIG. 1, the display device 100 according to an embodiment of the disclosure can include a display panel 110, a data driver 120, a gate driver 130, and a controller 140. Figure 6 If the power-off signal is generated, the display device 100 according to an embodiment of the disclosure can sense a characteristic value of a driving transistor DRT in each sub-pixel SP provided in the display panel 110 before an off sequence such as power-off is performed. This sensing process is referred to as a "power-off sensing process".

[0167] Referring to FIG. 1, the display device 100 according to an embodiment of the disclosure can include a display panel 110, a data driver 120, a gate driver 130, and a controller 140. Figure 6 The display device 100 according to an embodiment of the disclosure can sense a characteristic value of a driving transistor DRT in each sub-pixel SP during display driving after the power-on signal is generated until the power-off signal is generated. This sensing process is referred to as a "real-time sensing process".

[0168] This real-time sensing process can be performed every blanking period BLANK between active times ACT with respect to a vertical synchronization signal Vsync.

[0169] Since the mobility sensing of the driving transistor DRT requires only a short time, the mobility sensing can be performed in the second sensing mode F-Mode in the sensing driving scheme.

[0170] The mobility sensing that can be performed in the second sensing mode F-Mode as a fast mode requires only a short time, so that the mobility sensing can be performed in any one of the power-on sensing process, the power-off sensing process, and the real-time sensing process.

[0171] For example, mobility sensing, which can be performed in a second sensing mode F-Mode as a fast mode, can be performed in a real-time sensing process, which can reflect a change in mobility in real time during display driving. In other words, mobility sensing can be performed at each blanking period during display driving.

[0172] In contrast, threshold voltage sensing of the driving transistor DRT requires a long saturation time Tsat. Thus, threshold voltage sensing can be performed in a first sensing mode S-Mode in a sensing driving scheme.

[0173] Threshold voltage sensing of the driving transistor DRT should be performed using timing that does not interfere with user viewing. Thus, threshold voltage sensing can be performed when display driving is not performed after a power-off signal is generated according to, for example, a user input, that is, when the user does not intend to view. In other words, threshold voltage sensing can be performed in a power-off sensing process.

[0174] Figure 7 FIG. 1 is a diagram schematically illustrating a display device 100 according to an embodiment of the disclosure.

[0175] Referring to Figure 7 The gate drive circuit 130 according to an embodiment of the disclosure can include a plurality of scan driving circuits SCDR, and the plurality of scan driving circuits SCDR can correspond to a plurality of scan lines SCL.

[0176] Referring to Figure 7 Each of the plurality of scan driving circuits SCDR can further include a scan output buffer SCBUF for outputting a scan signal SC and a control circuit 700 for controlling the scan output buffer SCBUF.

[0177] The scan output buffer SCBUF can receive a scan clock signal SCCLK and a first low potential voltage GVSS1, and output the scan signal SC to a scan output node O.

[0178] The scan output buffer SCBUF can include a pull-up transistor Tu inputted with the scan clock signal SCCLK and a pull-down transistor Td inputted with the first low potential voltage GVSS1.

[0179] The scan output buffer SCBUF can output the scan signal SC to the scan output node O connected to the pull-up transistor Tu and the pull-down transistor Td.

[0180] The pull-up transistor Tu can switch a connection between a scan clock node NC and the scan output node O according to a voltage of a Q node.

[0181] The pull-down transistor Td can switch a connection between the first low voltage node NLV1 and the scan output node O according to a voltage of the QB node.

[0182] In the pull-up transistor Tu, the capacitor C can be electrically connected between the Q node as a gate node and the scan output node O. The capacitor C can be used to boost the voltage of the Q node according to a voltage change of the scan output node O.

[0183] The control circuit 700 can control the voltage of the Q node electrically connected to the gate node of the pull-up transistor Tu, and control the voltage of the QB node electrically connected to the gate node of the pull-down transistor Td. The QB node can receive a DC voltage or an AC signal through a transistor.

[0184] The control circuit 700 can include a plurality of transistors to control the respective voltages of the Q node and the QB node. For example, the control circuit 700 can include one or more transistors for charging the Q node, one or more transistors for discharging the Q node, one or more transistors for charging the QB node, and one or more transistors for discharging the QB node.

[0185] The control circuit 700 can receive a start signal, a reset signal, etc. to control the respective voltages of the Q node and the QB node, and can also receive a carry signal according to a gated drive scheme.

[0186] Figure 8 A display panel 110 in which a gate drive circuit 130 is disposed in a display device 100 according to an embodiment of the disclosure is illustrated.

[0187] Referring to Figure 8 , the gate drive circuit 130 can be a built-in-panel circuit disposed in a non-display area NDA that is an external area of a display area DA of the display panel 110. In this case, the gate drive circuit 130 can be disposed in a gate drive circuit area GIPA in the non-display area NDA.

[0188] As Figure 8 illustrated, the gate drive circuit area GIPA can be located on opposite sides of the display area DA. In some cases, the gate drive circuit area GIPA can be located on only one side of the display area DA.

[0189] Referring to Figure 8 , in order to reduce the bezel size of the display device 100, it is necessary to reduce the width W of the gate drive circuit area GIPA.

[0190] Accordingly, embodiments of the disclosure can provide a gate drive circuit 130 having a low area structure and a display device 100 including the same. A gate drive circuit 130 having a low area structure according to an embodiment of the disclosure and a display device 100 including the same are described below.

[0191] Figure 9 and Figure 10 is a block diagram illustrating a gate drive circuit 130 having a low area structure according to an embodiment of the disclosure.

[0192] Referring to Figure 9 , the gate drive circuit 130 having a low area structure according to an embodiment of the disclosure is an in-panel circuit, and can be disposed in a gate drive circuit region GIPA. The gate drive circuit region GIPA can be included in a non-display area NDA outside a display area DA of the display panel 110.

[0193] Referring to Figure 9 , the gate drive circuit 130 having a low area structure according to an embodiment of the disclosure can include a first scan drive circuit SCDR1, a second scan drive circuit SCDR2, a third scan drive circuit SCDR3, a fourth scan drive circuit SCDR4, and a common sensing circuit COM_RTS.

[0194] The first scan drive circuit SCDR1 can be configured to output an n-th scan signal SC(n) to an n+k-1-th scan signal SC(n+3) to an n-th scan line SCL(n) to an n+k-1-th scan line SCL(n+3). Here, n is a natural number of 1 or more. k can be a natural number of 2 or more.

[0195] The second scan drive circuit SCDR2 can be configured to output an n+k-th scan signal SC(n+4) to an n+2k-1-th scan signal SC(n+7) to an n+k-th scan line SCL(n+4) to an n+2k-1-th scan line SCL(n+7).

[0196] The third scan drive circuit SCDR3 can be configured to output an n+2k-th scan signal SC(n+8) to an n+3k-1-th scan signal SC(n+11) to an n+2k-th scan line SCL(n+8) to an n+3k-1-th scan line SCL(n+11).

[0197] The fourth scan drive circuit SCDR4 can be configured to output an n+3k-th scan signal SC(n+12) to an n+4k-1-th scan signal SC(n+15) to an n+3k-th scan line SCL(n+12) to an n+4k-1-th scan line SCL(n+15).

[0198] Referring toFigure 9 The common sensing circuit COM_RTS can be commonly connected to the first scan driving circuit SCDR1, the second scan driving circuit SCDR2, the third scan driving circuit SCDR3, and the fourth scan driving circuit SCDR4, and configured to receive the line selection signal LSP and output the first common control signal RT1 and the second common control signal RT2 to the first scan driving circuit SCDR1 to the fourth scan driving circuit SCDR4.

[0199] The common sensing circuit COM_RTS is a circuit required in each of the first scan driving circuit SCDR1, the second scan driving circuit SCDR2, the third scan driving circuit SCDR3, and the fourth scan driving circuit SCDR4.

[0200] However, in the gate driving circuit 130 according to the embodiment of the disclosure, since the common sensing circuit COM_RTS is shared by the first scan driving circuit SCDR1, the second scan driving circuit SCDR2, the third scan driving circuit SCDR3, and the fourth scan driving circuit SCDR4, the area of the gate driving circuit 130 can be significantly reduced.

[0201] Referring to Figure 9 In the gate driving circuit 130 having a low area structure, during a sensing driving period, after input of the reset signal RESET, one of the first scan driving circuit SCDR1 to the fourth scan driving circuit SCDR4 can output a scan signal for sensing driving to a corresponding scan line among the 4k scan lines SCL(n) to SCL(n+15).

[0202] Here, the sensing driving period can overlap with the blanking period BLANK. The sensing driving period can be a mobility sensing period during which the fast mode F-MODE can be performed in the blanking period BLANK (refer to Figure 5B ).

[0203] Meanwhile, a target sub-pixel SP or a target sub-pixel row in which mobility sensing is performed can be randomly determined.

[0204] As described above, k can be a natural number of 2 or more (for example, k can be 4 or 6). Figure 9 and Figure 10 An example of the gate driving circuit 130 when k is 4 is shown. As described above, k can be referred to as a Q node sharing range index, and can represent the number of scan output buffers sharing one Q node or one QB node. For example, refer to Figure 10When k is 4, the four scan output buffers SCBUF(n) to SCBUF(n+3) included in the first buffer group BUF_GR1 can share one first Q node Q1. In the present disclosure, each buffer group is a collection of buffers sharing one Q node or one QB node.

[0205] Further, the above k can represent the number of scan output buffers sharing a logic unit or a sensing unit. For example, referring to Figure 10 When k is 4, the four scan output buffers SCBUF(n) to SCBUF(n+3) included in the first buffer group BUF_GR1 can share one first logic unit LOGIC1 or one first sensing unit RTS1.

[0206] Referring to Figure 10 , the first scan driving circuit SCDR1 can include: a first buffer group BUF_GR1 including nth to n+k-1th scan output buffers SCBUF(n) to SCBUF(n+3) electrically connected to nth to n+k-1th scan lines SCL(n) to SCL(n+3); a first logic unit LOGIC1 for controlling the first buffer group BUF_GR1 during a display driving period; and a first sensing unit RTS1 for controlling the first buffer group BUF_GR1 during a sensing driving period. It can be considered that the first logic unit LOGIC1 and the first sensing unit RTS1 are included in a control circuit 700 of Figure 7 .

[0207] Referring to Figure 10 , the second scan driving circuit SCDR2 can include: a second buffer group BUF_GR2 including n+kth to n+2k-1th scan output buffers SCBUF(n+4) to SCBUF(n+7) electrically connected to n+kth to n+2k-1th scan lines SCL(n+4) to SCL(n+7); a second logic unit LOGIC2 for controlling the second buffer group BUF_GR2 during a display driving period; and a second sensing unit RTS2 for controlling the second buffer group BUF_GR2 during a sensing driving period.

[0208] Referring to Figure 10, the third scan driving circuit SCDR3 can include: a third buffer group BUF_GR3 including n+2k-th to n+3k-1-th scan output buffers SCBUF(n+8) to SCBUF(n+11) electrically connected to the n+8-th to n+11-th scan lines SCL(n+8) to SCL(n+11); a third logic unit LOGIC3 for controlling the third buffer group BUF_GR3 during a display driving period; and a third sensing unit RTS3 for controlling the third buffer group BUF_GR3 during a sensing driving period.

[0209] Referring to Figure 10 , the fourth scan driving circuit SCDR4 can include: a fourth buffer group BUF_GR4 including n+3k-th to n+4k-1-th scan output buffers SCBUF(n+12) to SCBUF(n+15) electrically connected to the n+12-th to n+15-th scan lines SCL(n+12) to SCL(n+15); a fourth logic unit LOGIC4 for controlling the fourth buffer group BUF_GR4 during a display driving period; and a fourth sensing unit RTS4 for controlling the fourth buffer group BUF_GR4 during a sensing driving period.

[0210] Referring to Figure 10 , the first sensing unit RTS1 can include: a first sensing Q-node charging circuit SQC1 for charging the first Q-node Q1 during a sensing driving period; a first sensing Q-node discharging circuit SQD1 for discharging the first Q-node Q1 during the sensing driving period; and a first sensing QB-node discharging circuit SQBD1 for discharging the first QB-node QB1 during the sensing driving period.

[0211] Referring to Figure 10 , the second sensing unit RTS2 can include: a second sensing Q-node charging circuit SQC2 for charging the second Q-node Q2 during a sensing driving period; a second sensing Q-node discharging circuit SQD2 for discharging the second Q-node Q2 during the sensing driving period; and a second sensing QB-node discharging circuit SQBD2 for discharging the second QB-node QB2 during the sensing driving period.

[0212] Referring to Figure 10 , the third sensing unit RTS3 can include: a third sensing Q-node charging circuit SQC3 for charging the third Q-node Q3 during a sensing driving period; a third sensing Q-node discharging circuit SQD3 for discharging the third Q-node Q3 during the sensing driving period; and a third sensing QB-node discharging circuit SQBD3 for discharging the third QB-node QB3 during the sensing driving period.

[0213] With reference to Figure 10 , the fourth sensing unit RTS4 can include a fourth sensing Q-node charging circuit SQC4 for charging the fourth Q-node Q4 during a sensing drive period, a fourth sensing Q-node discharging circuit SQD4 for discharging the fourth Q-node Q4 during the sensing drive period, and a fourth sensing QB-node discharging circuit SQBD4 for discharging the fourth QB-node QB4 during the sensing drive period.

[0214] With reference to Figure 9 and Figure 10 , the gating drive circuit 130 can further include a first common control line RTL1 for commonly transmitting a first common control signal RT1 from the common sensing circuit COM_RTS to the first sensing Q-node charging circuit SQC1 to the fourth sensing Q-node charging circuit SQC4, and a second common control line RTL2 for commonly transmitting a second common control signal RT2 from the common sensing circuit COM_RTS to the first sensing QB-node discharging circuit SQBD1 to the fourth sensing QB-node discharging circuit SQBD4.

[0215] With reference to Figure 9 and Figure 10 , the first logic unit LOGIC1 can include the same circuit parts as the second logic unit LOGIC2 and the circuit parts not included in the second logic unit LOGIC2. The third logic unit LOGIC3 can include the same circuit parts as the fourth logic unit LOGIC4 and the circuit parts not included in the fourth logic unit LOGIC4.

[0216] With reference to Figure 10 , the first logic unit LOGIC1 can include the first individual logic units QHCTR1, NQC1 and NQD1 and the first common logic units QBCTR1 / 2, QCTR1 / 2 and NQBD1 / 2.

[0217] However, the second logic unit LOGIC2 can include only the second individual logic units QHCTR2, NQC2 and NQD2 having the same structure as the first individual logic units QHCTR1, NQC1 and NQD1.

[0218] With reference to Figure 10 , the third logic unit LOGIC3 can include the third individual logic units QHCTR3, NQC3 and NQD3 and the third common logic units QBCTR3 / 4, QCTR3 / 4 and NQBD3 / 4.

[0219] However, the fourth logic unit LOGIC4 can include only fourth individual logic units QHCTR4, NQC4, and NQD4 having the same structure as the third individual logic units QHCTR3, NQC3, and NQD3.

[0220] According to the foregoing description, in the gate drive circuit 130, the area of the second logic unit LOGIC2 can be smaller than the area of the first logic unit LOGIC1, and the area of the fourth logic unit LOGIC4 can be smaller than the area of the third logic unit LOGIC3. Thus, the area of the gate drive circuit 130 can be significantly reduced.

[0221] Referring to Figure 10 , the first individual logic units QHCTR1, NQC1, and NQD1 can include: a first QH control circuit QHCTR1 for controlling a voltage level of a first QH node QH1 in the first scan drive circuit SCDR1; a first normal Q node charging circuit NQC1 for charging a first Q node during a display driving period; and a first normal Q node discharging circuit NQD1 for discharging the first Q node during the display driving period.

[0222] Referring to Figure 10 , the second individual logic units QHCTR2, NQC2, and NQD2 can include: a second QH control circuit QHCTR2 for controlling a voltage level of a second QH node QH2 in the second scan drive circuit SCDR2; a second normal Q node charging circuit NQC2 for charging a second Q node during a display driving period; and a second normal Q node discharging circuit NQD2 for discharging the second Q node during the display driving period.

[0223] Referring to Figure 10 , the third individual logic units QHCTR3, NQC3, and NQD3 can include: a third QH control circuit QHCTR3 for controlling a voltage level of a third QH node QH3 in the third scan drive circuit SCDR3; a third normal Q node charging circuit NQC3 for charging a third Q node during a display driving period; and a third normal Q node discharging circuit NQD3 for discharging the third Q node during the display driving period.

[0224] Referring to Figure 10The fourth common logic unit QBCTR3 / 4, QCTR3 / 4, and NQBD3 / 4 can include a third normal QB node discharge circuit NQBD3 / 4 for discharging the third QB node QB3 during a display driving period, a third QB node control circuit QBCTR3 / 4 for controlling a voltage of or charging the third QB node QB3, and a third Q node control circuit QCTR3 / 4 for controlling a voltage of the third Q node Q3.

[0225] Referring to Figure 10 The first common logic unit QBCTR1 / 2, QCTR1 / 2, and NQBD1 / 2 can include a first normal QB node discharge circuit NQBD1 / 2 for discharging the first QB node QB1 during a display driving period, a first QB node control circuit QBCTR1 / 2 for controlling a voltage of or charging the first QB node QB1, and a first Q node control circuit QCTR1 / 2 for controlling a voltage of the first Q node Q1.

[0226] Referring to Figure 10 The third common logic unit QBCTR3 / 4, QCTR3 / 4, and NQBD3 / 4 can include a third normal QB node discharge circuit NQBD3 / 4 for discharging the third QB node QB3 during a display driving period, a third QB node control circuit QBCTR3 / 4 for controlling a voltage of or charging the third QB node QB3, and a third Q node control circuit QCTR3 / 4 for controlling a voltage of the third Q node Q3.

[0227] The display device 100 according to the embodiment of the disclosure can perform sensing driving using the gate driving circuit 130 shown in FIG. 13. In this regard, a brief description is given below. Figure 2B

[0228] As shown in FIGS. 14 and 15, each of the plurality of sub-pixels SP provided in the display panel 110 can include a light emitting element ED, a drive transistor DRT for driving the light emitting element ED, a scan transistor SCT for controlling a connection between a first node of the drive transistor DRT and a data line DL, a sensing transistor SENT for controlling a connection between a second node N2 of the drive transistor DRT and a reference voltage line RVL, and a storage capacitor between the first node N1 and the second node N2 of the drive transistor DRT. Figure 4 Figure 5B As shown in FIGS. 14 and 15, each of the plurality of sub-pixels SP provided in the display panel 110 can include a light emitting element ED, a drive transistor DRT for driving the light emitting element ED, a scan transistor SCT for controlling a connection between a first node of the drive transistor DRT and a data line DL, a sensing transistor SENT for controlling a connection between a second node N2 of the drive transistor DRT and a reference voltage line RVL, and a storage capacitor between the first node N1 and the second node N2 of the drive transistor DRT.

[0229] ​​During the sensing drive period, one of the first to fourth scan drive circuits SCDR1 to SCDR4 can output a sensing drive scan signal to a scan line selected from 4k (k = 4) scan lines SCL(n) to SCL(n+15) through a line selection signal LSP. The line selection signal LSP can be applied to the common sensing circuit COM_RTS.

[0230] The output sensing drive scan signal can be applied to a gate node of a scan transistor SCT in a target sub-pixel SP connected to the selected scan line.

[0231] The sensing drive period can overlap with a blanking period BLANK. The sensing drive period can be a mobility sensing period during which a fast mode F-MODE can be performed during the blanking period BLANK (refer to Figure 5B ).

[0232] If the sensing drive period is a mobility sensing period, a constant voltage type reference voltage Vref can be applied to a reference voltage line RVL connected to the target sub-pixel SP during the initialization period Tinit among the initialization period Tinit and the tracking period Ttrack.

[0233] During the tracking period Ttrack after the initialization period Tinit, the voltage of the reference voltage line RVL connected to the target sub-pixel SP can increase (refer to Figure 11 ).

[0234] The voltage increase rate ΔV / Δt of the reference voltage line RVL can vary depending on the mobility of the drive transistor DRT included in the target sub-pixel SP.

[0235] As the mobility of the drive transistor DRT increases, the voltage increase rate ΔV / Δt of the reference voltage line RVL can increase. In other words, as the mobility of the drive transistor DRT increases, the voltage increment ΔV of the reference voltage line RVL for a predetermined time Δt can increase.

[0236] Figure 11 is a view illustrating a common sensing circuit COM_RTS included in a gate drive circuit 130 having a low area structure according to an embodiment of the disclosure.

[0237] Refer to Figure 11The common sensing circuit COM_RTS can include: first and second shared control transistors Ta and Tb connected in series between the front end carry-in node NPC and a control node M; and a third shared control transistor Tc for controlling connection between the first high potential voltage node NHV1 and a connection node NAB of the first and second shared control transistors Ta and Tb according to a voltage of the control node M.

[0238] Referring to Figure 11 The gate node of the first shared control transistor Ta and the gate node of the second shared control transistor Tb can be commonly connected, so that the line selection signal LSP can be commonly applied.

[0239] Referring to Figure 12 The common sensing circuit COM_RTS can further include: a fourth shared control transistor T1b for controlling connection between the first high potential voltage node NHV1 and a first common control node NRT1 according to a voltage of the control node M; a fifth shared control transistor T5b for controlling connection between a third low potential voltage node NLV3 and a second common control node NRT2 according to a voltage of the control node M; and a shared capacitor CCM between the control node M and the first high potential voltage node NHV1.

[0240] Figure 12 is a view illustrating a first scan driving circuit SCDR1 included in the gate driving circuit 130 having a low area structure according to an embodiment of the disclosure.

[0241] Referring to Figure 12 The first scan driving circuit SCDR1 can include: a first buffer group BUF_GR1 including n-th to n+k-1-th scan output buffers SCBUF(n) to SCBUF(n+3) electrically connected to n-th to n+k-1-th scan lines SCL(n) to SCL(n+3); a first logic unit LOGIC1 for controlling the first buffer group BUF_GR1 during a display driving period; and a first sensing unit RTS1 for controlling the first buffer group BUF_GR1 during a sensing driving period.

[0242] Referring to Figure 12 Each of the n-th to n+k-1-th scan output buffers SCBUF(n) to SCBUF(n+3) included in the first buffer group BUF_GR1 can include a pull-up transistor T6 and a pull-down transistor T7.

[0243] A pull-up transistor T6 of the nth scan output buffer SCBUF(n) can control a connection between the nth scan clock node NC11 and the nth scan output node O11. The nth scan clock signal SCCLK(n) can be applied to the nth scan clock node NC11.

[0244] The nth capacitor C1 can be formed between a gate node of the pull-up transistor T6 of the nth scan output buffer SCBUF(n) and the nth scan output node O11.

[0245] A pull-down transistor T7 of the nth scan output buffer SCBUF(n) can control a connection between the nth scan output node O11 and the first low potential voltage node NLV1. The first low potential voltage GVSS1 can be applied to the first low potential voltage node NLV1.

[0246] A pull-up transistor T6 of the nth+1 scan output buffer SCBUF(n+1) can control a connection between the nth+1 scan clock node NC12 and the nth+1 scan output node O12. The nth+1 scan clock signal SCCLK(n+1) can be applied to the nth+1 scan clock node NC12.

[0247] The nth+1 capacitor C2 can be formed between a gate node of the pull-up transistor T6 of the nth+1 scan output buffer SCBUF(n+1) and the nth+1 scan output node O12.

[0248] A pull-down transistor T7 of the nth+1 scan output buffer SCBUF(n+1) can control a connection between the nth+1 scan output node O12 and the first low potential voltage node NLV1. The first low potential voltage GVSS1 can be applied to the first low potential voltage node NLV1.

[0249] A pull-up transistor T6 of the nth+2 scan output buffer SCBUF(n+2) can control a connection between the nth+2 scan clock node NC13 and the nth+2 scan output node O13. The nth+2 scan clock signal SCCLK(n+2) can be applied to the nth+2 scan clock node NC13.

[0250] The nth+2 capacitor C3 can be formed between a gate node of the pull-up transistor T6 of the nth+2 scan output buffer SCBUF(n+2) and the nth+2 scan output node O13.

[0251] A pull-down transistor T7 of the nth+2 scan output buffer SCBUF(n+2) can control a connection between the nth+2 scan output node O13 and the first low potential voltage node NLV1. The first low potential voltage GVSS1 can be applied to the first low potential voltage node NLV1.

[0252] The pull-up transistor T6 of the nth+3 scan output buffer SCBUF(n+3) can control a connection between the nth+3 scan clock node NC14 and the nth+3 scan output node O14. The nth+3 scan clock signal SCCLK(n+3) can be applied to the nth+3 scan clock node NC14.

[0253] The nth+3 capacitor C4 can be formed between the gate node of the pull-up transistor T6 of the nth+3 scan output buffer SCBUF(n+3) and the nth+3 scan output node O14.

[0254] The pull-down transistor T7 of the nth+3 scan output buffer SCBUF(n+3) can control a connection between the nth+3 scan output node O14 and the first low voltage node NLV1. The first low voltage GVSS1 can be applied to the first low voltage node NLV1.

[0255] The gate nodes of the respective pull-up transistors T6 of the nth scan output buffer SCBUF(n) to the nth+k-1 scan output buffer SCBUF(n+3) can be commonly connected to the first Q node Q1.

[0256] The gate nodes of the respective pull-down transistors T7 of the nth scan output buffer SCBUF(n) to the nth+k-1 scan output buffer SCBUF(n+3) can be commonly connected to the first QB node QB1.

[0257] Referring to Figure 12 The first buffer group BUF_GR1 can further include an nth carry output buffer CRBUF(n). The nth carry output buffer CRBUF(n) can include a carry pull-up transistor T6cr and a carry pull-down transistor T7cr.

[0258] The pull-up transistor T6cr of the nth carry output buffer CRBUF(n) can control a connection between the nth carry clock node NCR1 and the nth carry output node OC1. The nth carry clock signal CRCLK(n) can be applied to the nth carry clock node NCR1.

[0259] The carry capacitor CCR can be formed between the gate node of the pull-up transistor T6cr of the nth carry output buffer CRBUF(n) and the nth carry output node OC1.

[0260] The pull-down transistor T7cr of the nth carry output buffer CRBUF(n) can control a connection between the nth carry output node OC1 and the third low voltage node NLV3. The third low voltage GVSS3 can be applied to the third low voltage node NLV3.

[0261] The gate node of the carry pull-up transistor T6cr of the nth carry output buffer CRBUF(n) can be commonly connected to the gate nodes of the respective pull-up transistors T6 of the nth scan output buffer SCBUF(n) to the (n+k-1)th scan output buffer SCBUF(n+3) together with the first Q node Q1.

[0262] The gate node of the carry pull-down transistor T7cr of the nth carry output buffer CRBUF(n) can be commonly connected to the gate nodes of the respective pull-down transistors T7 of the nth scan output buffer SCBUF(n) to the (n+k-1)th scan output buffer SCBUF(n+3) together with the first QB node QB1.

[0263] Referring to Figure 12 , the first sensing unit RTS1 can include a first sensing Q node charging circuit SQC1, a first sensing Q node discharging circuit SQD1, and a first sensing QB node discharging circuit SQBD1.

[0264] The first sensing Q node charging circuit SQC1 can include a first reset transistor T1c including a first node (a drain node or a source node) to which a first common control signal RT1 is applied, a second node (a source node or a drain node) electrically connected to the first Q node Q1, and a third node (a gate node) to which a reset signal RESET is applied.

[0265] The first sensing QB node discharging circuit SQBD1 can include a first reset transistor T5a including a first node to which a second common control signal RT2 is applied, a second node electrically connected to the first QB node QB1, and a third node to which a reset signal RESET is applied.

[0266] The first sensing Q node discharging circuit SQD1 can include two transistors T3nb and T3nc connected in series between the first Q node Q1 and a third low voltage node NLV3. In the first sensing Q node discharging circuit SQD1, the respective gate nodes of the two transistors T3nb and T3nc can be electrically connected and commonly receive a common start signal VST. In the first sensing Q node discharging circuit SQD1, the connection point of the two transistors T3nb and T3nc can be a first QH node QH1.

[0267] Referring to Figure 12 , the first logic unit LOGIC1 can include a first individual logic unit and a first common logic unit. The first individual logic unit of the first logic unit LOGIC1 can include a first QH control circuit QHCTR1, a first normal Q node charging circuit NQC1, and a first normal Q node discharging circuit NQD1.

[0268] The first normal Q node charging circuit NQC1 can include a first transistor T1 and a second transistor T1a connected in series between a first high potential voltage node NHV1 to which a first high potential voltage GVDD1 is applied and a first Q node Q1. Respective gate nodes of the first transistor T1 and the second transistor T1a can be electrically connected to commonly receive a front end carry signal C(n-2).

[0269] The first normal Q node charging circuit NQC1 can further include a third transistor T11 and a fourth transistor T11’ connected in series between a connection node of the first transistor T1 and the second transistor T1a and a third high potential voltage node NHV3 to which a third high potential voltage GVDD3 is applied. Respective gate nodes of the third transistor T11 and the fourth transistor T11’ can be commonly connected to the third high potential voltage node NHV3. The third transistor T11 and the fourth transistor T11’ can be in a diode connection state.

[0270] The first QH control circuit QHCTR1 can include hold control transistors T3q and T3q’ for controlling a connection between the first high potential voltage node NHV1 and a first QH node QH1 (also referred to as a first Q hold node). Gate nodes of the hold control transistors T3q and T3q’ can be electrically connected to the first Q node Q1.

[0271] The first QH control circuit QHCTR1 can hold a voltage of the first QH node QH1 as the first high potential voltage GVDD1 when the first Q node Q1 is enabled (high voltage) during a display driving period.

[0272] The first normal Q node discharging circuit NQD1 can include transistors T3n and T3na for controlling a connection between the first Q node Q1 and a third low potential voltage node NLV3 to which a third low potential voltage GVSS3 is applied according to a back end carry signal C(n+2) applied to a gate node.

[0273] Referring to Figure 13 The first common logic unit of the first logic unit LOGIC1 can include a first normal QB node discharging circuit NQBD1 / 2, a first QB node control circuit QBCTR1 / 2, and a first Q node control circuit QCTR1 / 2.

[0274] The first QB node control circuit QBCTR1 / 2 can include a first QB charging transistor T4 for controlling a connection between a first QB node QB1 and a second high potential voltage node NHV2 to which a second high potential voltage GVDD2 is applied.

[0275] The first QB node control circuit QBCTR1 / 2 can further include a first control transistor T41 for controlling connection between the gate node of the first QB charging transistor T4 and the second high potential voltage node NHV2, and a gate node of the first control transistor T41 can be connected to the second high potential voltage node NHV2.

[0276] The first QB node control circuit QBCTR1 / 2 can further include a second control transistor T4q for controlling connection between the gate node of the first QB charging transistor T4 and the second low potential voltage node NLV2 to which the second low potential voltage GVSS2 is applied, and a gate node of the second control transistor T4q can be electrically connected to the first Q node Q1.

[0277] The first Q node control circuit QCTR1 / 2 can include a third control transistor T3 and a fourth control transistor T3a connected in series between the first Q node Q1 and a third low potential voltage node NLV3. Gate nodes of the third control transistor T3 and the fourth control transistor T3a can be commonly connected to the first QB node QB1. Connection nodes of the third control transistor T3 and the fourth control transistor T3a can be connected to the first QH node QH1. The first Q node control circuit QCTR1 / 2 can perform a voltage stabilization function for the first Q node Q1. When the first Q node Q1 is to be at a third low potential voltage GVSS3, the first Q node control circuit QCTR1 / 2 can maintain the voltage of the first Q node Q1 as the third low potential voltage GVSS3.

[0278] The first normal QB node discharge circuit NQBD1 / 2 can include a first QB discharge transistor T5 for controlling connection between the first QB node QB1 and the third low potential voltage node NLV3 according to a front end carry signal C(n-2) applied to a gate node.

[0279] The first normal QB node discharge circuit NQBD1 / 2 can further include a second QB discharge transistor T5q for controlling connection between the first QB node QB1 and the third low potential voltage node NLV3, and a gate node of the second QB discharge transistor T5q can be electrically connected to the first Q node Q1.

[0280] Figure 13 FIG. 13 is a view illustrating a second scan driving circuit SCDR2 included in a gate driving circuit 130 having a low area structure according to an embodiment of the disclosure.

[0281] Referring to Figure 13The second scan driving circuit SCDR2 can include a second buffer group BUF_GR2 including n+kth scan output buffers SCBUF(n+4) to (n+2k-1)th scan output buffers SCBUF(n+7) electrically connected to the n+kth scan line SCL(n+4) to the n+2k-1th scan line SCL(n+7), a second logic unit LOGIC2 for controlling the second buffer group BUF_GR2 during a display driving period, and a second sensing unit RTS2 for controlling the second buffer group BUF_GR2 during a sensing driving period.

[0282] Referring to Figure 13 The second scan driving circuit SCDR2 can have the same structure as the first scan driving circuit SCDR1, except that the second scan driving circuit SCDR2 does not include the first common logic unit included in the first scan driving circuit SCDR1.

[0283] Referring to Figure 13 Since the second scan driving circuit SCDR2 does not include the first common logic unit included in the first scan driving circuit SCDR1, an area of the second scan driving circuit SCDR2 can be smaller than an area of the first scan driving circuit SCDR1.

[0284] Referring to Figure 13 The second buffer group BUF_GR2 of the second scan driving circuit SCDR2 can include the n+kth scan output buffers SCBUF(n+4) to the (n+2k-1)th scan output buffers SCBUF(n+7).

[0285] The n+kth scan output buffers SCBUF(n+4) to the (n+2k-1)th scan output buffers SCBUF(n+7) can be respectively configured to receive n+kth scan clock signals SCCLK(n+4) to (n+2k-1)th scan clock signals SCCLK(n+7) and output n+kth scan signals SC(n+4) to (n+2k-1)th scan signals SC(n+7) to n+kth scan output nodes to (n+2k-1)th scan output nodes OC21, OC22, OC23, and OC24, respectively.

[0286] Each of the n+kth scan output buffers SCBUF(n+4) to the (n+2k-1)th scan output buffers SCBUF(n+7) can include a pull-up transistor T6 and a pull-down transistor T7.

[0287] Gate nodes of the respective pull-up transistors T6 of the n+kth scan output buffers SCBUF(n+4) to the (n+2k-1)th scan output buffers SCBUF(n+7) can be commonly connected to a second Q node Q2.

[0288] The gate nodes of the respective pull-down transistors T7 of the nth+k scan output buffer SCBUF(n+4) to the nth+2k-1 scan output buffer SCBUF(n+7) can be commonly connected to the second QB node QB2.

[0289] The second buffer group BUF GR2 of the second scan driving circuit SCDR2 can further include an nth+1 carry output buffer CRBUF(n+1) including a carry pull-up transistor T6cr and a carry pull-down transistor T7cr.

[0290] The nth+1 carry output buffer CRBUF(n+1) can be configured to receive an nth+1 carry clock signal CRCLK(n+1) and output an nth+1 carry signal C(n+1) to an nth+1 carry output node OC2.

[0291] The gate node of the carry pull-up transistor T6cr of the nth+1 carry output buffer CRBUF(n+1) can be commonly connected to the second Q node Q2 along with the gate nodes of the respective pull-up transistors T6 of the nth+k scan output buffer SCBUF(n+4) to the nth+2k-1 scan output buffer SCBUF(n+7).

[0292] The gate node of the carry pull-down transistor T7cr of the nth+1 carry output buffer CRBUF(n+1) can be commonly connected to the second QB node QB2 along with the gate nodes of the respective pull-down transistors T7 of the nth+k scan output buffer SCBUF(n+4) to the nth+2k-1 scan output buffer SCBUF(n+7).

[0293] The nth+k scan output buffer SCBUF(n+4) to the nth+2k-1 scan output buffer SCBUF(n+7) can include capacitors C1 to C4 between the gate nodes and the source nodes (or drain nodes) of the pull-up transistors T6.

[0294] The nth+1 carry output buffer CRBUF(n+1) can include a capacitor CCR between the gate node and the source node (or drain node) of the carry pull-up transistor T6cr.

[0295] Referring to Figure 13 , the second sensing unit RTS2 can include a second sensing Q node charging circuit SQC2, a second sensing Q node discharging circuit SQD2, and a second sensing QB node discharging circuit SQBD2.

[0296] Referring to Figure 13The second sensing Q-node charging circuit SQC2 can include a second reset transistor T1c including a first node (a drain node or a source node) to which a first common control signal RT1 is applied, a second node (a source node or a drain node) electrically connected to a second Q-node Q2, and a third node (a gate node) to which a reset signal RESET is applied.

[0297] Referring to Figure 13 The second sensing QB-node discharging circuit SQBD2 can include a second reset transistor T5a including a first node to which a second common control signal RT2 is applied, a second node electrically connected to a second QB-node QB2, and a third node to which a reset signal RESET is applied.

[0298] Referring to Figure 13 The second sensing Q-node discharging circuit SQD2 can include two transistors T3nb and T3nc connected in series between the second Q-node Q2 and a third low-voltage node NLV3. In the second sensing Q-node discharging circuit SQD2, the respective gate nodes of the two transistors T3nb and T3nc can be electrically connected and commonly receive a common start signal VST. In the second sensing Q-node discharging circuit SQD2, the connection point of the two transistors T3nb and T3nc can be a second QH-node QH2.

[0299] Referring to Figure 14 The second logic unit LOGIC2 can include a second separate logic unit. The second separate logic unit can include a second QH control circuit QHCTR2, a second normal Q-node charging circuit NQC2, and a second normal Q-node discharging circuit NQD2.

[0300] The second normal Q-node charging circuit NQC2 can include a first transistor T1 and a second transistor T1a connected in series between a first high-voltage node NHV1 and the second Q-node Q2. The respective gate nodes of the first transistor T1 and the second transistor T1a can be electrically connected to commonly receive a front-end carry signal C(n-1).

[0301] The second normal Q-node charging circuit NQC2 can further include a third transistor T11 and a fourth transistor T11’ connected in series between the connection node of the first transistor T1 and the second transistor T1a and a third high-voltage node NHV3 to which a third high-voltage GVDD3 is applied. The respective gate nodes of the third transistor T11 and the fourth transistor T11’ can be commonly connected to the third high-voltage node NHV3. The third transistor T11 and the fourth transistor T11’ can be in a diode connection state.

[0302] The second QH control circuit QHCTR2 can include hold control transistors T3q and T3q' for controlling connection between the first high voltage node NHV1 and a second QH node QH2 (also referred to as a second Q hold node). Gate nodes of the hold control transistors T3q and T3q' can be electrically connected to the second Q node Q2.

[0303] The second normal Q node discharge circuit NQD2 can include transistors T3n and T3na for controlling connection between the second Q node Q2 and a third low voltage node NLV3 to which a third low voltage GVSS3 is applied, according to a back end carry signal C(n+3) applied to a gate node.

[0304] Figure 14 is a view illustrating a third scan driving circuit SCDR3 included in the gate driving circuit 130 having a low area structure according to an embodiment of the disclosure.

[0305] Referring to Figure 14 , the third scan driving circuit SCDR3 can have substantially the same structure as the first scan driving circuit SCDR1 except for a different order of steps.

[0306] Referring to Figure 14 , the third scan driving circuit SCDR3 can include a third buffer group BUF_GR3 including n+2k-th to n+3k-1-th scan output buffers SCBUF(n+8) to SCBUF(n+11) electrically connected to n+2k-th to n+3k-1-th scan lines SCL(n+8) to SCL(n+11), a third logic unit LOGIC3 for controlling the third buffer group BUF_GR3 during a display driving period, and a third sensing unit RTS3 for controlling the third buffer group BUF_GR3 during a sensing driving period.

[0307] Referring to Figure 14 , the third buffer group BUF_GR3 of the third scan driving circuit SCDR3 can include the n+2k-th to n+3k-1-th scan output buffers SCBUF(n+8) to SCBUF(n+11).

[0308] The nth+2k scan output buffer SCBUF(n+8) to the nth+3k-1 scan output buffer SCBUF(n+11) can be respectively configured to receive the nth+2k scan clock signal SCCLK(n+8) to the nth+3k-1 scan clock signal SCCLK(n+11) and output the nth+2k scan signal SC(n+8) to the nth+3k-1 scan signal SC(n+11) to the nth+2k scan output node to the nth+3k-1 scan output node OC31, OC32, OC33 and OC34 respectively.

[0309] Each of the nth+2k scan output buffer SCBUF(n+8) to the nth+3k-1 scan output buffer SCBUF(n+11) can include a pull-up transistor T6 and a pull-down transistor T7.

[0310] The gate node of the respective pull-up transistor T6 of the nth+2k scan output buffer SCBUF(n+8) to the nth+3k-1 scan output buffer SCBUF(n+11) can be commonly connected to the third Q node Q3.

[0311] The gate node of the respective pull-down transistor T7 of the nth+2k scan output buffer SCBUF(n+8) to the nth+3k-1 scan output buffer SCBUF(n+11) can be commonly connected to the third QB node QB3.

[0312] The third buffer group BUF GR3 of the third scan driving circuit SCDR3 can further include a nth+2 carry output buffer CRBUF(n+2) including a carry pull-up transistor T6cr and a carry pull-down transistor T7cr.

[0313] The nth+2 carry output buffer CRBUF(n+2) can be configured to receive the nth+2 carry clock signal CRCLK(n+2) and output the nth+2 carry signal C(n+2) to the nth+2 carry output node OC3.

[0314] The gate node of the carry pull-up transistor T6cr of the nth+2 carry output buffer CRBUF(n+2) can be commonly connected to the third Q node Q3 along with the gate nodes of the respective pull-up transistors T6 of the nth+2k scan output buffer SCBUF(n+8) to the nth+3k-1 scan output buffer SCBUF(n+11).

[0315] The gate node of the carry pull-down transistor T7cr of the n+2th carry output buffer CRBUF(n+2) can be commonly connected to the gate nodes of the respective pull-down transistors T7 of the n+2kth scan output buffer SCBUF(n+8) to the n+3k-1th scan output buffer SCBUF(n+11) together with the third QB node QB3.

[0316] The n+2kth scan output buffer SCBUF(n+8) to the n+3k-1th scan output buffer SCBUF(n+11) can include capacitors C1 to C4 located between the gate node and the source node (or the drain node) of the pull-up transistor T6.

[0317] The n+2th carry output buffer CRBUF(n+2) can include a capacitor CCR located between the gate node and the source node (or the drain node) of the carry pull-up transistor T6cr.

[0318] Referring to Figure 14 The third sensing unit RTS3 can include a third sensing Q node charging circuit SQC3, a third sensing Q node discharging circuit SQD3, and a third sensing QB node discharging circuit SQBD3.

[0319] The third sensing Q node charging circuit SQC3 can include a first reset transistor T1c including a first node (a drain node or a source node) to which a first common control signal RT1 is applied, a second node (a source node or a drain node) electrically connected to the third Q node Q3, and a third node (a gate node) to which a reset signal RESET is applied.

[0320] The third sensing QB node discharging circuit SQBD3 can include a first reset transistor T5a including a first node to which a second common control signal RT2 is applied, a second node electrically connected to the third QB node QB3, and a third node to which a reset signal RESET is applied.

[0321] The third sensing Q node discharging circuit SQD3 can include two transistors T3nb and T3nc connected in series between the third Q node Q3 and a third low voltage node NLV3. In the third sensing Q node discharging circuit SQD3, the respective gate nodes of the two transistors T3nb and T3nc can be electrically connected and commonly receive a common start signal VST. In the third sensing Q node discharging circuit SQD3, the connection point of the two transistors T3nb and T3nc can be a third QH node QH3.

[0322] Referring to Figure 14The third logic unit LOGIC3 can include a third individual logic unit and a third common logic unit. The third individual logic unit of the third logic unit LOGIC3 can include a third QH control circuit QHCTR3, a third normal Q node charging circuit NQC3, and a third normal Q node discharging circuit NQD3.

[0323] The third normal Q node charging circuit NQC3 can include a first transistor T1 and a second transistor T1a connected in series between a first high potential voltage node NHV1 to which a first high potential voltage GVDD1 is applied and a third Q node Q3. Respective gate nodes of the first transistor T1 and the second transistor T1a can be electrically connected to commonly receive a front-end carry signal C(n).

[0324] The third normal Q node charging circuit NQC3 can further include a third transistor T11 and a fourth transistor T11’ connected in series between a connection node of the first transistor T1 and the second transistor T1a and a third high potential voltage node NHV3 to which a third high potential voltage GVDD3 is applied. Respective gate nodes of the third transistor T11 and the fourth transistor T11’ can be commonly connected to the third high potential voltage node NHV3. The third transistor T11 and the fourth transistor T11’ can be in a diode connection state.

[0325] The third QH control circuit QHCTR3 can include holding control transistors T3q and T3q’ for controlling a connection between the first high potential voltage node NHV1 and a third QH node QH3 (also referred to as a third Q holding node). Gate nodes of the holding control transistors T3q and T3q’ can be electrically connected to the third Q node Q3.

[0326] The third normal Q node discharging circuit NQD3 can include transistors T3n and T3na for controlling a connection between the third Q node Q3 and a third low potential voltage node NLV3 to which a third low potential voltage GVSS3 is applied, according to a back-end carry signal C(n+4) applied to a gate node.

[0327] Referring to Figure 15 The third common logic unit QBCTR3 / 4, QCTR3 / 4, and NQBD3 / 4 of the third logic unit LOGIC3 can include a third normal QB node discharging circuit NQBD3 / 4, a third QB node control circuit QBCTR3 / 4, and a third Q node control circuit QCTR3 / 4.

[0328] The third QB node control circuit QBCTR3 / 4 can include a first QB charging transistor T4 for controlling a connection between a third QB node QB3 and a second high potential voltage node NHV2 to which a second high potential voltage GVDD2 is applied.

[0329] The third QB node control circuit QBCTR3 / 4 can further include a first control transistor T41 for controlling connection between the gate node of the first QB charging transistor T4 and the second high potential voltage node NHV2, and the gate node of the first control transistor T41 can be connected to the second high potential voltage node NHV2.

[0330] The third QB node control circuit QBCTR3 / 4 can further include a second control transistor T4q for controlling connection between the gate node of the first QB charging transistor T4 and the second low potential voltage node NLV2 to which the second low potential voltage GVSS2 is applied, and the gate node of the second control transistor T4q can be electrically connected to the third Q node Q3.

[0331] The third Q node control circuit QCTR3 / 4 can include a third control transistor T3 and a fourth control transistor T3a connected in series between the third Q node Q3 and the third low potential voltage node NLV3. The gate nodes of the third control transistor T3 and the fourth control transistor T3a can be commonly connected to the third QB node QB3. The connection nodes of the third control transistor T3 and the fourth control transistor T3a can be connected to the third QH node QH3.

[0332] The third normal QB node discharge circuit NQBD3 / 4 can include a first QB discharge transistor T5 for controlling connection between the third QB node QB3 and the third low potential voltage node NLV3 according to a front end carry signal C(n) applied to the gate node.

[0333] The third normal QB node discharge circuit NQBD3 / 4 can further include a second QB discharge transistor T5q for controlling connection between the third QB node QB3 and the third low potential voltage node NLV3, and the gate node of the second QB discharge transistor T5q can be electrically connected to the third Q node Q3.

[0334] Figure 15 FIG. 13 is a view illustrating a fourth scan driving circuit SCDR4 included in the gate driving circuit 130 having a low area structure according to an embodiment of the disclosure.

[0335] Referring to Figure 15The fourth scan driving circuit SCDR4 can include a fourth buffer group BUF_GR4 including n+3k-th to n+4k-1-th scan output buffers SCBUF(n+12) to SCBUF(n+15) electrically connected to the n+3k-th to n+4k-1-th scan lines SCL(n+12) to SCL(n+15), a fourth logic unit LOGIC4 for controlling the fourth buffer group BUF_GR4 during a display driving period, and a fourth sensing unit RTS4 for controlling the fourth buffer group BUF_GR4 during a sensing driving period.

[0336] Referring to Figure 15 The fourth scan driving circuit SCDR4 can have the same structure as the third scan driving circuit SCDR3, except that the fourth scan driving circuit SCDR4 does not include the third common logic unit included in the third scan driving circuit SCDR3.

[0337] Referring to Figure 15 Since the fourth scan driving circuit SCDR4 does not include the third common logic unit included in the third scan driving circuit SCDR3, an area of the fourth scan driving circuit SCDR4 can be smaller than an area of the third scan driving circuit SCDR3.

[0338] Referring to Figure 15 The fourth buffer group BUF_GR4 of the fourth scan driving circuit SCDR4 can include the n+3k-th to n+4k-1-th scan output buffers SCBUF(n+12) to SCBUF(n+15).

[0339] Referring to Figure 15 The n+3k-th to n+4k-1-th scan output buffers SCBUF(n+12) to SCBUF(n+15) can be respectively configured to receive n+3k-th to n+4k-1-th scan clock signals SCCLK(n+12) to SCCLK(n+15) and output n+3k-th to n+4k-1-th scan signals SC(n+12) to SC(n+15) to n+3k-th to n+4k-1-th scan output nodes OC41, OC42, OC43, and OC44, respectively.

[0340] Each of the n+3k-th to n+4k-1-th scan output buffers SCBUF(n+12) to SCBUF(n+15) can include a pull-up transistor T6 and a pull-down transistor T7.

[0341] The gate nodes of the respective pull-up transistors T6 of the nth+3k scan output buffer SCBUF(n+12) to the nth+4k-1 scan output buffer SCBUF(n+15) can be commonly connected to the fourth Q node Q4.

[0342] The gate nodes of the respective pull-down transistors T7 of the nth+3k scan output buffer SCBUF(n+12) to the nth+4k-1 scan output buffer SCBUF(n+15) can be commonly connected to the fourth QB node QB4.

[0343] The fourth buffer group BUF GR4 of the fourth scan driving circuit SCDR4 can further include an nth+3 carry output buffer CRBUF(n+3) including a carry pull-up transistor T6cr and a carry pull-down transistor T7cr.

[0344] The nth+3 carry output buffer CRBUF(n+3) can be configured to receive an nth+3 carry clock signal CRCLK(n+3) and output an nth+3 carry signal C(n+3) to an nth+3 carry output node OC4.

[0345] The gate node of the carry pull-up transistor T6cr of the nth+3 carry output buffer CRBUF(n+3) can be commonly connected to the fourth Q node Q4 along with the gate nodes of the respective pull-up transistors T6 of the nth+3k scan output buffer SCBUF(n+12) to the nth+4k-1 scan output buffer SCBUF(n+15).

[0346] The gate node of the carry pull-down transistor T7cr of the nth+3 carry output buffer CRBUF(n+3) can be commonly connected to the fourth QB node QB4 along with the gate nodes of the respective pull-down transistors T7 of the nth+3k scan output buffer SCBUF(n+12) to the nth+4k-1 scan output buffer SCBUF(n+15).

[0347] The nth+3k scan output buffer SCBUF(n+12) to the nth+4k-1 scan output buffer SCBUF(n+15) can include capacitors C1 to C4 between the gate nodes and the source nodes (or drain nodes) of the pull-up transistors T6.

[0348] The nth+3 carry output buffer CRBUF(n+3) can include a capacitor CCR between the gate node and the source node (or drain node) of the carry pull-up transistor T6cr.

[0349] Reference is made to Figure 15The fourth sensing unit RTS4 can include a fourth sensing Q-node charging circuit SQC4, a fourth sensing Q-node discharging circuit SQD4, and a fourth sensing QB-node discharging circuit SQBD4.

[0350] Referring to Figure 15 The fourth sensing Q-node charging circuit SQC4 can include a first reset transistor T1c including a first node (a drain node or a source node) to which a first common control signal RT1 is applied, a second node (a source node or a drain node) electrically connected to the fourth Q-node Q4, and a third node (a gate node) to which a reset signal RESET is applied.

[0351] Referring to Figure 15 The fourth sensing QB-node discharging circuit SQBD4 can include a second reset transistor T5a including a first node to which a second common control signal RT2 is applied, a second node electrically connected to the fourth QB-node QB4, and a third node to which the reset signal RESET is applied.

[0352] Referring to Figure 16 The fourth sensing Q-node discharging circuit SQD4 can include two transistors T3nb and T3nc connected in series between the fourth Q-node Q4 and a third low-voltage node NLV3. In the fourth sensing Q-node discharging circuit SQD4, the respective gate nodes of the two transistors T3nb and T3nc can be electrically connected and commonly receive a common start signal VST. In the fourth sensing Q-node discharging circuit SQD4, the connection point of the two transistors T3nb and T3nc can be a fourth QH-node QH4.

[0353] Referring to Figure 17 The fourth logic unit LOGIC2 can include a fourth separate logic unit. The fourth separate logic unit can include a fourth QH control circuit QHCTR4, a fourth normal Q-node charging circuit NQC4, and a fourth normal Q-node discharging circuit NQD4.

[0354] The fourth normal Q-node charging circuit NQC4 can include a first transistor T1 and a second transistor T1a connected in series between a first high-voltage node NHV1 and the fourth Q-node Q4. The respective gate nodes of the first transistor T1 and the second transistor T1a can be electrically connected to commonly receive a front-end carry signal C(n+1).

[0355] The fourth normal Q node charging circuit NQC4 can further include a third transistor T11 and a fourth transistor T11' connected in series between the connection node of the first transistor T1 and the second transistor T1a and a third high potential voltage node NHV3 to which a third high potential voltage GVDD3 is applied. Respective gate nodes of the third transistor T11 and the fourth transistor T11' can be commonly connected to the third high potential voltage node NHV3. The third transistor T11 and the fourth transistor T11' can be in a diode connection state.

[0356] The fourth QH control circuit QHCTR4 can include hold control transistors T3q and T3q' for controlling connection between the first high potential voltage node NHV1 and a fourth QH node QH4 (also referred to as a fourth Q hold node). Gate nodes of the hold control transistors T3q and T3q' can be electrically connected to the fourth Q node Q4.

[0357] The fourth normal Q node discharging circuit NQD4 can include transistors T3n and T3na for controlling connection between the fourth Q node Q4 and a third low potential voltage node NLV3 to which a third low potential voltage GVSS3 is applied, according to a back end carry signal C(n+5) applied to a gate node.

[0358] Figure 16 is a first driving timing diagram of the gate drive circuit 130 having a low area structure according to an embodiment of the disclosure, and Figure 16 is a second driving timing diagram of the gate drive circuit 130 having a low area structure according to an embodiment of the disclosure. However, in Figure 17 , k is 4.

[0359] Figure 16 The first driving timing diagram of the gate drive circuit 130 having a low area structure according to an embodiment of the disclosure is a driving timing diagram of the gate drive circuit 130 during a display driving period (an active period ACT), and Figure 16 The second driving timing diagram of the gate drive circuit 130 having a low area structure according to an embodiment of the disclosure is a driving timing diagram of the gate drive circuit 130 during a sensing driving period (a blanking period BLANK).

[0360] Referring to Figure 16 , during the display driving period, the gate drive circuit 130 can generate and output scan signals using 16 scan clock signals SCCLK1 to SCCLK16, and can further use four carry clock signals CRCLK1 to CRCLK4 when generating the scan signals.

[0361] Referring to Figure 16 , the gate drive circuit 130 can perform driving using a start signal VST related to the start of a frame and a line selection signal LSP. Accordingly, the gate drive timing can be controlled.

[0362] Referring to Figure 16 The scan signals output based on the 16 scan clock signals SCCLK1 to SCCLK16 can include a pulse (an on-level voltage period) identical to one pulse waveform in each of the 16 scan clock signals SCCLK1 to SCCLK16.

[0363] Referring to Figure 17 The on-level voltage period (e.g., a high-level voltage period) of each scan signal generated by the gate drive circuit 130 having a low-area structure can have a horizontal time longer than one horizontal time (1H) (e.g., 4H).

[0364] Referring to Figure 17 Each scan signal generated by the gate drive circuit 130 having a low-area structure can overlap with a next scan signal.

[0365] For example, the high-level voltage period of each of the first to sixteenth scan clock signals SCCLK1 to SCCLK16 can have 4 horizontal times (4H). The first scan signal generated based on the first scan clock signal SCCLK1 can have an on-level voltage period (e.g., a high-level voltage period) of 4H horizontal times. Similarly, the second scan signal generated based on the second scan clock signal SCCLK2 can have an on-level voltage period (e.g., a high-level voltage period) of 4H horizontal times. The high-level voltage period of the first scan clock signal SCCLK1 and the high-level voltage period of the second scan clock signal SCCLK2 can overlap in three horizontal times 3H. Accordingly, the on-level voltage period of the first scan signal generated based on the first scan clock signal SCCLK1 and the on-level voltage period of the second scan signal generated based on the second scan clock signal SCCLK2 can overlap in three horizontal times 3H.

[0366] Referring to ​ If the reset signal RESET is generated during the sensing drive period, the gate drive circuit 130 can generate and output a scan signal SCCLK1 for sensing drive according to a carry clock signal (e.g., CRCLK1) subsequently input.

[0367] Referring to ​ The reset signal RESET is a control signal input to a gate node of a first to fourth reset transistor T1c included in a first to fourth sensing Q-node charging circuit SQC1 to SQC4 of the first to fourth sensing units RTS1 to RTS4.

[0368] The above-described gate drive circuit 130 having a low-area structure according to the embodiment of the disclosure is briefly described below.

[0369] The gate drive circuit 130 with a low area structure according to the embodiment of the disclosure can include four buffer groups BUF_GR1 to BUF_GR4 for driving 4k scan lines SCL(n) to SCL(n+4k-1), two common logic units for controlling the four buffer groups BUF_GR1 to BUF_GR4, and one common sensing circuit COM_RTS for controlling output of a sensing drive scan signal to at least one of the 4k scan lines SCL(n) to SCL(n+4k-1).

[0370] For example, when the Q node sharing range index (i.e., k) is 4, the gate drive circuit 130 with a low area structure according to the embodiment of the disclosure can include four buffer groups BUF_GR1 to BUF_GR4 for driving 16 scan lines SCL(n) to SCL(n+15), two common logic units for controlling the four buffer groups BUF_GR1 to BUF_GR4, and one common sensing circuit COM_RTS for controlling output of a sensing drive scan signal to at least one of the 16 scan lines SCL(n) to SCL(n+15).

[0371] In summary, in the above-described sharing structure, one buffer group can correspond to four scan output channels. One common logic unit can correspond to eight scan output channels. One common sensing circuit can correspond to 18 scan output channels. Accordingly, the area of the gate drive circuit 130 can be significantly reduced, and the area of the gate drive circuit region GIPA in the non-display area NDA of the display panel 110 can also be significantly reduced.

[0372] According to the embodiment of the disclosure as described above, a gate drive circuit with a low area structure and a display device including the same can be provided.

[0373] According to the embodiment of the disclosure, a gate drive circuit with a low area structure while normally performing a gate drive operation for sensing the mobility of a drive transistor in a sub-pixel and a display device including the same can be provided.

[0374] The above description has been presented to enable any person skilled in the art to practice and use the inventive concept of the present application and has been provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments can be obvious to those skilled in the art and can be made without departing from the spirit and scope of the application and the general principles defined herein. The above description and drawings are merely illustrative of the inventive concept of the present application and, therefore, should not be taken to limit the scope of the present application. That is, the disclosed embodiments are intended to be illustrative, but not limiting, of the scope of the inventive concept of the present application. Thus, the scope of the present application should be construed in accordance with the summary of the application and the claims appended hereto, rather than being construed in light of the above description and drawings. The scope of the present application should be interpreted based on the appended claims, and all technical concepts within the scope of equivalents thereof should be construed as included in the scope of the present application.

[0375] CROSS-REFERENCE TO RELATED APPLICATIONS

[0376] This application claims priority to Korean Patent Application No. 10-2021-0194519, filed on December 31, 2021, which is hereby incorporated by reference herein in its entirety for all purposes as if fully set forth herein.

Claims

1. A gate drive circuit, the gate drive circuit comprising: a first scan drive circuit configured to output an n-th scan signal to an (n+k-1)-th scan signal to n-th scan lines to (n+k-1)-th scan lines; a second scan drive circuit configured to output an (n+k)-th scan signal to an (n+2k-1)-th scan signal to (n+k)-th scan lines to (n+2k-1)-th scan lines; a third scan drive circuit configured to output an (n+2k)-th scan signal to an (n+3k-1)-th scan signal to (n+2k)-th scan lines to (n+3k-1)-th scan lines; a fourth scan drive circuit configured to output an (n+3k)-th scan signal to an (n+4k-1)-th scan signal to (n+3k)-th scan lines to (n+4k-1)-th scan lines; and a common sensing circuit commonly connected with the first scan drive circuit, the second scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit, and receiving a line selection signal to output a first common control signal and a second common control signal to the first scan drive circuit to the fourth scan drive circuit, wherein n is a natural number of 1 or more, and k is a natural number of 2 or more, and wherein during a sensing drive period, after an input reset signal, one of the first scan drive circuit to the fourth scan drive circuit outputs a scan signal to a corresponding scan line of the 4k scan lines. The sensing drive period overlaps with a blanking period.

2. A gating drive circuit according to claim 1, wherein, The gate drive circuit is a panel built-in circuit provided in a non-display area of a display panel.

3. The gating drive circuit of claim 1, wherein, The common sensing circuit comprises:

4. The gating drive circuit of claim 1, wherein, a first shared control transistor and a second shared control transistor connected in series between a front-end carry-in input node and a control node; and a third shared control transistor controlling a connection between a first high potential voltage node and a connection node of the first shared control transistor and the second shared control transistor according to a voltage of the control node, wherein a gate node of the first shared control transistor and a gate node of the second shared control transistor are commonly connected to allow the line selection signal to be commonly applied to the gate node of the first shared control transistor and the gate node of the second shared control transistor, wherein the common sensing circuit further comprises: a fourth shared control transistor for controlling a connection between the first high potential voltage node and a first common control node according to the voltage of the control node; a fifth shared control transistor for controlling a connection between a third low potential voltage node and a second common control node according to the voltage of the control node; and a capacitor between the control node and the first high potential voltage node. ​ 5. The gating drive circuit of claim 1, wherein, The first scan driving circuit comprises: a first buffer group comprising an nth scan output buffer to an n+k-1th scan output buffer electrically connected with the nth scan line to the n+k-1th scan line; a first logic unit for controlling the first buffer group during a display driving period; and a first sensing unit for controlling the first buffer group during a sensing driving period, The second scan driving circuit comprises: a second buffer group comprising an n+kth scan output buffer to an n+2k-1th scan output buffer electrically connected with the n+kth scan line to the n+2k-1th scan line; a second logic unit for controlling the second buffer group during the display driving period; and a second sensing unit for controlling the second buffer group during the sensing driving period, The third scan driving circuit comprises: a third buffer group comprising an n+2kth scan output buffer to an n+3k-1th scan output buffer electrically connected with the n+2kth scan line to the n+3k-1th scan line; a third logic unit for controlling the third buffer group during the display driving period; and a third sensing unit for controlling the third buffer group during the sensing driving period, and The fourth scan driving circuit comprises: a fourth buffer group comprising an n+3kth scan output buffer to an n+4k-1th scan output buffer electrically connected with the n+3kth scan line to the n+4k-1th scan line; a fourth logic unit for controlling the fourth buffer group during the display driving period; and a fourth sensing unit for controlling the fourth buffer group during the sensing driving period.

6. A gating drive circuit according to claim 5, wherein, Each of the nth scan output buffer to the n+k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor, wherein gate nodes of respective pull-up transistors of the nth scan output buffer to the n+k-1th scan output buffer are commonly connected to a first Q node, Each of the n+kth scan output buffer to the n+2k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor, wherein gate nodes of respective pull-up transistors of the n+kth scan output buffer to the n+2k-1th scan output buffer are commonly connected to a second Q node, Each of the n+2kth scan output buffer to the n+3k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor, wherein gate nodes of respective pull-up transistors of the n+2kth scan output buffer to the n+3k-1th scan output buffer are commonly connected to a third Q node, and Each of the n+3kth scan output buffer to the n+4k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor, wherein gate nodes of respective pull-up transistors of the n+3kth scan output buffer to the n+4k-1th scan output buffer are commonly connected to a fourth Q node. Each of the n+3k-th scan output buffer to the n+4k-1-th scan output buffer comprises a pull-up transistor and a pull-down transistor, wherein gate nodes of the respective pull-up transistors of the n+3k-th scan output buffer to the n+4k-1-th scan output buffer are commonly connected to a fourth Q node.

7. A gating drive circuit according to claim 6, wherein, The first sensing unit comprises: a first sensing Q node charging circuit configured to charge the first Q node during the sensing driving period; a first sensing Q node discharging circuit configured to discharge the first Q node during the sensing driving period; and a first sensing QB node discharging circuit configured to discharge a first QB node during the sensing driving period, The second sensing unit comprises: a second sensing Q node charging circuit configured to charge the second Q node during the sensing driving period; a second sensing Q node discharging circuit configured to discharge the second Q node during the sensing driving period; and a second sensing QB node discharging circuit configured to discharge a second QB node during the sensing driving period, The third sensing unit comprises: a third sensing Q node charging circuit configured to charge the third Q node during the sensing driving period; a third sensing Q node discharging circuit configured to discharge the third Q node during the sensing driving period; and a third sensing QB node discharging circuit configured to discharge a third QB node during the sensing driving period, and The fourth sensing unit comprises: a fourth sensing Q node charging circuit configured to charge the fourth Q node during the sensing driving period; a fourth sensing Q node discharging circuit configured to discharge the fourth Q node during the sensing driving period; and a fourth sensing QB node discharging circuit configured to discharge a fourth QB node during the sensing driving period.

8. A gating drive circuit according to claim 7, wherein, The first sensing Q node charging circuit comprises a first reset transistor comprising a first node to which the first common control signal is applied, a second node electrically connected to the first Q node, and a third node to which the reset signal is applied, The second sensing Q node charging circuit comprises a second reset transistor comprising a first node to which the first common control signal is applied, a second node electrically connected to the second Q node, and a third node to which the reset signal is applied, The third sensing Q node charging circuit comprises a third reset transistor comprising a first node to which the second common control signal is applied, a second node electrically connected to the third Q node, and a third node to which the reset signal is applied, and The fourth sensing Q node charging circuit comprises a fourth reset transistor comprising a first node to which the second common control signal is applied, a second node electrically connected to the fourth Q node, and a third node to which the reset signal is applied. The third sensing Q node charging circuit includes a third reset transistor, the third reset transistor includes a first node to which the first common control signal is applied, a second node electrically connected to the third Q node, and a third node to which the reset signal is applied, and The fourth sensing Q node charging circuit includes a fourth reset transistor, the fourth reset transistor includes a first node to which the first common control signal is applied, a second node electrically connected to the fourth Q node, and a third node to which the reset signal is applied.

9. The gating drive circuit of claim 7, wherein, The first sensing QB node discharging circuit includes a first reset transistor, the first reset transistor includes a first node to which the second common control signal is applied, a second node electrically connected to the first QB node, and a third node to which the reset signal is applied, The second sensing QB node discharging circuit includes a second reset transistor, the second reset transistor includes a first node to which the second common control signal is applied, a second node electrically connected to the second QB node, and a third node to which the reset signal is applied, The third sensing QB node discharging circuit includes a third reset transistor, the third reset transistor includes a first node to which the second common control signal is applied, a second node electrically connected to the third QB node, and a third node to which the reset signal is applied, and The fourth sensing QB node discharging circuit includes a fourth reset transistor, the fourth reset transistor includes a first node to which the second common control signal is applied, a second node electrically connected to the fourth QB node, and a third node to which the reset signal is applied.

10. The gate drive circuit according to claim 7, further comprising: a first common control line for commonly transmitting the first common control signal from the common sensing circuit to the first sensing Q node charging circuit to the fourth sensing Q node charging circuit; and a second common control line for commonly transmitting the second common control signal from the common sensing circuit to the first sensing QB node discharging circuit to the fourth sensing QB node discharging circuit.

11. The gating drive circuit of claim 6, wherein, The area of the second logic unit is smaller than the area of the first logic unit, and The area of the fourth logic unit is smaller than the area of the third logic unit.

12. The gating drive circuit of claim 6, wherein, The first logic unit includes a circuit portion having the same structure as the second logic unit and a circuit portion not included in the second logic unit, and The third logic unit includes a circuit portion having the same structure as the fourth logic unit and a circuit portion not included in the fourth logic unit.

13. A gating drive circuit according to claim 12, wherein, The first logic unit includes a first individual logic unit and a first common logic unit, The second logic unit includes a second individual logic unit having the same structure as the first individual logic unit, The third logic unit includes a third individual logic unit and a third common logic unit, The fourth logic unit includes a fourth individual logic unit and a fourth common logic unit. The fourth logic unit comprises a fourth individual logic unit having the same structure as the third individual logic unit, The first individual logic unit comprises a first QH control circuit for controlling a voltage level of a first QH node in the first scan driving circuit, a first normal Q node charging circuit for charging the first Q node during the display driving period, and a first normal Q node discharging circuit for discharging the first Q node during the display driving period, The second individual logic unit comprises a second QH control circuit for controlling a voltage level of a second QH node in the second scan driving circuit, a second normal Q node charging circuit for charging the second Q node during the display driving period, and a second normal Q node discharging circuit for discharging the second Q node during the display driving period, The third individual logic unit comprises a third QH control circuit for controlling a voltage level of a third QH node in the third scan driving circuit, a third normal Q node charging circuit for charging the third Q node during the display driving period, and a third normal Q node discharging circuit for discharging the third Q node during the display driving period, and The fourth individual logic unit comprises a fourth QH control circuit for controlling a voltage level of a fourth QH node in the fourth scan driving circuit, a fourth normal Q node charging circuit for charging the fourth Q node during the display driving period, and a fourth normal Q node discharging circuit for discharging the fourth Q node during the display driving period.

14. A gating drive circuit according to claim 13, wherein, The first common logic unit comprises a first normal QB node discharging circuit for discharging a first QB node during the display driving period, a first QB node control circuit for charging the first QB node or controlling a voltage of the first QB node, and a first Q node control circuit for controlling a voltage of the first Q node, and The second common logic unit comprises a second normal QB node discharging circuit for discharging a second QB node during the display driving period, a second QB node control circuit for charging the second QB node or controlling a voltage of the second QB node, and a second Q node control circuit for controlling a voltage of the second Q node, and The third common logic unit comprises a third normal QB node discharging circuit for discharging a third QB node during the display driving period, a third QB node control circuit for charging the third QB node or controlling a voltage of the third QB node, and a third Q node control circuit for controlling a voltage of the third Q node, and The fourth common logic unit comprises a fourth normal QB node discharging circuit for discharging a fourth QB node during the display driving period, a fourth QB node control circuit for charging the fourth QB node or controlling a voltage of the fourth QB node, and a fourth Q node control circuit for controlling a voltage of the fourth Q node. The third common logic unit comprises a third normal QB node discharge circuit, a third QB node control circuit, and a third Q node control circuit.

15. The gated drive circuit of claim 5, wherein, k is 4 or 6.

16. The gating drive circuit of claim 1, wherein, The on level voltage period of each scan signal generated by the gate drive circuit has a horizontal time longer than 1H.

17. A gating drive circuit according to claim 16, wherein, Each scan signal generated by the gate drive circuit overlaps with the next scan signal.

18. A display device, comprising: a display panel comprising a plurality of scan lines and a plurality of sub-pixels; and a gate drive circuit disposed in a non-display area of the display panel and driving the plurality of scan lines, wherein the gate drive circuit comprises: a first scan drive circuit for outputting an n-th scan signal to an n+k-1-th scan signal to the n-th scan line to the n+k-1-th scan line of the plurality of scan lines; a second scan drive circuit for outputting an n+k-th scan signal to an n+2k-1-th scan signal to the n+k-th scan line to the n+2k-1-th scan line of the plurality of scan lines; a third scan drive circuit for outputting an n+2k-th scan signal to an n+3k-1-th scan signal to the n+2k-th scan line to the n+3k-1-th scan line of the plurality of scan lines; a fourth scan drive circuit for outputting an n+3k-th scan signal to an n+4k-1-th scan signal to the n+3k-th scan line to the n+4k-1-th scan line of the plurality of scan lines; and a common sensing circuit commonly connected with the first scan drive circuit, the second scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit, receiving a line selection signal, and outputting a first common control signal and a second common control signal to the first scan drive circuit to the fourth scan drive circuit, wherein during a sensing drive period, one of the first scan drive circuit to the fourth scan drive circuit outputs a scan signal to a corresponding scan line of the 4k scan lines after inputting a reset signal.

19. The display device of claim 18, wherein, The sensing drive period overlaps with a blanking period.

20. The display device of claim 18, wherein, Each of the plurality of sub-pixels comprises a light emitting element, a drive transistor for driving the light emitting element, a scan transistor controlling connection between a first node of the drive transistor and a data line, a sensing transistor controlling connection between a second node of the drive transistor and a reference voltage line, and a storage capacitor between the first node and the second node of the drive transistor. During the sensing driving period, one of the first to fourth scan driving circuits outputs a sensing driving scan signal to a scan line selected by a line selection signal from the 4k scan lines, and the sensing driving scan signal is applied to a gate node of the scan transistor in the target sub-pixel connected to the selected scan line.

21. The display device of claim 20, wherein, The sensing driving scan signal is further applied to a gate node of the sensing transistor in the target sub-pixel connected to the selected scan line.

22. The display device of claim 20, wherein, The line selection signal is applied to the common sensing circuit.

23. The display device of claim 20, wherein, The sensing driving period includes an initialization period and a tracking period, During the initialization period, a constant voltage type reference voltage is applied to the reference voltage line connected to the target sub-pixel, and During the tracking period after the initialization period, the voltage of the reference voltage line connected to the target sub-pixel increases.

24. The display device of claim 23, wherein, The rate of voltage increase of the reference voltage line varies according to the mobility of the driving transistor included in the target sub-pixel.

25. The display device of claim 23, wherein, During the tracking period, the first node and the second node of the driving transistor are in a floating state, and During the tracking period, both the voltage of the first node and the voltage of the second node of the driving transistor increase.

26. The display device of claim 18, wherein, The first scan driving circuit includes a first buffer group including nth to n+k-1 scan output buffers electrically connected to the nth to n+k-1 scan lines, a first logic unit for controlling the first buffer group during a display driving period, and a first sensing unit for controlling the first buffer group during a sensing driving period, The second scan driving circuit includes a second buffer group including n+k to n+2k-1 scan output buffers electrically connected to the n+k to n+2k-1 scan lines, a second logic unit for controlling the second buffer group during the display driving period, and a second sensing unit for controlling the second buffer group during the sensing driving period, The third scan driving circuit includes a third buffer group including n+2k to n+3k-1 scan output buffers electrically connected to the n+2k to n+3k-1 scan lines, a third logic unit for controlling the third buffer group during the display driving period, and a third sensing unit for controlling the third buffer group during the sensing driving period, and The fourth scan driving circuit comprises a fourth buffer group, a fourth logic unit and a fourth sensing unit. The fourth buffer group comprises an n+3k scan output buffer to an n+4k-1 scan output buffer electrically connected with the n+3kth scan line to the n+4k-1th scan line. The fourth logic unit is configured to control the fourth buffer group during the display driving period. The fourth sensing unit is configured to control the fourth buffer group during the sensing driving period.

27. The display device of claim 26, wherein, Each of the nth scan output buffer to the n+k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor. A gate node of a corresponding pull-up transistor of the nth scan output buffer to the n+k-1th scan output buffer is commonly connected to a first Q node, and a gate node of a corresponding pull-down transistor of the nth scan output buffer to the n+k-1th scan output buffer is commonly connected to a first QB node. Each of the n+kth scan output buffer to the n+2k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor. A gate node of a corresponding pull-up transistor of the n+kth scan output buffer to the n+2k-1th scan output buffer is commonly connected to a second Q node, and a gate node of a corresponding pull-down transistor of the n+kth scan output buffer to the n+2k-1th scan output buffer is commonly connected to a second QB node. Each of the n+2kth scan output buffer to the n+3k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor. A gate node of a corresponding pull-up transistor of the n+2kth scan output buffer to the n+3k-1th scan output buffer is commonly connected to a third Q node, and a gate node of a corresponding pull-down transistor of the n+2kth scan output buffer to the n+3k-1th scan output buffer is commonly connected to a third QB node. Each of the n+3kth scan output buffer to the n+4k-1th scan output buffer comprises a pull-up transistor and a pull-down transistor. A gate node of a corresponding pull-up transistor of the n+3kth scan output buffer to the n+4k-1th scan output buffer is commonly connected to a fourth Q node, and a gate node of a corresponding pull-down transistor of the n+3kth scan output buffer to the n+4k-1th scan output buffer is commonly connected to a fourth QB node.

28. The display device of claim 26, wherein, An area of the second logic unit is less than an area of the first logic unit, and An area of the fourth logic unit is less than an area of the third logic unit.

29. A gate driving circuit, the gate driving circuit comprising: four buffer groups for driving 4k scan lines, each of the four buffer groups comprising k scan output buffers, where k is a natural number of 2 or more; a first logic unit including a first individual logic unit for controlling a first buffer group of the four buffer groups and a first common logic unit for controlling the first buffer group and a second buffer group of the four buffer groups; a second logic unit including a second individual logic unit for controlling the second buffer group; a third logic unit including a third individual logic unit for controlling a third buffer group of the four buffer groups and a third common logic unit for controlling the third buffer group and a fourth buffer group of the four buffer groups; a fourth logic unit including a fourth individual logic unit for controlling the fourth buffer group; and a common sensing circuit that controls output of a sensing drive scan signal to at least one scan line of the 4k scan lines. ​

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