Pixel circuit and display panel

Abstract

The present invention provides a pixel circuit and a display panel. The pixel circuit includes a light-emitting circuit, a first light-emitting control circuit, a second light-emitting control circuit, and a third light-emitting control circuit. The first light-emitting control circuit generates a drive signal based on a first reference voltage and a second reference voltage. The second light-emitting control circuit generates a light-emission time control signal based on a modulation signal, the modulation control signal, and the second reference voltage. The third light-emitting control circuit determines whether to enable the drive signal based on the light-emission time control signal. During a maintenance period, the second light-emitting control circuit maintains the modulation signal at a third reference voltage based on the first control voltage and the second control voltage.

Description

Technical Field

[0001] The present invention relates to a pixel circuit and a display panel, and in particular to a pixel circuit and a display panel capable of stably modulating a signal. Background Art

[0002] Display panels using light-emitting diodes (LEDs) can be driven using pulse-width modulation (PWM) and pulse-amplitude modulation (PAM). Generally speaking, PWM and PAM drive methods enable a modulation signal based on multiple control voltages in a light-emitting control circuit, thereby controlling the drive signal. However, during the maintenance period, due to the switching of some control voltages, the modulation signal cannot be maintained at the preset voltage level, causing the voltage of the light-emitting control circuit to vary, which in turn affects the drive signal and results in uneven brightness. Summary of the Invention

[0003] An embodiment of the present invention provides a pixel circuit capable of stabilizing a modulation signal during a sustain period to improve brightness uniformity.

[0004] A pixel circuit according to an embodiment of the present invention includes a light-emitting circuit, a first light-emitting control circuit, a second light-emitting control circuit, and a third light-emitting control circuit. The first light-emitting control circuit is configured to generate a drive signal based on a first reference voltage and a second reference voltage. The second light-emitting control circuit is coupled to the first light-emitting control circuit. The second light-emitting control circuit is configured to generate a light-emission time control signal based on a modulation signal, a modulation control signal, and a second reference voltage. The third light-emitting control circuit is coupled to the light-emitting circuit, the first light-emitting control circuit, and the second light-emitting control circuit. The third light-emitting control circuit is configured to determine whether to enable the drive signal based on the light-emission time control signal. During a maintenance period, the second light-emitting control circuit maintains the modulation signal at a third reference voltage based on the first control voltage and the second control voltage.

[0005] An embodiment of the present invention further provides a display panel. The display panel includes a first circuit and a second circuit. The first circuit includes the aforementioned pixel circuit. The second circuit includes a gate control circuit and a second pixel circuit. The first circuit and the second circuit are located in different regions.

[0006] Based on the above, the pixel circuit and display panel of the present invention employ a second light-emission control circuit to maintain the voltage level of the modulation signal based on the first and second control voltages, thereby preventing variations in the output light-emission timing control signal during the maintenance period. This ensures that the enabled drive signal has a stable voltage, thereby improving brightness uniformity.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a pixel circuit according to an embodiment of the present invention.

[0009] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention.

[0010] Figure 3 According to the present invention Figure 2 Schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0011] Figure 4 According to the present invention Figure 2 Circuit diagram of the stabilization circuit shown in the embodiment.

[0012] Figure 5 According to the present invention Figure 2 Circuit diagram of the stabilization circuit shown in the embodiment.

[0013] Figure 6 is a block diagram of a display panel according to an embodiment of the present invention.

[0014] Description of reference numerals:

[0015] 100, 200: pixel circuit

[0016] 110, 210: First light-emitting control circuit

[0017] 120, 220: Second light-emitting control circuit

[0018] 130, 230: third light-emitting control circuit

[0019] 140, 240: Light-emitting circuit

[0020] 221, 421, 521: Stable circuit

[0021] 222: Operation Circuit

[0022] 250: Compensation circuit

[0023] 423: Complementary Metal Oxide Semiconductor Devices

[0024] 60: Display panel

[0025] A1, A2, A11, A12: Area

[0026] C1~C2:Capacitors

[0027] E2E: Maintenance period

[0028] EMI_PAM: First control voltage

[0029] EMI_PWM: Second control voltage

[0030] ILED: driving current

[0031] INV: Inverter

[0032] N1: NMOSFET

[0033] P1: PMOSFET

[0034] SET: Third control voltage

[0035] SPWM: Modulated control signal

[0036] SW_VGH: third reference voltage

[0037] Sweep: Modulation signal

[0038] SWPcoupl1, SWPcoupl2: minimum voltage value

[0039] t1~t2: time

[0040] T1~T10: transistors

[0041] TEST: Fourth control voltage

[0042] V1, V2: voltage levels

[0043] Vdata: data signal

[0044] VDD_PAM: first reference voltage

[0045] VDD_PWM: Second reference voltage

[0046] VN1: voltage

[0047] Vset: fourth reference voltage

[0048] VSS: Ground reference voltage DETAILED DESCRIPTION

[0049] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Reference numerals will be used to identify identical or similar elements in different figures. These embodiments represent only a portion of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are merely examples within the scope of the present invention.

[0050] Figure 1FIG is a block diagram of a pixel circuit according to an embodiment of the present invention. Figure 1 The pixel circuit 100 can be applied to a display device of a micron light emitting diode (Micro LED) (e.g. Figure 6 The display device may include a plurality of pixel circuits 100 arranged in an array.

[0051] exist Figure 1 In the illustrated embodiment, pixel circuit 100 may include a first light-emission control circuit 110, a second light-emission control circuit 120, a third light-emission control circuit 130, and a light-emitting circuit 140. The first light-emission control circuit 110, the third light-emission control circuit 130, and the light-emitting circuit 140 are sequentially connected in series between a first reference voltage VDD_PAM, a second reference voltage VDD_PWM, and a ground reference voltage VSS to form a light-emitting path. In this embodiment, light-emitting circuit 140 may be implemented, for example, using a switch and a micron-sized light-emitting diode.

[0052] In this embodiment, the first light-emitting control circuit 110 can receive a first reference voltage VDD_PAM and a second reference voltage VDD_PWM. The first light-emitting control circuit 110 can generate a driving signal (not shown) based on the first reference voltage VDD_PAM and the second reference voltage VDD_PWM. In other words, the first driving circuit 110 can generate a driving signal having a fixed current value. The fixed current value is related to the first reference voltage VDD_PAM and the second reference voltage VDD_PWM. In this embodiment, the first light-emitting control circuit 110 can be, for example, a pulse-amplitude modulation (PAM) circuit to control the current of the driving signal.

[0053] In this embodiment, the second emission control circuit 120 is coupled to the first emission control circuit 110 and the third emission control circuit 130. The second emission control circuit 120 can receive the modulation signal Sweep, the second reference voltage VDD_PWM, the modulation control signal SPWM, the third reference voltage SW_VGH, the first control voltage EMI_PAM, and the second control voltage EMI_PWM. The second emission control circuit 120 can generate a light-emission timing control signal (not shown) to the third emission control circuit 130 based on the modulation signal Sweep, the modulation control signal SPWM, and the second reference voltage VDD_PWM.

[0054] It should be noted that during the sustain period, the second light-emitting control circuit 120 can maintain the modulation signal Sweep at the third reference voltage SW_VGH based on the first control voltage EMI_PAM and the second control voltage EMI_PWM. The sustain period refers to the period during which the first control voltage EMI_PAM and the second control voltage EMI_PWM are switched. During the sustain period, the first control voltage EMI_PAM and the second control voltage EMI_PWM are in opposite directions, and the modulation signal Sweep is maintained at the third reference voltage SW_VGH to prepare for the start of ramp wave (or sawtooth wave) generation.

[0055] In this embodiment, the third light control circuit 130 is coupled to the light emitting circuit 140, the first light control circuit 110, and the second light control circuit 120. The third light control circuit 130 can receive a light-emission time control signal from the second light control circuit 120 and a drive signal from the first light control circuit 110. The third light control circuit 130 can determine whether to enable the drive signal based on the light-emission time control signal. In other words, the third light control circuit 130 can control the duration of the light-emitting path based on the light-emission time control signal. In this embodiment, the second light control circuit 120 and the third light control circuit 130 can be, for example, pulse-width modulation (PWM) circuits to control the duration of the drive signal output to the light emitting circuit 140, thereby further controlling the displayed grayscale value.

[0056] It's worth noting that the second light-emission control circuit 120 stabilizes the modulation signal Sweep, maintaining it at the third reference voltage SW_VGH for a period (i.e., a sustain period) before ramp generation begins. This prevents voltage variations in the second light-emission control circuit 120 and allows the second light-emission control circuit 120 to generate a stable light-emission timing control signal. Consequently, the drive signal output to the light-emitting circuit 140 has a stable and constant voltage (or current), preventing uneven brightness (e.g., mura) and improving brightness uniformity.

[0057] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Figure 2 The pixel circuit 200 includes a first light-emitting control circuit 210, a second light-emitting control circuit 220, a third light-emitting control circuit 230, a light-emitting circuit 240, and a compensation circuit 250. The first light-emitting control circuit 210, the second light-emitting control circuit 220, the third light-emitting control circuit 230, and the light-emitting circuit 240 can refer to the relevant description of the pixel circuit 100 and be deduced by analogy, so they are not repeated here.

[0058] In this embodiment, the first light control circuit 210 can receive a first reference voltage VDD_PAM, a second reference voltage VDD_PWM, and a first control voltage EMI_PAM. The first light control circuit 210 can be controlled by the first control voltage EMI_PAM to generate a driving signal (not shown) based on the first reference voltage VDD_PAM and the second reference voltage VDD_PWM. The first light control circuit 210 can be implemented, for example, as a PAM circuit.

[0059] In this embodiment, the second light-emitting control circuit 220 may include a stabilization circuit 221 and an operation circuit 222. The stabilization circuit 221 is coupled to the operation circuit 222. The stabilization circuit 221 can stabilize the modulation signal Sweep. The operation circuit 222 is also coupled to the first light-emitting control circuit 210 and the third light-emitting control circuit 230. The operation circuit 222 can generate a light-emitting timing control signal for the third light-emitting control circuit 230 based on the modulation signal Sweep, the modulation control signal SPWM, and the second reference voltage VDD_PWM.

[0060] In this embodiment, the operating circuit 222 may include first to third transistors T1 to T3 and a first capacitor C1. The first to third transistors T1 to T3 may be implemented as p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs), for example.

[0061] Specifically, the stabilization circuit 221 has multiple receiving terminals for respectively receiving a modulation signal Sweep, a first control voltage EMI_PAM, a second control voltage EMI_PWM, and a third reference voltage SW_VGH. The first transistor T1 has a control terminal (i.e., a gate terminal) for receiving the modulation control signal SPWM. A first terminal (i.e., a source / drain terminal) of the first transistor T1 is coupled to the stabilization circuit 221 to receive the modulation signal Sweep. A second terminal (i.e., a source / drain terminal) of the first transistor T1 is coupled to the stabilization circuit 221 to receive the third reference voltage SW_VGH. A first terminal of the first capacitor C1 is coupled to a first terminal (i.e., a source / drain terminal) of the first transistor T1. A second terminal of the first capacitor C1 is coupled to a first node N1.

[0062] Continuing with the above description, the second transistor T2 has a control terminal (i.e., gate terminal) coupled to the control terminal (i.e., gate terminal) of the first transistor T1 to receive the modulation control signal SPWM. A first terminal (i.e., source / drain terminal) of the second transistor T2 is coupled to the second terminal of the first capacitor C1 at a first node N1. A second terminal (i.e., source / drain terminal) of the second transistor T2 receives the data signal Vdata and is coupled to the third emission control circuit 230. A third transistor T3 has a control terminal (i.e., gate terminal) coupled to the first node N1. A first terminal (i.e., source / drain terminal) of the third transistor T3 receives the second reference voltage VDD_PWM and is coupled to the first emission control circuit 210. A second terminal (i.e., source / drain terminal) of the third transistor T3 is coupled to the third emission control circuit 230 at a second node N2 to output the emission time control signal. In this embodiment, the third transistor T3 may be the control transistor of the second emission control circuit 220.

[0063] In this embodiment, the stabilization circuit 221 includes a fourth transistor T4, a fifth transistor T5, and an inverter INV. The fourth transistor T4 and the fifth transistor T5 can each be implemented, for example, as a PMOSFET. In this embodiment, the control terminal (i.e., gate terminal) of the fourth transistor T4 is coupled to the output terminal of the inverter INV. The first terminal (i.e., source / drain terminal) of the fourth transistor T4 receives the modulation signal Sweep. The second terminal (i.e., source / drain terminal) of the fourth transistor T4 is coupled to the first terminal (i.e., source / drain terminal) of the fifth transistor T5. The control terminal (i.e., gate terminal) of the fifth transistor T5 receives the second control voltage EMI_PWM. The second terminal (i.e., source / drain terminal) of the fifth transistor T5 receives the third reference voltage SW_VGH. The input terminal of the inverter INV receives the first control voltage EMI_PAM.

[0064] In this embodiment, the third light-emitting control circuit 230 may include eighth to tenth transistors T8 to T10 and a second capacitor C2. Each of the eighth to tenth transistors T8 to T10 may be implemented, for example, as a PMOSFET. In this embodiment, the eighth transistor T8 has a control terminal (i.e., gate terminal) that receives the second control voltage EMI_PWM. A first terminal (i.e., source / drain terminal) of the eighth transistor T8 is coupled to the second node N2. A second terminal (i.e., source / drain terminal) of the eighth transistor T8 is coupled to a first terminal (i.e., source / drain terminal) of a ninth transistor T9. The ninth transistor T9 has a control terminal (i.e., gate terminal) that receives a third control voltage SET. A first terminal (i.e., source / drain terminal) of the ninth transistor T9 is coupled to a second terminal (i.e., source / drain terminal) of T8 and a first terminal of the second capacitor C2 at a third node N3. A second terminal (i.e., source / drain terminal) of the ninth transistor T9 receives a fourth reference voltage Vset and is coupled to the second terminal of the second capacitor C2. The tenth transistor T10 has a control terminal (i.e., a gate terminal) coupled to the third node N3. A first terminal (i.e., a source / drain terminal) of the tenth transistor T10 is coupled to the first light-emitting control circuit 210 and the compensation circuit 250. A second terminal (i.e., a source / drain terminal) of the tenth transistor T10 is coupled to the light-emitting circuit 240 to output a driving signal. In this embodiment, the tenth transistor T10 may be a driving transistor of the pixel circuit 200.

[0065] In this embodiment, the lighting circuit 240 can receive a first reference voltage VDD_PAM and a fourth control voltage TEST. The lighting circuit 240 can be controlled by the first reference voltage VDD_PAM and the fourth control voltage TEST, and by the PAM circuit (i.e., the first lighting control circuit 210) and the PWM circuit (i.e., the second lighting control circuit 220 and the third lighting control circuit 230) to emit light.

[0066] In this embodiment, the first reference voltage VDD_PAM, the second reference voltage VDD_PWM, the third reference voltage SW_VGH, and the fourth reference voltage Vset can be different high power signals, and the ground reference voltage VSS can be ground or a low voltage source signal.

[0067] In some embodiments, the first to tenth transistors T1 to T10 may be implemented as N-type Metal-Oxide-Semiconductor Field-Effect Transistors (NMOSFETs). The signals in some embodiments are inverse to the corresponding signals in this embodiment.

[0068] In this embodiment, the compensation circuit 250 is coupled to the first light control circuit 210 and the third light control circuit 230. The compensation circuit 250 can compensate the threshold voltage of the driving transistor (i.e., the tenth transistor T10) to a node in the third light control circuit 230 to ensure that the light emission time is consistent under the same gray scale and the light emission brightness is consistent. Figure 2 In the illustrated embodiment, the compensation circuit 250 may be, for example, an external compensation detection switch circuit shared by multiple pixel circuits 200. In some embodiments, the compensation circuit 250 may be omitted.

[0069] Figure 3 According to the present invention Figure 2 The operation diagram of the pixel circuit shown in the embodiment. Figure 3 In FIG, the horizontal axis is the operation time of the pixel circuit 200, and the vertical axis is the voltage value. Figure 2 as well as Figure 3 The signal generated by the pixel circuit 200 can be represented by a solid line. Signals generated by other pixel circuits that do not include or are not coupled to the stabilization circuit 221 can be represented by dashed lines. For example, the drive signal output to the light-emitting circuit 240 can be the drive current ILED shown in a solid line. The drive signals of other pixel circuits can be the drive current ILED shown in dashed lines.

[0070] At time t1, the second control voltage EMI_PWM is switched to gradually increase from the first voltage level V1 to the second voltage level V2. Subsequently, the first control voltage EMI_PAM is switched to gradually increase from the first voltage level V1 to the second voltage level V2. At time t2, both the first control voltage EMI_PAM and the second control voltage EMI_PWM are switched to the second voltage level V2. That is, during the sustain period E2E (i.e., from time t1 to t2), the first control voltage EMI_PAM has the first voltage level V1, and the second control voltage EMI_PWM has the second voltage level V2. The first control voltage EMI_PAM and the second control voltage EMI_PWM are in opposite directions.

[0071] During the sustain period E2E (ie, time t1 to t2), the modulation control signal SPWM has the second voltage level V2 and is enabled to turn on the first transistor T1. At this time, the modulation signal Sweep is pulled to the third reference voltage SW_VGH through the first transistor T1 to regulate the modulation signal Sweep.

[0072] It should be noted that the inverted first control voltage EMI_PAM has a second voltage level V2 and is enabled to turn on the fourth transistor T4. The second control voltage EMI_PWM has a second voltage level V2 and is enabled to turn on the fifth transistor T5. At this time, the modulation signal Sweep is pulled to the third reference voltage SW_VGH through the fourth transistor T4 and the fifth transistor T5, thereby enhancing the voltage regulation capability of the modulation signal Sweep and maintaining the modulation signal Sweep at a substantially constant voltage before the ramp wave begins to be generated.

[0073] In this embodiment, the voltage regulation capability of the modulation signal Sweep can be evaluated, for example, using the following formula (1). In formula (1), SWP RATIO is a voltage regulation parameter, SWP_VGH is an initial voltage value of the modulation signal Sweep during the sustain period E2E, and SWPcouple is a minimum voltage value of the modulation signal Sweep during the sustain period E2E.

[0074]

[0075] Compared to other pixel circuits, the modulation signal Sweep of the pixel circuit 200 has a higher minimum voltage value (i.e., SWPcouple1) during the sustain period E2E. Therefore, when the initial voltage value of the modulation signal Sweep is fixed at the third reference voltage SW_VGH, the modulation signal Sweep of the pixel circuit 200 has a lower voltage regulation parameter (i.e., SWPRATIO). In other words, the pixel circuit 200 has a higher voltage regulation capability for the modulation signal Sweep.

[0076] On the other hand, the voltage at the first node N1 can be represented by a voltage VN1, for example. In this embodiment, the control terminal (i.e., the gate terminal) of the control transistor (i.e., the third transistor T3) of the second light-emitting control circuit 220 also has a stable voltage during the sustain period E2E, thereby generating a stable light-emitting time control signal.

[0077] It should be noted that multiple pixel circuits 200 arranged in the same row can share the same modulation signal Sweep. The stabilization circuit 221 of each pixel circuit 200 can stabilize the corresponding modulation signal Sweep to achieve consistent brightness when displaying a predetermined pattern (such as an X-talk pattern).

[0078] Figure 4 According to the present invention Figure 2 The circuit diagram of the stabilization circuit shown in the embodiment. Figure 2 as well as Figure 4 , Figure 2 The stabilization circuit 221 can also be implemented as Figure 4The stabilization circuit 421 is used to stabilize the modulation signal Sweep.

[0079] In this embodiment, the stabilization circuit 421 includes a fourth transistor T4, a fifth transistor T5, and a complementary metal-oxide-semiconductor (CMOS) device 423. In this embodiment, the CMOS device 423 can be implemented, for example, as a PMOSFET P1 and an NMOSFET N1. The control terminal (i.e., gate terminal) of the fourth transistor T4 is coupled to the output terminal of the CMOS device 423. The first terminal (i.e., source / drain terminal) of the fourth transistor T4 receives the modulation signal Sweep. The second terminal (i.e., source / drain terminal) of the fourth transistor T4 is coupled to the first terminal (i.e., source / drain terminal) of the fifth transistor T5. The control terminal (i.e., gate terminal) of the fifth transistor T5 receives the second control voltage EMI_PWM. The second terminal (i.e., source / drain terminal) of the fifth transistor T5 receives the third reference voltage SW_VGH. The control terminal of the CMOS device 423 receives the first control voltage EMI_PAM. The first terminal and second terminal of the CMOS device 423 receive the third reference voltage SW_VGH and the fourth reference voltage Vset, respectively.

[0080] Figure 5 According to the present invention Figure 2 The circuit diagram of the stabilization circuit shown in the embodiment. Figure 2 as well as Figure 5 , Figure 2 The stabilization circuit 221 can also be implemented as Figure 5 The stabilization circuit 521 is used to stabilize the modulation signal Sweep.

[0081] In this embodiment, the stabilization circuit 521 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. In this embodiment, the sixth transistor T6 and the seventh transistor T7 can each be implemented as a PMOSFET, for example. The control terminal (i.e., gate terminal) of the fourth transistor T4 is coupled to the second terminal (i.e., source / drain terminal) of the sixth transistor T6 and the first terminal (i.e., source / drain terminal) of the seventh transistor T7. The first terminal (i.e., source / drain terminal) of the fourth transistor T4 receives the modulation signal Sweep. The second terminal (i.e., source / drain terminal) of the fourth transistor T4 is coupled to the first terminal (i.e., source / drain terminal) of the fifth transistor T5. The control terminal (i.e., gate terminal) of the fifth transistor T5 receives the second control voltage EMI_PWM. The second terminal (i.e., source / drain terminal) of the fifth transistor T5 receives the third reference voltage SW_VGH. The control terminal (i.e., gate terminal) of the sixth transistor T6 receives the first control voltage EMI_PAM. The control terminal (ie, the gate terminal) and the second terminal (ie, the source / drain terminal) of the seventh transistor T7 are coupled together and receive the fourth reference voltage Vset.

[0082] Figure 6 FIG is a block diagram of a display panel according to an embodiment of the present invention. Figure 6 The display panel 60 may include a first circuit disposed in a first area A1 and a second circuit disposed in a second area A2. The first area A1 and the second area A2 may be alternately arranged on the display panel 60. In other words, the first circuit and the second circuit are located in different areas A1 and A2.

[0083] In this embodiment, the first circuit in the first area A1 may include a plurality of Figure 2 The second circuit of the second area A2 may include a plurality of second pixel circuits arranged in an array and a gate control circuit. The second circuit may be, for example, a gate in pixel (GIP) circuit.

[0084] In this embodiment, each second pixel circuit may include Figure 2 The first light emission control circuit 210, the operating circuit 222, the third light emission control circuit 230, the light emission circuit 240, and the compensation circuit 250 are shown in FIG. In some embodiments, the compensation circuit 250 in each second pixel circuit can be omitted. In other words, the second pixel circuit can be, for example, the pixel circuit 200 without the stabilization circuit 221. Therefore, the second pixel circuit can stabilize the modulation signal Sweep through the first transistor T1 in the operating circuit 222, without using the stabilization circuit 221 to enhance the voltage regulation capability.

[0085] In this embodiment, the first area A1 may include a plurality of first sub-areas A11 and a plurality of second sub-areas A12 arranged in an array. The stabilization circuit 221 of each pixel circuit 200 may be disposed in the second sub-area A12, and other circuits of each pixel circuit 200 may be disposed in the first sub-area A11. The aforementioned other circuits include the first emission control circuit 210, the operating circuit 222, the third emission control circuit 230, the emission circuit 240, and the compensation circuit 250. In other words, for each pixel circuit 200, the stabilization circuit 221 and the first emission control circuit 210, the operating circuit 222, the third emission control circuit 230, the emission circuit 240, and the compensation circuit 250 are located in different areas A12 and A11.

[0086] In summary, the pixel circuit and display panel of the present invention can enhance the voltage regulation capability of the modulation signal during the sustain period through the stabilization circuit, thereby preventing voltage variations at the control terminal (i.e., the first node) of the second light-emitting control circuit and generating a control signal with a stable light-emitting duration. As a result, the drive signal can be a stable drive current, thereby improving the uniformity of the light-emitting brightness.

[0087] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A pixel circuit comprising: a light-emitting circuit; a first light-emitting control circuit for generating a driving signal based on a first reference voltage and a second reference voltage; a second light-emitting control circuit, coupled to the first light-emitting control circuit, for generating a light-emitting time control signal according to a modulation signal, a modulation control signal, and the second reference voltage; as well as a third light emitting control circuit coupled to the light emitting circuit, the first light emitting control circuit, and the second light emitting control circuit, for determining whether to enable the driving signal according to the light emitting time control signal; During a maintenance period, the second light emitting control circuit maintains the modulation signal at a third reference voltage based on a first control voltage and a second control voltage. The second light emitting control circuit includes: a stabilization circuit having a plurality of receiving terminals for respectively receiving the modulation signal, the first control voltage, the second control voltage, and the third reference voltage; a first transistor having a control terminal for receiving the modulation control signal, a first terminal of the first transistor coupled to the stabilization circuit for receiving the modulation signal, and a second terminal of the first transistor coupled to the stabilization circuit for receiving the third reference voltage; a first capacitor having a first terminal coupled to the first terminal of the first transistor; a second transistor having a control terminal receiving the modulated control signal, a first terminal of the second transistor coupled to the second terminal of the first capacitor at a first node, and a second terminal of the second transistor receiving a data signal; and A third transistor has a control terminal coupled to the first node, a first terminal of the third transistor receives the second reference voltage, and a second terminal of the third transistor is coupled to the third light emitting control circuit at a second node. 2 . The pixel circuit as claimed in claim 1 , wherein during the sustain period, the first control voltage and the second control voltage are in opposite directions.

3. The pixel circuit according to claim 1 , wherein the stabilization circuit comprises: a fourth transistor having a first terminal receiving the modulation signal; a fifth transistor having a control terminal receiving the second control voltage, a first terminal of the fifth transistor coupled to the second terminal of the fourth transistor, and a second terminal of the fifth transistor receiving the third reference voltage; as well as An inverter has an output terminal coupled to the control terminal of the fourth transistor, and an input terminal of the inverter receives the first control voltage.

4. The pixel circuit according to claim 1 , wherein the stabilization circuit comprises: a fourth transistor having a first terminal for receiving the modulation signal; a fifth transistor having a control terminal receiving the second control voltage, a first terminal of the fifth transistor coupled to the second terminal of the fourth transistor, and a second terminal of the fifth transistor receiving the third reference voltage; as well as A complementary metal oxide semiconductor device has an output terminal coupled to the control terminal of the fourth transistor, the control terminal of the complementary metal oxide semiconductor device receives the first control voltage, and the first terminal and the second terminal of the complementary metal oxide semiconductor device receive the third reference voltage and a fourth reference voltage respectively.

5. The pixel circuit according to claim 1 , wherein the stabilization circuit comprises: a fourth transistor having a first terminal for receiving the modulation signal; a fifth transistor having a control terminal receiving the second control voltage, a first terminal of the fifth transistor coupled to the second terminal of the fourth transistor, and a second terminal of the fifth transistor receiving the third reference voltage; a sixth transistor having a control terminal receiving the first control voltage, a first terminal of the sixth transistor receiving the third reference voltage, and a second terminal of the sixth transistor coupled to the control terminal of the fourth transistor; and A seventh transistor has a first terminal coupled to the control terminal of the fourth transistor, and the control terminal and the second terminal of the seventh transistor receive a fourth reference voltage.

6. The pixel circuit according to claim 1 , wherein the third light emitting control circuit comprises: an eighth transistor having a control terminal receiving the second control voltage, and a first terminal of the eighth transistor coupled to the second node; a ninth transistor having a control terminal receiving a third control voltage, a first terminal of the ninth transistor coupled to the second terminal of the eighth transistor at a third node, and a second terminal of the ninth transistor receiving a fourth reference voltage; a second capacitor having a first terminal coupled to the third node, and a second terminal coupled to the second terminal of the ninth transistor; as well as A tenth transistor has a control terminal coupled to the third node, a first terminal of the tenth transistor coupled to the first light emitting control circuit, and a second terminal of the tenth transistor coupled to the light emitting circuit.

7. A display panel comprising: a first circuit comprising a plurality of pixel circuits according to claim 1; as well as a second circuit comprising a gate control circuit and a plurality of second pixel circuits, The first circuit and the second circuit are located in different areas.

8. The display panel as claimed in claim 7, wherein the second light emitting control circuit of the first circuit comprises: a stabilization circuit having a plurality of receiving terminals for respectively receiving the modulation signal, the first control voltage, the second control voltage, and the third reference voltage; as well as an operating circuit coupled to the stabilization circuit, the first light-emitting control circuit, and the third light-emitting control circuit, for generating the light-emitting time control signal to the third light-emitting control circuit; Each of the second pixel circuits includes the light emitting circuit, the first light emitting control circuit, the operating circuit and the third light emitting control circuit. 9 . The display panel as claimed in claim 8 , wherein the stabilization circuit, the light emitting circuit, the first light emitting control circuit, the operation circuit, and the third light emitting control circuit are located in different areas.

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