Display device

Abstract

A display apparatus includes a display panel including a plurality of pixels connected to a data line and a gate line, a data driver configured to apply a data voltage to the data line for an active period and to apply a sustain voltage thereto for a blanking period in which no data voltage is applied thereto, a gate driver to apply a scan signal to the gate line, a light emission signal generator to apply a light emission signal to the plurality of pixels, and a controller configured to operate the display apparatus based on a plurality of frequency bands, wherein the plurality of frequency bands have different maximum target brightness levels based on an operating environment of the display apparatus, wherein a duty cycle of the light emission signal is less than a duty cycle of the sustain voltage in at least one of the plurality of frequency bands. Accordingly, sustain voltage brightness non-uniformity is reduced and uniformity of the display panel is improved to improve image quality.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device, and more particularly, to a display device that reduces uniformity deterioration due to flicker and luminance mura such as a spot. BACKGROUND

[0002] An image display device that implements various information on a screen is a key factor in the information and communication era, and is thinner, lighter, and has higher performance. Accordingly, a display device that can be manufactured in a thin and light manner is receiving attention. An organic light emitting display device can be a self-emitting device, can be advantageous in terms of power consumption due to low voltage operation, and can have a high response speed, a high luminous efficiency, a wide field of view (FOV), and a high contrast ratio, and thus is being researched as a next-generation display. The organic light emitting display device implements an image using a plurality of sub-pixels arranged in a matrix form. Each of the plurality of sub-pixels includes a light emitting element and a pixel circuit including a plurality of transistors for independently driving the light emitting element.

[0003] Specific examples of the flat panel display device can include a liquid crystal display device (LCD), a quantum dot display device (QD), a field emission display device (FED), an organic light emitting display device (OLED), and the like. The organic light emitting display device, which does not require a separate light source, can be compact and can implement clear color display. The OLED device can include an organic light emitting diode (OLED) that self-emits light, and thus can have a fast response speed, a high contrast ratio, a high luminous efficiency, a high brightness, and a wide field of view (FOV).

[0004] An organic light emitting display device including an organic light emitting diode can have various advantages because the organic light emitting display device displays an image based on light generated by a light emitting element within a pixel. However, in the OLED device, during operation, flicker and luminance mura phenomena such as a spot can occur due to coupling between internal lines in a pixel and operating conditions of a driving signal, and the like. Accordingly, uniformity defects can occur. This becomes a factor that deteriorates image quality of the display device.

[0005] Accordingly, various driving techniques are being developed to address image abnormalities. In order to improve image quality, an operating condition of a pixel can be controlled to improve operating performance. SUMMARY

[0006] The disclosure proposes a solution to the above problem. Accordingly, an object of the disclosure is to provide a display device that can control an operating voltage condition of a pixel circuit to reduce flicker and uniformity deterioration.

[0007] The objects of the present disclosure are not limited to the above-mentioned objects. Other unmentioned objects and advantages of the present disclosure can be understood by the following description and can be more clearly understood from the embodiments of the present disclosure. Also, it will be easily understood that the objects and advantages of the present disclosure can be achieved using the means shown in the claims and combinations thereof.

[0008] To achieve this object, according to an aspect of the present disclosure, a display apparatus includes a display panel including a plurality of pixels connected to a data line and a gate line, a data driver configured to apply a data voltage to the data line for an active period and to apply a parking voltage to the data line for a blanking period in which the data voltage is not applied, a gate driver for applying a scan signal to the gate line, a light emission signal generator for applying a light emission signal to the plurality of pixels, and a controller configured to operate the display apparatus based on a plurality of frequency bands, wherein the plurality of frequency bands have different maximum target brightness levels based on an operating environment of the display apparatus, and wherein a duty cycle of the light emission signal is less than a duty cycle of the parking voltage in at least one of the plurality of frequency bands.

[0009] According to the embodiments of the present disclosure, the duty cycle of the light emission signal can be controlled to reduce parking voltage mura and improve uniformity of the display panel, and thus the image quality can be improved.

[0010] Effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned herein will become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram of a display apparatus according to an embodiment of the present disclosure.

[0012] Figure 2A 、 Figure 2B and Figure 2C is a circuit diagram showing a pixel circuit of a display apparatus according to an embodiment of the present disclosure.

[0013] Figure 3A and Figure 3B are diagrams for illustrating operations of the pixel circuit and the light emitting element shown in Figure 2A

[0014] Figure 4 is a diagram showing a band-based dimming level of a pixel circuit in a display apparatus according to an embodiment of the present disclosure.

[0015] Figure 5A is a diagram showing a band-based dimming level adjustment scheme of a pixel circuit in a display apparatus according to an embodiment of the present disclosure, Figure 5B ​is a graph illustrating a light emission signal having a duty cycle that varies according to a frequency band.

[0016] Figure 6 is a graph illustrating an operation of a scan signal during one frame in a display device according to an embodiment of the disclosure.

[0017] Figure 7 is a graph illustrating a residual voltage brightness unevenness generated in a middle area of a display panel in a display device according to an embodiment of the disclosure.

[0018] Figure 8 is a graph illustrating a data voltage and a duty cycle of a light emission signal in a display device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0019] Advantages and features of the disclosure, and methods of achieving the advantages and features will become apparent by referring to the embodiments described later in detail together with the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, the embodiments are presented only to make the disclosure more complete and to give a full appreciation of the scope of the disclosure to those skilled in the art to which the disclosure belongs, and the disclosure is limited only by the scope of the claims.

[0020] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the accompanying drawings for describing the embodiments of the disclosure are exemplary, and the disclosure is not limited thereto. The same reference numerals refer to the same elements throughout this document. Also, for simplicity of description, the description and details of well-known steps and elements are omitted. Also, in the following detailed description of the disclosure, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be understood that the disclosure can be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits are not described in detail to avoid unnecessarily obscuring aspects of the disclosure.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and "comprising", when used in this specification, specify the presence of stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. In the interpretation of the specification and of the claims, it is expressly intended that the terms "comprises", "comprising", "includes", "including", "has", "having" or any other variations thereof be construed as maintaining the open-ended nature of the description and are intended to cover both the recited features and also additional features not recited. The terms "a" or "an", as used herein, mean "one or more" when applied to any element. Throughout this document, the term "about" is used to indicate that exact values are not necessary to achieve the desired result, and that a range of values will be deemed to be acceptable as being "about" a stated value. Such terms should be interpreted in the light of the description and should be interpreted to cover not only the explicitly stated values but also values which are reasonably close thereto in the context of the technology.

[0022] Moreover, it is to be understood that when a first element or layer is referred to as being "on" a second element or layer, it can be directly on the second element or layer or intervening elements or layers can also be present. In addition, it should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected to or coupled to the other element or layer, or one or more intervening elements or layers can also be present. Furthermore, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements or layers can also be present.

[0023] In the description of the temporal relationship between two events, such as "after", "subsequently", "before", etc., a temporal precedence between the two events can occur with another event in between unless "immediately", "directly after" or "directly before" is indicated.

[0024] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first element, component, region, layer or section described below can be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0025] The features of the various embodiments of the present disclosure can be combined, in part or in whole, and can be interchanged between the various embodiments, and can be implemented in conjunction with one another or in correlation with one another.

[0026] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation and are intended to account for the inherent deviations in measured or calculated values that would be apparent to one of ordinary skill in the art. These terms can be used to prevent unauthorized infringers from taking advantage of exact or absolute numbers provided to aid in understanding the present disclosure.

[0027] Unless otherwise defined, all terms used herein including technical and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] In describing signal flow relationships, for example, even when "a signal is transmitted from node A to node B," the signal can be transmitted from node A to node B via another node unless "immediately" or "directly" is used.

[0029] Hereinafter, examples of a display device according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In assigning reference numerals to the components of the drawings, the same components can have the same reference numerals regardless of the drawings. Also, the ratio of the respective components shown in the drawings can be different from the actual ratio for convenience of explanation. Therefore, the present disclosure is not limited to the ratio shown in the drawings.

[0030] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0032] Referring to Figure 1 The display device 10 includes a display panel 100 including a plurality of pixels, a gate driver 300 for providing a gate signal to each of the plurality of pixels, a data driver 400 for providing a data signal to each of the plurality of pixels, an emission signal generator 500 for providing an emission signal to each pixel, and a controller 200.

[0033] The controller 200 processes image data RGB inputted from an external device based on the size and resolution of the display panel 100, and provides the processed image data to the data driver 400. Based on an externally inputted synchronization signal SYNC, for example, a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, the controller 200 can generate a gate control signal GCS, a data control signal DCS, and an emission control signal ECS. The controller 200 can provide the gate control signal GCS, the data control signal DCS, and the emission control signal ECS to the gate driver 300, the data driver 400, and the emission signal generator 500, respectively, to control the gate driver 300, the data driver 400, and the emission signal generator 500.

[0034] The controller 200 can be implemented as a combination of various processors, for example, a combination of a microprocessor, a mobile processor, and an application processor.

[0035] The controller 200 generates signals so that the pixels can operate at various refresh rates. That is, the controller 200 generates signals related to the operation so that the pixels operate in a variable refresh rate (VRR) mode or the refresh rate of the pixels is switchable between a first refresh rate and a second refresh rate. For example, the controller 200 can simply change the speed of a clock signal, generate a synchronization signal to generate a horizontal blanking or a vertical blanking, or operate the gate driver 300 in a mask scheme so that the pixels can operate at various refresh rates.

[0036] In addition, the controller 200 generates various signals for operating the pixels at the first refresh rate. In particular, when the pixels operate at the first refresh rate, the controller 200 can generate the emission control signal ECS so that the emission signal generator 500 generates the emission signal EM(n) having a first duty ratio. Thereafter, the controller 200 can operate the pixels at the second refresh rate. For this purpose, the controller 200 generates various signals for operating the pixels at the second refresh rate. In particular, when the pixels operate at the second refresh rate, the controller 200 can generate the emission control signal ECS so that the emission signal generator 500 generates the emission signal EM(n) having a second duty ratio different from the first duty ratio.

[0037] The gate driver 300 provides a scan signal SC to the gate line GL based on the gate control signal GCS provided from the controller 200. In Figure 1 The gate driver 300 is illustrated as being disposed at one side of the display panel 100 and spaced apart from the display panel 100. However, the number and position of the gate driver 300 are not limited thereto. That is, the gate driver 300 can be disposed at one side of the display panel 100 or each of two opposite sides in a GIP (Gate In Panel) scheme.

[0038] The data driver 400 converts the image data RGB into a data voltage Vdata based on a data control signal DCS provided from the controller 200, and supplies the converted data voltage Vdata to the pixels through the data lines DL.

[0039] In the display panel 100, a plurality of gate lines GL and a plurality of emission lines EL intersect with a plurality of data lines DL. Each of the plurality of pixels is connected to the gate line GL, the emission line EL, and the data line DL. Specifically, one pixel receives a scan signal from the gate driver 300 through the gate line GL, receives a data voltage from the data driver 400 through the data line DL, receives an emission signal EM(n) through the emission line EL, and receives various electric powers through the power supply line. In this regard, the gate line GL supplies a scan signal SC, the emission line EL supplies an emission signal EM(n), and the data line DL supplies a data voltage Vdata. However, according to various embodiments, the gate line GL can include a plurality of scan signal lines, and the data line DL can further include a plurality of power supply lines VL. Also, the emission line EL can include a plurality of emission signal lines. Also, the pixel receives a high potential voltage ELVDD and a low potential voltage ELVSS. Also, one pixel can receive a first bias voltage V1 and a second bias voltage V2 through two power supply lines VL.

[0040] Also, each pixel includes an emission element ELD and a pixel circuit that controls an operation of the emission element ELD. In this regard, the emission element ELD is composed of an anode, a cathode, and an organic emission layer located between the anode and the cathode. The pixel circuit includes a plurality of switching elements, a driving element, and a capacitor. In this regard, the switching elements and the driving element can be implemented as TFTs. In the pixel circuit, the driving TFT controls an amount of current supplied to the emission element ELD based on a difference between the data voltage charged in the capacitor and a reference voltage, to adjust an emission amount of the emission element ELD. Also, the plurality of switching TFTs receive a scan signal SC supplied through the gate line GL and an emission signal EM(n) supplied through the emission line EL, and charge the data voltage Vdata in the capacitor based on the received signals.

[0041] The display device 10 according to the embodiment of the present disclosure includes a gate driver 300, a data driver 400, and an emission signal generator 500 for operating a display panel 100 including a plurality of pixels, and a controller 200 for controlling the gate driver 300, the data driver 400, and the emission signal generator 500. In this regard, the emission signal generator 500 is configured to be able to adjust a duty cycle of an emission signal EM(n). For example, the emission signal generator 500 can include a shift register and a latch to adjust the duty cycle of the emission signal EM(n). When the pixels are operated at a first refresh rate, the emission signal generator 500 generates an emission signal EM(n) having a first duty cycle based on an emission control signal ECS generated from the controller 200 and provides the generated emission signal to the pixel circuit. When the pixels are operated at a second refresh rate, the emission signal generator 500 generates an emission signal EM(n) having a second duty cycle based on the emission control signal ECS generated from the controller 200 and provides the generated emission signal to the pixel circuit, wherein the second duty cycle is different from the first duty cycle.

[0042] FIG. 2 is an exemplary circuit diagram of a pixel circuit in a display device according to an embodiment of the present disclosure.

[0043] FIG. 2 only shows an example for the pixel circuit for illustration. The structure of the pixel circuit is not particularly limited as long as the pixel circuit receives an emission signal EM(n) and controls emission of an emission element ELD based on the emission signal. For example, the pixel circuit can include an additional scan signal, a switching TFT to which the additional scan signal is applied, and a switching TFT to which an additional initialization voltage is applied. The connection relationship between the switching elements or the connection position of the capacitor can be variously modified. That is, various structures of the pixel circuit can be used as long as emission of the emission element ELD is controlled according to a change in the duty cycle of the emission signal EM(n) so that the emission is controlled according to the refresh rate. For example, various pixel circuits such as 3T1C, 4T1C, 6T1C, 7T1C, 7T2C can be used. Hereinafter, for convenience of explanation, an example of the display device having the pixel circuit of 7T1C in FIG. 2 will be described.

[0044] Referring to FIG. 2, each of the plurality of pixels P can include a pixel circuit having a driving transistor DT and an emission element ELD connected to the pixel circuit.

[0045] The pixel circuit can control a drive current flowing through the light emitting element ELD to operate the light emitting element ELD. The pixel circuit can include a drive transistor DT, first to sixth transistors T1 to T6, and a storage capacitor Cst. Each of the transistors DT, T1 to T6 can include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode can function as a source electrode, and the other of the first electrode and the second electrode can function as a drain electrode.

[0046] Each of the transistors DT, T1 to T6 can be implemented as a PMOS transistor or an NMOS transistor. In an embodiment of the present disclosure, Figure 2A and Figure 2B In an embodiment of the present disclosure, the first transistor T1 is implemented as an NMOS transistor, and each of the remaining transistors DT, T2 to T6 is implemented as a PMOS transistor. Further, in an embodiment of the present disclosure, Figure 2C In an embodiment of the present disclosure, each of the transistors DT, T1 to T6 is implemented as a PMOS transistor.

[0047] Hereinafter, an example in which the first transistor T1 is implemented as an NMOS transistor and each of the remaining transistors DT, T2 to T6 is implemented as a PMOS transistor will be described. Accordingly, the first transistor T1 receives a high-level voltage to be turned on, and each of the remaining transistors DT, T2 to T6 receives a low-level voltage to be turned on.

[0048] According to an example, the first transistor T1 constituting the pixel circuit can function as a compensation transistor, the second transistor T2 constituting the pixel circuit can function as a data supply transistor, each of the third transistor T3 and the fourth transistor T4 constituting the pixel circuit can function as a light emission control transistor, and each of the fifth transistor T5 and the sixth transistor T6 constituting the pixel circuit can function as a bias transistor.

[0049] The light emitting element ELD can include a pixel electrode (or an anode) and a cathode. The pixel electrode of the light emitting element ELD can be connected to the fifth node N5, and the cathode can be connected to the second power supply voltage ELVSS.

[0050] The drive transistor DT can include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The drive transistor DT can provide a drive current to the light emitting element ELD based on a voltage of the first node N1 (or a data voltage stored in the capacitor Cst which will be described later).

[0051] The first transistor T1 can include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode receiving a first scan signal SC1(n). The first transistor T1 can be turned on in response to the first scan signal SC1(n), and thus can connect the third node N3 to the first node N1. The first transistor T1 can be connected and disposed in a diode manner between the first node N1 and the third node N3, and can sample a threshold voltage Vth of the driving transistor DT. The first transistor T1 can function as a compensation transistor.

[0052] The capacitor Cst can be connected and disposed between the first node N1 and the fourth node N4. The capacitor Cst can store or maintain a provided data signal Vdata.

[0053] The second transistor T2 can include a first electrode connected to a data line DL (or receiving a data signal Vdata), a second electrode connected to the second node N2, and a gate electrode receiving a second scan signal SC2(n). The second transistor T2 can be turned on in response to the second scan signal SC2(n), and thus can transmit the data signal Vdata to the second node N2. The second transistor T2 can function as a data supply transistor.

[0054] The third transistor T3 and the fourth transistor T4 (or first and second light emission control transistors) can be connected and disposed between the first power voltage ELVDD and the light emitting element ELD, and thus can constitute a current moving path in which a driving current generated from the driving transistor DT moves.

[0055] The third transistor T3 can include a first electrode connected to the fourth node N4 to receive the first power voltage ELVDD, a second electrode connected to the second node N2, and a gate electrode receiving a light emission signal EM(n).

[0056] Similarly, the fourth transistor T4 can include a first electrode connected to the third node N3, a second electrode connected to a fifth node N5 (or a pixel electrode of the light emitting element ELD), and a gate electrode receiving the light emission signal EM(n).

[0057] The third transistor T3 and the fourth transistor T4 can be turned on in response to the light emission signal EM(n). In this case, the driving current can be supplied to the light emitting element ELD, and thus the light emitting element ELD can emit light with a brightness corresponding to the driving current.

[0058] The fifth transistor T5 can include a first electrode connected to the third node N3, a second electrode receiving a first bias voltage V1, and a gate electrode receiving a third scan signal SC3(n).

[0059] The sixth transistor T6 can include a first electrode connected to the fifth node N5, a second electrode receiving the second bias voltage V2, and a gate electrode receiving the third scan signal SC3(n). In Figure 2A In the above, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to commonly receive the third scan signal SC3(n). However, the present disclosure is not necessarily limited thereto. As shown in Figure 2B and Figure 2C The gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to receive separate scan signals, respectively, so as to be independently controlled.

[0060] The sixth transistor T6 can be turned on in response to the third scan signal SC3(n) before (or after) the light emitting element ELD performs light emission. The sixth transistor T6 can initialize the pixel electrode (or anode) of the light emitting element ELD based on the second bias voltage V2. The light emitting element ELD can have a parasitic capacitance formed between the pixel electrode and the cathode. In addition, the parasitic capacitance can be charged when the light emitting element ELD emits light, so that the pixel electrode of the light emitting element ELD can have a specific voltage. Accordingly, the second bias voltage V2 can be applied to the pixel electrode of the light emitting element ELD through the sixth transistor T6, thereby initializing the amount of charge accumulated in the light emitting element ELD.

[0061] Figure 3A and Figure 3B are diagrams for explaining the operation of the pixel circuit and the light emitting element of the display apparatus shown in Figure 2A

[0062] Referring to Figure 3A and Figure 3B , each of the plurality of pixels P can initialize a voltage charged or remaining in the pixel circuit. Specifically, the influence of the data voltage Vdata stored in the previous frame can be removed. Accordingly, each of the plurality of pixels P can display an image corresponding to a new data voltage Vdata.

[0063] The operation of the pixel circuit can include at least one initialization period, a sampling period, and a light emission period. However, this is only one embodiment. The present disclosure is not necessarily limited to this order.

[0064] ​The display device according to the embodiment of the present disclosure can be separately operated in each of a refresh frame and a reset frame. In the refresh frame, a data voltage Vdata can be programmed in each pixel P, and thus the light emitting element ELD can emit light. Further, the reset frame can be a vertical blanking frame. The anode of the light emitting element ELD can be reset during the reset frame. As used herein, the terms "frame", "refresh frame", and "reset frame" can refer to the concept of a period of time. In some cases, the terms "frame", "refresh frame", and "reset frame" can refer to an image or an operation mode.

[0065] In the display device according to the embodiment of the present disclosure, the refresh frame can be divided into an on-bias stress period Tobs (hereinafter referred to as a "stress period"), an initialization period Ti, a sampling period Ts, and a light emission period Te. The stress period Tobs refers to a period in which a bias stress is applied to the third node N3 which is a drain electrode of the driving transistor DT. The initialization period Ti refers to a period in which a voltage of the third node N3 which is a drain electrode of the driving transistor DT is initialized. The sampling period Ts refers to a period in which the threshold voltage Vth of the driving transistor DT is sampled and a data voltage Vdata is programmed. The light emission period Te refers to a period in which the light emitting element ELD emits light based on a driving current generated by the programmed gate-source voltage of the driving transistor DT.

[0066] Specifically, referring to Figure 3A During the first stress period Tobs, the third scan signal SC3(n) has a low level as an on level. Thus, the fifth transistor T5 can be turned on to apply the first bias voltage V1 from the power supply line VL to the third node N3. The first bias voltage V1 can refer to a stress voltage Vobs or an initialization voltage Vini. The stress voltage Vobs can be selected from a voltage range sufficiently higher than an operating voltage of the light emitting element ELD, and can be set to be equal to or lower than a voltage of the first driving power source ELVDD. That is, during the stress period Tobs, a bias stress can be applied to the third node N3 which is a drain electrode of the driving transistor DT, and thus a gate-source voltage Vgs of the driving transistor DT can be reduced. Thus, during the stress period Tobs, a source-drain current of the driving transistor DT can flow, and thus a hysteresis of the driving transistor DT can be reduced.

[0067] Further, the sixth transistor T6 can be turned on to apply the second bias voltage V2 to the fifth node N5. That is, the anode of the light emitting element ELD is reset to the second bias voltage V2. The second bias voltage V2 can refer to a reset voltage VAR.

[0068] Further, referring to Figure 3ADuring the initialization period Ti, the first scan signal SC1(n) has a high level as an on level, and the third scan signal SC3(n) has a low level as an on level. Therefore, the first transistor T1 and the fifth transistor T5 can be turned on to apply the initialization voltage Vini from the power supply line VL to the first node N1. As a result, the gate electrode of the drive transistor DT can be initialized based on the initialization voltage Vini. The initialization voltage Vini can be selected from a voltage range sufficiently lower than an operating voltage of the light emitting element ELD, and can be set to be equal to or lower than a voltage of the second drive power supply ELVSS. Further, during the initialization period Ti, the sixth transistor T6 can be turned on again so that the reset voltage VAR is applied to the fifth node N5.

[0069] Further, with reference to Figure 3A During the sampling period Ts, the first scan signal SC1(n) has a high level as an on level, and the second scan signal SC2(n) has a low level as an on level. Further, during the sampling period Ts, the second transistor T2 is turned on so that the data voltage Vdata is applied to the second node N2. Further, the first transistor T1 is turned on so that the drive transistor DT is connected in a diode manner, and thus the gate electrode and the drain electrode of the drive transistor DT are short-circuited to each other. Therefore, the drive transistor DT operates like a diode.

[0070] During the sampling period Ts, a current flows between the source electrode and the drain electrode of the drive transistor DT. Because the gate electrode and the drain electrode of the drive transistor DT are connected in a diode manner to each other, the voltage of the first node N1 rises due to the current flowing from the source electrode to the drain electrode until the gate-source voltage Vgs of the drive transistor DT becomes the threshold voltage Vth of the drive transistor DT.

[0071] Further, with reference to Figure 3A During the second stress period Tobs, the third scan signal SC3(n) has a low level as an on level. Therefore, the sixth transistor T6 is turned on so that the reset voltage VAR is applied to the fifth node N5. That is, the anode of the light emitting element ELD is reset to the reset voltage VAR. Further, the fifth transistor T5 can be turned on to apply the stress voltage Vobs to the third node N3. That is, the bias stress is applied to the third node N3 which is the drain electrode of the drive transistor DT during the stress period Tobs, and the hysteresis effect of the drive transistor DT can be reduced.

[0072] Further, with reference to Figure 3ADuring the light emission period Te, the light emission signal EM(n) is at a low level as an on level. Therefore, the third transistor T3 is turned on, so that the first drive power source ELVDD is applied to the second node N2. Further, since the first node N1 is coupled to the first drive power source ELVDD via the storage capacitor Cst, the first drive power source ELVDD is also reflected in the first node N1. Further, the fourth transistor T4 is turned on, thereby forming a current path between the third node N3 and the fifth node N5. As a result, the drive current flowing through the source electrode and the drain electrode of the drive transistor DT is applied to the light emitting element ELD. Further, referring to Figure 3B During the reset frame, the first scan signal SC1(n) is maintained at a low level as an off level, and the second scan signal SC2(n) is maintained at a high level as an off level. Therefore, the data voltage Vdata is not programmed in each pixel P during the reset frame.

[0073] However, the third scan signal SC3(n) can be periodically wobbled. That is, when the third scan signal SC3(n) is periodically wobbled, the reset frame can include a plurality of stress periods Tobs. However, the present disclosure is not limited thereto, and the reset frame can include one stress period Tobs, as Figure 3B shown.

[0074] In other words, during the reset frame, the anode of the light emitting element ELD can be reset to the reset voltage VAR, and the bias stress can be applied to the third node N3 as the drain electrode of the drive transistor DT.

[0075] Finally, in the display device according to the embodiment of the present disclosure, the anode of the light emitting element ELD can be periodically reset during the refresh frame and the reset frame. Therefore, it is possible to prevent the voltage of the anode of the light emitting element ELD from continuously increasing due to the leakage current, so that the anode of the light emitting element ELD can maintain a constant voltage level. Therefore, it is possible to minimize the luminance variation of the display device, so that it is possible to improve the image quality.

[0076] Figure 4 is a graph showing the band-based dimming level of a pixel circuit in a display device according to an embodiment of the present disclosure.

[0077] Referring to Figure 4The display panel 100 can include a plurality of frequency bands Band1, Band2, Band3, …, Band13, such that the target luminance Lv varies based on the operating environment. The dimming level can be adjusted based on the plurality of frequency bands Band1, Band2, Band3, …, Band13. For example, the first frequency band Band1 can be correspondingly set for a case in which the display device needs the highest maximum target luminance Lv based on the ambient illuminance of the day. The second frequency band Band2 can be correspondingly set for a case in which the display device exists in the shade during the day. The seventh frequency band Band7 can be correspondingly set for a case in which the display device exists in overcast weather. The eighth frequency band Band8 can be correspondingly set for a case in which the display device exists in a night-time environment. The thirteenth frequency band Band13 can be correspondingly set for a case in which the display device exists in a dark room environment. In addition, the frequency bands can be further subdivided and classified according to various usage environments and applications.

[0078] In each of the plurality of frequency bands Band1, Band2, Band3, …, Band13, the dimming level can vary to adjust the luminance step at a particular gray level. In addition, the maximum target luminance Lv of each of the plurality of frequency bands Band1, Band2, Band3, …, Band13 can be set such that the plurality of frequency bands Band1, Band2, Band3, …, Band13 can have the same number of luminance steps. For example, there can be 256 luminance steps between the maximum target luminance Lv of the first frequency band Band1 and the maximum target luminance Lv of the second frequency band Band2.

[0079] The dimming level for adjusting the luminance can vary in the range of 0 to 100%. Even at the same gray level, the dimming level can differ from frequency band to frequency band, and thus the luminance can differ from frequency band to frequency band. For example, the maximum target luminance Lv of the first frequency band Band1 can have a dimming level of 100%. In addition, the dimming level can be adjusted based on the data voltage applied to the pixel and / or can be adjusted based on the duty cycle of the emission signal EM(n) applied to the pixel.

[0080] Figure 5A FIG. 1 is a diagram illustrating a frequency band-based dimming level adjustment scheme of a pixel circuit in a display device according to an embodiment of the disclosure. Figure 5B FIG. 2 is a diagram illustrating an emission signal having a duty cycle that varies according to a frequency band.

[0081] Referring to Figure 5AIn each of the plurality of frequency bands Band1, Band2, Band3, …, Band13, the dimming level can be adjusted based on at least one of a data voltage Vdata applied to the pixel or a duty cycle of an emission signal EM(n) applied to the pixel.

[0082] The maximum target luminance Lv of one of the plurality of frequency bands Band1, Band2, Band3, …, Band13 can be equal to the minimum target luminance Lv of another of the plurality of frequency bands Band1, Band2, Band3, …, Band13. For example, the minimum target luminance Lv of the first frequency band Band1 can be equal to the maximum target luminance Lv of the second frequency band Band2.

[0083] Each of the first to seventh frequency bands Band1, Band2, …, Band7 has a relatively high target luminance Lv. Therefore, the amount of luminance change based on the gray scale will be large. In this regard, the luminance corresponds to the data voltage Vdata. The data voltage Vdata can be adjusted, and thus the dimming level can be adjusted.

[0084] Each of the eighth to thirteenth frequency bands Band8, Band9, …, Band13 has a relatively low target luminance Lv. Therefore, the amount of luminance change based on the gray scale will be small. Therefore, when the dimming level is adjusted based on the data voltage Vdata, the pixel can not operate normally. Therefore, in each of the eighth to thirteenth frequency bands Band8, Band9, …, Band13, the dimming level can be adjusted based on a duty cycle of the emission signal EM(n).

[0085] In other words, in each of the first to seventh frequency bands Band1, Band2, …, Band7, the duty cycle of the emission signal EM(n) can be fixed, and the data voltage Vdata can be changed so that the dimming level can be adjusted. Also, in each of the eighth to thirteenth frequency bands Band8, Band9, …, Band13, the data voltage Vdata can be fixed, and the duty cycle of the emission signal EM(n) can be changed so that the dimming level can be adjusted.

[0086] Referring to Figure 5BThe light emission signal EM(n) can have a duty cycle that varies based on the frequency band. The voltage waveform of the second node N2 to which the third transistor T3 connected based on the light emission signal EM(n) can vary based on the duty cycle of the light emission signal EM(n). For example, in the first frequency band Band1 in which the duty cycle of the light emission signal EM(n) is about 90%, the voltage waveform of the second node N2 has a form that is continuously maintained when the light emission signal EM(n) is applied. Also, in the thirteenth frequency band Band13 in which the duty cycle of the light emission signal EM(n) is about 9%, the voltage waveform of the second node N2 can change at the instant when the light emission signal EM(n) is applied.

[0087] Figure 6 FIG. 1 is a diagram illustrating an operation of a scan signal during one frame in a display device according to an embodiment of the disclosure.

[0088] As Figure 6 indicated, each of the plurality of pixels P is operated at a constant frequency. At this time, when high-speed operation is required, the pixel circuit is operated at an increased refresh rate. The refresh rate refers to the rate at which the data voltage Vdata is refreshed. When low power consumption is required or low-speed operation is required, the pixel circuit can be operated at a reduced refresh rate. As such, the pixel circuit can operate in a variable refresh rate (VRR) mode.

[0089] In this regard, the third scan signal SC3(n) for driving the sixth transistor T6 provided from the gate driver 300 can have a frequency that is twice the operation frequency provided to the display panel 100 from the controller 200.

[0090] For example, when the refresh rate is 120 Hz, the operation frequency can be 120 Hz, and the frequency of the third scan signal SC3(n) for turning on the TFT can be 240 Hz. That is, since the frequency of the third scan signal SC3(n) is twice the operation frequency, the sixth transistor T6 is turned on an increased number of times, and thus the fifth node N5 can be initialized more frequently, and thus the performance of the driving transistor DT can be improved.

[0091] Referring to Figure 6 , the period in which the data voltage Vdata is applied can be an active period, and the period in which the data voltage is not applied can be a blanking period.

[0092] When the data line DL is in a floating state during the blanking period, the data line DL can affect the first node N and the second node N2 adjacent thereto through coupling. This can cause flicker.

[0093] Accordingly, in response to operation in a variable refresh rate (VRR) mode, a data voltage Vdata can be applied to the data line DL for an active period, and then a sustain voltage Vpark can be applied to the data line DL for a blanking period before a data voltage Vdata of a next frame is applied.

[0094] In this regard, when a sustain voltage Vpark of a certain voltage level is applied, one sustain voltage Vpark must be used to adjust the flicker performance of all gray scales. Accordingly, based on a relationship between the levels of the data voltage Vdata and the sustain voltage Vpark, luminance unevenness such as a spot can occur at a certain gray scale. The luminance unevenness such as a spot is referred to as sustain voltage luminance unevenness Vpark Mura.

[0095] Further, when a sustain voltage Vpark of a certain voltage level is applied during blanking, since the third scan signal SC3(n) sequentially applied to the gate line GL has a frequency twice as high as the operating frequency, the sixth transistor T6 in each of the plurality of pixels located in the middle region of the display panel 100 can be turned on. Accordingly, coupling occurs between the data line DL and the fifth node N5, thereby causing sustain voltage luminance unevenness Vpark Mura in the middle region of the display panel 100, and thus uniformity is reduced.

[0096] The sustain voltage luminance unevenness Vpark Mura based on the voltage level of the sustain voltage Vpark is more sensitive at low gray scales than at high gray scales. Accordingly, the light emitting element ELD can unnecessarily emit light at low gray scales.

[0097] Figure 7 FIG. 1 is a diagram illustrating sustain voltage luminance unevenness generated in a middle region of a display panel in a display apparatus according to an embodiment of the disclosure.

[0098] Referring to Figure 7 The sustain voltage luminance unevenness Vpark Mura generated in the middle region of the display panel 100 can have 3 types based on driving timing.

[0099] In the A zone, when the fifth transistor T5 is turned off by the third scan signal SC3(n+i), the voltage applied to the data line changes from the data voltage Vdata to the sustain voltage Vpark, and thus a voltage change due to the change can be identified.

[0100] In other words, when the fifth transistor T5 is turned off by the third scan signal SC3(n+i), the stress voltage Vobs is not applied to the third node N3, and thus the third node N3 is in a floating state, so that the second node N2 and the third node N3 have the same potential. At this time, when the voltage applied to the data line changes from the data voltage Vdata to the park voltage Vpark, coupling between the second node N2 and the data line DL to which the data voltage Vdata or the park voltage Vpark is applied occurs, so that the source voltage and the drain voltage of the drive transistor DT can temporarily differ from each other. That is, a transient potential difference is generated between the third node N3 and the second node N2 connected to the drive transistor DT. When the third transistor T3 is turned on by the emission signal EM(n+i) before the second node N2 and the third node N3 again have the same potential, this affects the drive current flowing through the light emitting element ELD, resulting in a rapid decrease in brightness. Thus, a dark spot can be identified.

[0101] Conversely, in the C region, when the fifth transistor T5 is turned off by the third scan signal SC3(n+k), the voltage applied to the data line changes from the park voltage Vpark to the data voltage Vdata, so that the drain voltage and the source voltage of the drive transistor DT can temporarily differ from each other. When the third transistor T3 is turned on by the emission signal EM(n+k), the brightness rapidly increases. Thus, a bright spot can be identified.

[0102] In the B region, at the time when the voltage applied to the data line changes from the data voltage Vdata to the park voltage Vpark, the fifth transistor T5 is in a state of being turned on by the third scan signal SC3(n+j). Thus, since the stress voltage Vobs is applied to the third node N3, the potential of the third node N3 is not changed or affected due to the change of the voltage applied to the data line from the data voltage Vdata to the park voltage Vpark. In addition, even if the voltage applied to the data line changes from the park voltage Vpark to the data voltage Vdata, the potential of the third node N3 is not affected during the period in which the third transistor T3 is in a state of being turned on by the emission signal EM(n).

[0103] In this way, depending on the driving timing of the third scan signal SC3(n) and the emission signal EM(n), the influence of the change timing of the active period and the blanking period on the A region, the B region, and the C region of the middle area of the display panel 100 can be identified on the screen.

[0104] Figure 8 FIG. 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0105] Referring to Figure 8The sustain voltage Vpark applied during the blanking period can have a first duty ratio W1, and the light emission signal EM(n) can have a second duty ratio W2. In this regard, in at least one of the plurality of frequency bands Band1, Band2, Band3,..., Band13, the second duty ratio W2 of the low level as the on level of the light emission signal EM(n) can be less than the first duty ratio W1 of the sustain voltage Vpark.

[0106] In other words, the sustain voltage brightness unevenness Vpark mura is more sensitively recognized during the low gray scale of the low luminance. Therefore, in at least one of the eighth to thirteenth frequency bands Band8, Band9,..., Band13 having a relatively low target luminance Lv, the second duty ratio W2 of the light emission signal EM(n) can be less than the first duty ratio W1 of the sustain voltage Vpark.

[0107] For example, when the sustain voltage Vpark applied during the blanking period has a first duty ratio W1 of 40 horizontal periods, the second duty ratio W2 of the on level of the light emission signal EM(n) can be set to a value less than or equal to 36 horizontal periods (90% of the first duty ratio W1).

[0108] In this case, in the thirteenth frequency band Band13 in which the light emission signal EM(n) has the minimum duty ratio, the light emission signal EM(n) can have a duty ratio of about 8%.

[0109] Further, the middle region of the display panel 100 is affected by the timing at which the voltage applied to the data line changes between the data voltage Vdata and the sustain voltage Vpark. Therefore, the light emission signal EM(n) can become the on level when at least 3 horizontal periods have passed after the third scan signal SC3(n) becomes the high level as the off level. In other words, the time at which the light emission signal EM(n) becomes the on level can not overlap with the time at which the voltage applied to the data line changes. That is, the light emitting element ELD emits light only after the temporary difference between the source voltage and the drain voltage of the drive transistor DT generated due to the coupling is eliminated. Therefore, even when the third scan signal SC3(n) becomes the off level, and the applied voltage changes from the data voltage Vdata to the sustain voltage Vpark, or from the sustain voltage Vpark to the data voltage Vdata again, the viewer does not see the sustain voltage brightness unevenness Vpark mura. Therefore, the uniformity of the display panel 100 can be improved, and thus the image quality can be improved.

[0110] The display apparatus according to an embodiment of the disclosure can be described as follows.

[0111] One aspect of the present disclosure provides a display apparatus including a display panel including a plurality of pixels connected to a data line and a gate line; a data driver configured to apply a data voltage to the data line for an active period and to apply a sustain voltage to the data line for a blanking period in which the data voltage is not applied; a gate driver to apply a scan signal to the gate line; a light emission signal generator to apply a light emission signal to the plurality of pixels; and a controller configured to operate the display apparatus based on a plurality of frequency bands, wherein the plurality of frequency bands have different maximum target brightness levels based on an operating environment of the display apparatus, wherein a duty cycle of the light emission signal is less than a duty cycle of the sustain voltage in at least one frequency band of the plurality of frequency bands.

[0112] In one embodiment of the display apparatus, a duty cycle of the light emission signal is equal to or less than about 90% of a duty cycle of the sustain voltage.

[0113] In one embodiment of the display apparatus, each of the plurality of pixels includes a light emitting element to emit light in response to a drive current; a drive transistor to control the drive current, wherein the drive transistor includes a gate electrode acting as a first node, a source electrode acting as a second node, and a drain electrode acting as a third node; a first transistor to diode-connect the first node and the third node to each other; a second transistor to apply the data voltage or the sustain voltage to the second node; a third transistor to apply a high potential voltage from a fourth node to the second node; a fourth transistor to constitute a current path between the drive transistor and the light emitting element; a fifth transistor to apply a first bias voltage to the third node; a sixth transistor to apply a second bias voltage to a fifth node, wherein an anode of the light emitting element acts as the fifth node; and a storage capacitor, one electrode of the storage capacitor being connected to the first node and the other electrode being connected to the fourth node.

[0114] In one embodiment of the display apparatus, an operating period of the display apparatus includes a stress period, an initialization period, a sampling period, and a light emission period, wherein during the stress period, a stress voltage is applied to the drain electrode of the drive transistor, wherein during the initialization period, the first node and the third node are initialized based on an initialization voltage, wherein during the sampling period, the data voltage is applied to the second node, and wherein during the light emission period, the drive current is applied to the light emitting element to perform light emission.

[0115] In one embodiment of the display apparatus, the scan signal includes a first scan signal to control the first transistor, a second scan signal to control the second transistor, and a third scan signal to control the fifth transistor.

[0116] In one embodiment of the display device, the timing at which the light emission signal becomes the on level does not overlap with the timing at which the voltage applied to the data line changes.

[0117] In one embodiment of the display device, the light emission signal becomes the on level when at least 3 horizontal periods have passed after the third scan signal becomes the off level.

[0118] In one embodiment of the display device, the controller is configured to change the operation frequency based on the refresh rate, wherein the frequency of the third scan signal is higher than the operation frequency.

[0119] In one embodiment of the display device, the frequency of the third scan signal is twice or more than the operation frequency.

[0120] In one embodiment of the display device, the frequency of the light emission signal is four times higher than the operation frequency.

[0121] In one embodiment of the display device, in a frequency band having the lowest maximum target brightness level among the plurality of frequency bands, the duty cycle of the light emission signal is about 8%.

[0122] In one embodiment of the display device, the plurality of frequency bands include first to thirteenth frequency bands, wherein in each of the first to thirteenth frequency bands, the dimming level is adjusted based on the duty cycle of the light emission signal or the magnitude of the data voltage.

[0123] The features, structures, effects, and the like described in the above-described embodiments of the present disclosure are included in at least one example of the present disclosure, and are not necessarily limited to one example. Furthermore, the features, structures, effects, and the like disclosed in at least one example of the present disclosure can be combined or modified by those skilled in the art to which the present disclosure pertains in another example. Therefore, matters related to these combinations and modifications should be understood to be included in the scope of the present disclosure.

[0124] The scope of protection of the present disclosure should be construed based on the scope of claims, and the technical ideas equivalent thereto should be understood to be included in the scope of the present disclosure. Although the embodiments of the present disclosure have been described in detail with reference to the drawings, the present disclosure is not necessarily limited to the embodiments. The present disclosure can be implemented in various modified forms without departing from the technical ideas of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical ideas of the present disclosure, but to describe the present disclosure. The scope of the technical ideas of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the above-described embodiments are illustrative rather than restrictive in all aspects. The scope of protection of the present disclosure should be construed based on the claims, and the technical ideas within the scope of the present disclosure should be understood to be included in the scope of the present disclosure.

Claims

1. A display device comprising: a display panel including a plurality of pixels each connected to a respective data line and a respective gate line; a data driver configured to apply a data voltage to the data lines for an active period and to apply a sustain voltage to the data lines for a blanking period in which the data voltage is not applied; a gate driver for applying a scan signal to the gate lines; a light emission signal generator for applying a light emission signal to the plurality of pixels; and a controller configured to operate the display device based on a plurality of frequency bands having different maximum target luminance levels based on an operating environment of the display device, wherein, in at least one of the plurality of frequency bands, a duty cycle of the light emission signal is less than a duty cycle of the sustain voltage, wherein timing at which the light emission signal becomes an on level does not overlap with timing at which a voltage applied to the data line changes between the data voltage and the sustain voltage. The duty cycle of the light emission signal is equal to or less than 90% of the duty cycle of the sustain voltage.

2. The display device according to claim 1, wherein Each of the plurality of pixels includes:

3. The display device according to claim 1, wherein a light emitting element for emitting light according to a drive current; a drive transistor for controlling the drive current, wherein the drive transistor includes a gate electrode serving as a first node, a source electrode serving as a second node, and a drain electrode serving as a third node; a data supply transistor connected between the data line and the second node; a first light emission control transistor connected between a high potential voltage and the second node; and a first bias transistor connected between a first bias voltage and the third node. A refresh frame of the display device includes a stress period, a sampling period, and a light emission period, 4. The display device according to claim 3, wherein wherein, during the stress period, the first bias transistor is turned on to apply the first bias voltage to the third node, wherein, during the sampling period, the data supply transistor is turned on to apply the data voltage to the second node, wherein, during the light emission period, the first light emission control transistor is turned on in response to the light emission signal to apply the high potential voltage to the second node. Each of the plurality of pixels further includes:

5. The display device according to claim 3, wherein a second bias transistor connected between a second bias voltage and an anode of the light emitting element. Each of the plurality of pixels further includes:

6. The display device according to claim 3, wherein a second light emission control transistor connected between the third node and the anode of the light emitting element. Each of the plurality of pixels further includes:

7. The display device according to claim 3, wherein a compensation transistor for diode-connecting the first node and the third node to each other. The stress period includes a first stress period located before the sampling period, and a second stress period located between the sampling period and the light emission period.

8. The display device according to claim 4, wherein The light emission signal becomes the on level after at least 3 horizontal periods have elapsed since the first bias transistor is turned off.

9. The display device according to claim 3, wherein The controller is configured to change an operating frequency of the display device based on a refresh rate of the data voltage, 10. The display device according to claim 4, wherein wherein a frequency of the stress period is higher than the operating frequency. The frequency of the stress period is two or more times the operating frequency.

11. The display device of claim 10, wherein, ​ 12. The display device of claim 1, wherein, The light emission signal has a minimum duty cycle in a frequency band of the plurality of frequency bands having a lowest maximum target brightness level.

13. The display device of claim 12, wherein, The light emission signal has a duty cycle of 8% with the minimum duty cycle.

14. The display device of claim 1, wherein, In each of the plurality of frequency bands, a dimming level is adjusted based on at least one of a duty cycle of the light emission signal and a magnitude of the data voltage.

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