Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The method includes selectively removing a first alignment structure formed in a first dielectric layer simultaneously with a first interconnect structure to expose a first alignment trench defined in the first dielectric layer. A conductive layer is then formed over the first dielectric layer, wherein the conductive layer fills a portion of the first alignment trench to form a second alignment structure. The conductive layer is then patterned into a second interconnect structure using the second alignment structure as an alignment mark for a lithography and etching process. The method of the present invention can achieve better alignment accuracy between the first interconnect structure and the second interconnect structure.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including interconnection structures and alignment structures and a method of manufacturing the same. BACKGROUND

[0002] Photolithography is an important step in manufacturing semiconductor devices, which transfers a design pattern on a photo mask to a photoresist layer by exposure and development, and then uses the photoresist layer as an etching mask to etch a material layer underneath, thereby transferring the design pattern to the material layer and manufacturing a circuit structure.

[0003] A semiconductor manufacturing process is a process of repeatedly performing deposition, photolithography and etching to build up an integrated circuit structure of a semiconductor device layer by layer. As the circuit pattern design becomes more and more detailed and compact, the alignment specification between the upper and lower circuit structures becomes more and more stringent, because a slight alignment offset can cause defects such as contact abnormality, short circuit or disconnection. In some cases, a zero mark is also made in the stacked structure to assist alignment. SUMMARY

[0004] The present invention aims to provide a semiconductor device and a method of manufacturing the same, which can improve the alignment accuracy between the upper and lower interconnection structures without omitting the zero mark. Compared with the conventional process which needs to make a zero mark to assist alignment, the present invention omits this step, which not only saves the cost of the photo mask of the zero mark, but also simplifies the process.

[0005] An embodiment of the present invention provides a method of manufacturing a semiconductor device, which includes first providing a substrate, then forming a first dielectric layer on the substrate, and then forming a first interconnection structure and a first alignment structure composed of a first conductive layer in the first dielectric layer. A first photolithography and etching process is performed to remove the first alignment structure and expose a first alignment trench. A second conductive layer is formed to cover the first dielectric layer and the first interconnection structure and fill the first alignment trench, and a second alignment structure is formed, wherein the upper part of the second alignment structure located above the first alignment trench includes a second alignment trench. Then, a second photolithography and etching process is performed to remove the upper part of the second alignment structure and part of the first dielectric layer, and expose the lower part of the second alignment structure located in the first alignment trench. Finally, a third photolithography and etching process is performed to pattern the second conductive layer into a second interconnection structure, wherein the first interconnection structure and the second interconnection structure are electrically connected.

[0006] Another embodiment of the present application provides a semiconductor device, comprising a substrate, a first dielectric layer on the substrate, a first interconnect structure and an alignment structure in the first dielectric layer, a second dielectric layer on the first dielectric layer and covering a top surface of the alignment structure, and a second interconnect structure in the second dielectric layer and directly contacting a top surface of the first interconnect structure. The top surface of the alignment structure is lower than the top surface of the first interconnect structure.

[0007] Yet another embodiment of the present application provides a semiconductor device, comprising a substrate, a first dielectric layer on the substrate, a first interconnect structure and an alignment structure in the first dielectric layer, a second dielectric layer on the first dielectric layer and covering a top surface of the alignment structure, and a second interconnect structure in the second dielectric layer and directly contacting a top surface of the first interconnect structure. The top surface of the alignment structure is lower than the top surface of the first interconnect structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification. The drawings

[0009] Figures 1 to 12 The drawings illustrate the design and implementation of the process for fabricating a semiconductor device according to an embodiment of the present application.

[0010] In the drawings, like reference numerals refer to like elements throughout.

[0011] R1 circuit region

[0012] R2 alignment mark region

[0013] 10 substrate

[0014] 12 interlayer dielectric layer

[0015] 14 conductive structure

[0016] 16 etch stop layer

[0017] 18 first dielectric layer

[0018] 22 interconnect opening

[0019] 26 first interconnect structure

[0020] 32 first photoresist layer

[0021] 34 cap layer

[0022] 36 second photoresist layer

[0023] 38 planarization layer

[0024] 40 anti-reflective layer

[0025] 42 third photoresist layer

[0026] 44 second interconnect structure

[0027] 18a top surface

[0028] 18b top surface

[0029] 18c top surface

[0030] 18d top surface

[0031] 24A first alignment trench

[0032] 24B second alignment trench

[0033] 32a first marker opening

[0034] 36a second marker opening

[0035] A1 first alignment structure

[0036] A2 second alignment structure

[0037] A2a lower portion

[0038] A2b upper portion

[0039] CL1 first conductive layer

[0040] CL2 second conductive layer

[0041] S1 step difference

[0042] S2 step difference

[0043] S3 step difference DETAILED DESCRIPTION

[0044] In order to enable a person familiar in the art to which the present application pertains to further understand the present application, several preferred embodiments of the present application are listed below, and the technical solutions of the present application and the effects to be achieved are described in detail with reference to the accompanying drawings. A person skilled in the art can replace, reorganize, mix the features in several different embodiments to complete other embodiments without departing from the spirit of the present application.

[0045] The figures in the present disclosure only draw a part of the display device, the number and size of each element in the figures are only for illustration, and are not intended to limit the scope of the present disclosure. The relative position of the elements in the figures described herein refers to the relative position of the objects, and therefore can be reversed to show the same components, which should be included in the scope of the present disclosure.

[0046] Figures 1 to 12 The structure shown is involved in the step of the process of the manufacturing method of the semiconductor element according to an embodiment of the present disclosure. Please refer to Figure 1 , first provide a substrate 10, including a circuit area R1 and an alignment mark area R2. Then, form an interlayer dielectric layer 12 on the substrate 10, and then form an etching stop layer 16 and a first dielectric layer 18 on the interlayer dielectric layer 12.

[0047] As Figure 1 shown, the substrate 10 is, for example, a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but not limited to. The substrate 10 can be a substrate that has completed part of the semiconductor process, including structures and circuit elements (not shown in the figure) made therein or thereon. The interlayer dielectric layer 12, the etching stop layer 16 and the first dielectric layer 18 can all be composed of dielectric materials, suitable dielectric materials include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or a combination of the above materials, but not limited to.

[0048] According to an embodiment of the present disclosure, please refer to Figure 1As shown, the ILD layer 12 and the first dielectric layer 18 mainly comprise silicon oxide (SiO2), and the etch stop layer 16 comprises a material different from the ILD layer 12 and the first dielectric layer 18, such as silicon nitride (SiN). According to some embodiments of the present application, the ILD layer 12 of the circuit region Rl can be provided with a conductive structure 14, wherein the conductive structure 14 is mainly composed of a conductive material, and the conductive material can include, but is not limited to, aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), polysilicon, doped silicon, silicide, or any combination thereof. The top surface of the conductive structure 14 is substantially flush with the upper surface of the ILD layer 12, and directly contacts the etch stop layer 16.

[0049] Referring to Figure 2 Next, a photolithography and etching process is performed to form a plurality of interconnection openings 22 in the first dielectric layer 18 of the circuit region Rl, and a plurality of first alignment trenches 24A in the first dielectric layer 18 of the alignment mark region R2. According to some embodiments of the present application, the photolithography and etching process includes transferring a design pattern of the interconnection openings 22 and the first alignment trenches 24A on a photomask to a photoresist layer (not shown) disposed on the first dielectric layer 18 by using a photolithography device (such as a scanning photolithography machine or a step-by-step photolithography machine), and then etching and removing the exposed portions of the first dielectric layer 18 by using the photoresist layer as an etching mask, so as to transfer the design pattern of the interconnection openings 22 and the first alignment trenches 24A to the first dielectric layer 18. According to some embodiments of the present application, the photolithography device is aligned with the photomask and the substrate 10 by using an alignment structure (not shown) formed in the substrate 10 or the ILD layer 12 as an alignment mark, so as to form the interconnection openings 22 and the first alignment trenches 24A at the intended positions. According to some embodiments of the present application, the bottoms of the interconnection openings 22 penetrate the etch stop layer 16 and substantially stop on the conductive structure 14, thereby exposing a portion of the conductive structure 14. The bottoms of the first alignment trenches 24A penetrate the etch stop layer 16 and further extend into the upper portion of the ILD layer 12, so that the bottoms of the first alignment trenches 24A are lower than the bottoms of the interconnection openings 22.

[0050] Referring to Figure 3A first conductive layer CL1 is then formed to completely cover the first dielectric layer 18 and to fill the interconnection opening 22 and the first alignment trench 24A. The first conductive layer CL1 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto.

[0051] Referring to Figure 4 A first conductive layer CL1 is then formed to completely cover the first dielectric layer 18 and to fill the interconnection opening 22 and the first alignment trench 24A. The first conductive layer CL1 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto. Figure 4 As shown in FIG. 2, the top surface of the first alignment structure A1 and the top surface of the first interconnection structure 26 are substantially flush with each other, and the bottom surface of the first alignment structure A1 is lower than the bottom surface of the first interconnection structure 26.

[0052] Referring to Figures 4 to 6 A first conductive layer CL1 is then formed to completely cover the first dielectric layer 18 and to fill the interconnection opening 22 and the first alignment trench 24A. The first conductive layer CL1 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto.

[0053] Referring to Figure 7 After the first photoresist layer 32 is removed, a second conductive layer CL2 is then formed to completely cover the first dielectric layer 18 and the first interconnection structure 26 and to fill the first alignment trench 24A, forming a second alignment structure A2. The second conductive layer CL2 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto. According to some embodiments of the present application, the first conductive layer CL1 and the second conductive layer CL2 can comprise the same material selected from the aforementioned group, such as tungsten (W). According to other embodiments of the present application, the first conductive layer CL1 and the second conductive layer CL2 can comprise different materials selected from the aforementioned group, such as the first conductive layer CL1 mainly comprises titanium (Ti) and the second conductive layer CL2 mainly comprises tungsten (W). As shown in FIG. 3, the top surface of the second alignment structure A2 and the top surface of the first interconnection structure 26 are substantially flush with each other, and the bottom surface of the second alignment structure A2 is lower than the bottom surface of the first interconnection structure 26.Figure 7 As shown, the second alignment structure A2 can be divided into a lower portion A2a filled in the first alignment trench 24A, and an upper portion A2b located outside the first alignment trench 24A, wherein the upper portion A2b has a second alignment trench 24B corresponding to the profile of the first alignment trench 24A. According to some embodiments of the present application, a cap layer 34 can be formed to conformally cover the second conductive layer CL2 and the second alignment trench 24B. The cap layer 34 can comprise a dielectric material, such as silicon oxide (SiO2).

[0054] Referring to Figure 8 and Figure 9 , a second lithography and etching process is performed to remove the upper portion A2b of the second alignment structure A2 and part of the first dielectric layer 18, exposing the lower portion A2a in the first alignment trench 24A. Specifically, the second lithography and etching process comprises forming a second photoresist layer 36 on the cap layer 34, and then using a photolithography device (such as a scanning photolithography machine or a step-by-step photolithography machine) to transfer a mark opening pattern on a photomask (not shown) to the second photoresist layer 36, forming a second mark opening 36a to expose the second alignment structure A2. Then, the exposed cap layer 34, second conductive layer CL2 and first dielectric layer 18 are etched through the second mark opening 36a using the second photoresist layer 36 as an etching mask. According to some embodiments of the present application, the second lithography and etching process is aligned to the photomask and the substrate 10 using the second alignment trench 24B of the second alignment structure A2 as an alignment mark, so that the second mark opening 36a is formed at the intended position. According to an embodiment of the present application, Figures 5 to 6 the first lithography and etching process and Figures 8 to 9 the second lithography and etching process use the same photomask. The top surface of the lower portion A2a of the second alignment structure A2 can be flush with or slightly lower than the top surface 18b of the first dielectric layer 18 exposed from the second mark opening 36a, and both are lower than the top surface 18a of the first dielectric layer 18 which is not etched and still covered by the second conductive layer CL2. According to an embodiment of the present application, a step difference S1 is included between the top surface 18a and the top surface 18b of the first dielectric layer 18.

[0055] Referring to Figure 10 and Figure 11 , the remaining second photoresist layer 36 is removed (in Figure 9After (as shown in the figure), a planarization layer 38 is formed to completely cover the circuit region R1 and the alignment mark region R2. Then, a third lithography and etching process is performed to remove the excess portion of the second conductive layer CL2, obtaining the second interconnect structure 44. Specifically, the third lithography and etching process includes first forming a third photoresist layer 42 on the planarization layer 38, then using photolithography equipment (e.g., a scanning lithography machine or a stepper lithography machine) to transfer the interconnect structure pattern on a photomask (not shown) to the third photoresist layer 42, and then using the third photoresist layer 42 as an etching mask to etch the exposed planarization layer 38, capping layer 34, and part of the second conductive layer CL2, thereby patterning the remaining second conductive layer CL2 into the second interconnect structure 44. According to some embodiments of the present invention, the third lithography and etching process uses the second alignment structure A2 (in Figure 8 The lower portion A2a (shown in the diagram) serves as an alignment mark for aligning the photomask and substrate 10. The distinct boundary contour between the lower portion A2a and the first dielectric layer 18 facilitates easier alignment of the photolithography equipment with the photomask and substrate 10, achieving better alignment accuracy and allowing the second interconnect structure 44 to be formed more accurately in the expected location. The planarization layer 38 may include a dielectric material, such as an organic polymer dielectric material. Optionally, an antireflective layer 40, such as a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer, may be disposed between the planarization layer 38 and the third photoresist layer 42.

[0056] like Figure 11 As shown, to ensure that there is no residual second conductive layer CL2 between each second interconnect structure 44, and to avoid short circuits between the second interconnect structures 44, the step of etching the second conductive layer CL2 may include over-etching the first dielectric layer 18. Therefore, the top surface 18c of the first dielectric layer 18 exposed by over-etching near the second interconnect structure 44 on the circuit region R1 will be lower than the top surface 18a of the first dielectric layer 18 covered by the second interconnect structure 44. Align the top surface 18b of the first dielectric layer 18 on the alignment mark region R2 (in Figure 9 (As shown in the diagram) it will also be over-etched to a lower top surface 18d, and top surface 18d is lower than top surface 18c. According to one embodiment of the present invention, the step difference S3 between top surface 18c and top surface 18d is greater than the step difference S2 between top surface 18a and top surface 18c. According to one embodiment of the present invention, due to the different etching selectivity of the materials, after the third lithography and etching process, the top surface of the lower part A2a of the second alignment structure A2 may be slightly higher than the top surface 18d of the first dielectric layer 18, but still lower than the top surface 18c of the first dielectric layer 18. According to one embodiment of the present invention, after the third lithography and etching process, the step difference between the top surface of the lower part A2a of the second alignment structure A2 and top surface 18d is smaller than the step difference between the top surface of the lower part A2a of the second alignment structure A2 and top surface 18c.

[0057] Please refer toFigure 11 and Figure 12 Next, the remaining third photoresist layer 42, anti-reflection layer 40, and planarization layer 38 are removed, and then a second dielectric layer 46 is formed. The second dielectric layer 46 completely covers the first dielectric layer 18, the second interconnect structure 44 (and the capping layer 34 thereon), and the lower part A2a of the second alignment structure A2, and fills the gaps between the second interconnect structures 44. Then, an etch-back process or a chemical mechanical polishing (CMP) process is performed to remove the second dielectric layer 46 and the capping layer 34 on the second interconnect structure 44 until the top surface of the second interconnect structure 44 is exposed, thereby obtaining the semiconductor device of the present invention. The second dielectric layer 46 is composed of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations thereof, but is not limited thereto. According to one embodiment of the present invention, the second dielectric layer 46 mainly comprises silicon oxide (SiO2).

[0058] like Figure 12 As shown, the semiconductor device provided by the present invention includes a substrate 10, an interlayer dielectric layer 12 disposed on the substrate 10, a first dielectric layer 18 disposed on the interlayer dielectric layer 12, a first interconnect structure 26 and an alignment structure (i.e., the lower part A2a of the second alignment structure A2) disposed in the first dielectric layer 18, a second dielectric layer 46 disposed on the first dielectric layer 18 and directly covering the top surface of the alignment structure (i.e., the lower part A2a of the second alignment structure A2), and a second interconnect structure 44 disposed in the second dielectric layer 46. The top surface of the first interconnect structure 26 is in direct contact with and electrically connected to the bottom surface of the second interconnect structure 44. The top and bottom surfaces of the alignment structure (i.e., the lower part A2a of the second alignment structure A2) are completely covered by the second dielectric layer 46 and the interlayer dielectric layer 12, respectively, and are not in direct contact or electrically connected to other circuit structures. That is to say, the alignment structure (i.e., the lower part A2a of the second alignment structure A2) is electrically floating. Specifically, the top surface of the alignment structure (i.e., the lower part A2a of the second alignment structure A2) is lower than the top surface of the first interconnect structure 26 and the bottom surface of the second interconnect structure 44, while the bottom surface of the alignment structure (i.e., the lower part A2a of the second alignment structure A2) is lower than the bottom surface of the first interconnect structure 26.

[0059] refer to Figure 12, the second interconnect structure 44 and the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) are made of the same layer of metal material (i.e., the second conductive layer CL2), have the same material, and can be the same or different material as the first interconnect structure 26 (i.e., the first conductive layer CL1).

[0060] In some embodiments, referring to Figure 12 , the second interconnect structure 44 and the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) comprise the same material, for example, selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and the like metal, or a compound, an alloy, and / or a composite layer of the aforementioned metal materials.

[0061] In some embodiments, referring to Figure 12 , the second interconnect structure 44 and the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) comprise different materials, for example, selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and the like metal, or a compound, an alloy, and / or a composite layer of the aforementioned metal materials.

[0062] In some embodiments, referring to Figure 12 , the semiconductor element further comprises an interlayer dielectric layer 12 disposed between the substrate 10 and the first dielectric layer 18, a conductive structure 14 disposed in the interlayer dielectric layer 12, and an etch stop layer 16 disposed between the interlayer dielectric layer 12 and the first dielectric layer 18. The etch stop layer 16 directly contacts a top surface of the conductive structure 14. A bottom portion of the first interconnect structure 26 penetrates the etch stop layer 16 and directly contacts the conductive structure 14.

[0063] In some embodiments, referring to Figure 12 , the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) penetrates the etch stop layer 16 and extends to an upper portion of the interlayer dielectric layer 12. A bottom surface of the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) is lower than a bottom surface of the first interconnect structure 26.

[0064] In some embodiments, referring to Figure 12 , the first dielectric layer 18 comprises a top surface 18a (first top surface) directly contacting a bottom surface of the second interconnect structure 44, a top surface 18c (second top surface) adjacent to the second interconnect structure 44 and directly contacting a bottom surface of the second dielectric layer 46, and a top surface 18d (third top surface) adjacent to the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) and directly contacting a bottom surface of the second dielectric layer 46, wherein the top surface 18d is lower than a top surface of the alignment structure (i.e., the lower portion A2a of the second alignment structure A2), the top surface of the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) is lower than the top surface 18c, and the top surface 18c is lower than the top surface 18a.

[0065] In some embodiments, referring to Figure 11 , the step difference S3 between the top surface 18c and the top surface 18d is greater than the step difference S2 between the top surface 18a and the top surface 18c.

[0066] In summary, referring to Figure 12 , the present application utilizes the alignment structure (i.e. the lower portion A2a of the second alignment structure A2) formed by the second conductive layer CL2 filled in the first alignment trench 24A (shown in Figure 10 ) as an alignment mark to pattern the second conductive layer CL2, forming the second interconnection structure 44, so that the alignment accuracy between the first interconnection structure 26 and the second interconnection structure 44 can be improved without zero layer mark.

[0067] The above descriptions are only the preferred embodiments of the present application and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of manufacturing a semiconductor element, characterized by, Comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a first interconnect structure and a first alignment structure comprised of a first conductive layer in the first dielectric layer; performing a first lithography and etching process to remove the first alignment structure and reveal a first alignment trench; forming a second conductive layer covering the first dielectric layer and the first interconnect structure and filling the first alignment trench to form a second alignment structure, wherein an upper portion of the second alignment structure located above the first alignment trench comprises a second alignment trench; performing a second lithography and etching process to remove the upper portion of the second alignment structure and etch a portion of the first dielectric layer to a predetermined depth to reveal a lower portion of the second alignment structure located in the first alignment trench; the lower portion of the second alignment structure and the first dielectric layer having a predetermined step difference, a top surface of the lower portion of the second alignment structure being lower than a top surface of the first interconnect structure; and performing a third lithography and etching process to pattern the second conductive layer into a second interconnect structure using the lower portion of the second alignment structure as an alignment mark, wherein the first interconnect structure and the second interconnect structure are in electrical contact. The step of forming the first interconnect structure and the first alignment structure comprises:

2. The method for manufacturing a semiconductor element according to claim 1, wherein forming an interconnect opening and the first alignment trench in the first dielectric layer; forming the first conductive layer covering the first dielectric layer and filling the interconnect opening and the first alignment trench; and removing the first conductive layer outside the interconnect opening and the first alignment trench to obtain the first interconnect structure located in the interconnect opening and the first alignment structure located in the first alignment trench. The first conductive layer and the second conductive layer are of the same material.

3. The method for manufacturing a semiconductor element according to claim 1, wherein The first conductive layer and the second conductive layer are of different materials.

4. The method for manufacturing a semiconductor element according to claim 1, wherein The step of the first lithography and etching process comprises:

5. The method for manufacturing a semiconductor element according to claim 1, wherein forming a first photoresist layer on the first dielectric layer; patterning the first photoresist layer to form a first mark opening and reveal the first alignment structure using the first alignment structure as an alignment mark; and etching the first alignment structure through the first mark opening. The step of the second lithography and etching process comprises:

6. The method for manufacturing a semiconductor element according to claim 1, wherein forming a second photoresist layer on the second conductive layer; patterning the second photoresist layer to form a second mark opening and reveal the upper portion of the second alignment structure using the second alignment trench as an alignment mark; and etching the upper portion of the second alignment structure and a portion of the first dielectric layer through the second mark opening. Further comprising:

7. The method for manufacturing a semiconductor element according to claim 1, wherein forming an interlayer dielectric layer and a conductive structure located in the interlayer dielectric layer on the substrate; and forming an etch stop layer on the interlayer dielectric layer and covering the conductive structure, wherein the first interconnect structure penetrates the etch stop layer and is in electrical contact with the conductive structure. The step of the third lithography and etching process comprises: forming a planarization layer on the second conductive layer and covering the lower portion of the second alignment structure; 8. The method for manufacturing a semiconductor element according to claim 1, wherein forming a third photoresist layer on the planarization layer; ​ ​ patterning the third photoresist layer using the lower portion of the second alignment structure as an alignment mark; and etching to remove portions of the planarization layer and the second conductive layer exposed from the third photoresist layer.

9. The method of manufacturing a semiconductor element according to claim 1, wherein a top surface of the first alignment structure is flush with a top surface of the first interconnect structure, and a bottom surface of the first alignment structure is lower than a bottom surface of the first interconnect structure.

10. The method of manufacturing a semiconductor element according to claim 1, wherein further comprising: forming a second dielectric layer on the first dielectric layer, covering the lower portion of the second alignment structure and filling gaps between the second interconnect structures.

11. The method of manufacturing a semiconductor element according to claim 1, wherein a top surface of the lower portion of the second alignment structure is lower than a bottom surface of the second interconnect structure.

12. A semiconductor device, characterized by comprising: a semiconductor device manufactured using the method of any one of claims 1-11, comprising: a substrate; a first dielectric layer on the substrate; first interconnect structures and alignment structures in the first dielectric layer; a second dielectric layer on the first dielectric layer and completely covering top surfaces and sidewalls of the alignment structures; and second interconnect structures in the second dielectric layer and directly contacting top surfaces of the first interconnect structures, wherein the top surfaces of the alignment structures are lower than the top surfaces of the first interconnect structures.

13. A semiconductor device, characterized by comprising: a semiconductor device manufactured using the method of any one of claims 1-11, comprising: a substrate; a first dielectric layer on the substrate; first interconnect structures and alignment structures in the first dielectric layer; a second dielectric layer on the first dielectric layer and filling gaps between the alignment structures and second interconnect structures, a bottom surface of the second dielectric layer forming a stepped contact with a top surface of the first dielectric layer; and second interconnect structures in the second dielectric layer, wherein a bottom surface of the second interconnect structures directly contacts top surfaces of the first interconnect structures, and the top surfaces of the alignment structures are lower than the bottom surfaces of the second interconnect structures.

14. The semiconductor device according to claim 12 or 13, wherein the second interconnect structures and the alignment structures are of the same material.

15. The semiconductor device according to claim 12 or 13, wherein the second interconnect structures and the alignment structures are of a material comprising tungsten.

16. The semiconductor device according to claim 12 or 13, wherein the first interconnect structures and the alignment structures are of different materials.

17. The semiconductor device according to claim 12 or 13, wherein further comprising: an interlayer dielectric layer between the substrate and the first dielectric layer; a conductive structure in the interlayer dielectric layer; and an etch stop layer between the interlayer dielectric layer and the first dielectric layer and covering the conductive structure, wherein the first interconnect structures penetrate the etch stop layer and electrically contact the conductive structure. the alignment structures penetrate the etch stop layer and portions of the interlayer dielectric layer, and a bottom surface of the alignment structures is lower than a bottom surface of the first interconnect structures.

18. The semiconductor device according to claim 17, wherein the first dielectric layer comprises:

19. The semiconductor device according to claim 12 or 13, wherein a first top surface directly contacting a bottom surface of the second interconnect structures; a second top surface adjacent to the second interconnect structures and directly contacting a bottom surface of the second dielectric layer; and a third top surface adjacent to the alignment structures and directly contacting a bottom surface of the second dielectric layer, wherein the third top surface is lower than a top surface of the alignment structures, the top surface of the alignment structures is lower than the second top surface, and the second top surface is lower than the first top surface. ​ 20. The semiconductor device according to claim 19, wherein The step difference between the second top surface and the third top surface is greater than the step difference between the first top surface and the second top surface.

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