A single event burnout resistant gallium nitride based reference vertical trench mosfet device structure and method of manufacture

Abstract

The application provides a single-event burnout-resistant gallium nitride reference vertical trench MOSFET device structure and a manufacturing method thereof, and belongs to the field of semiconductor power devices. The structure comprises a substrate layer, a buffer layer, a drain heavily doped N+ type gallium nitride layer, a low-doped N- type gallium nitride drift layer, a gate-under P type gallium nitride region, a gate-under metal, a P type base region layer, a source heavily doped N+ type gallium nitride layer, a P type base region contact metal, a gate dielectric, a passivation layer, a gate electrode, a source-drain electrode and an interconnection metal layer. The application is based on a gallium nitride reference vertical structure MOSFET device, a P type gallium nitride region is added at the bottom of a gate trench, an ohmic contact electrode is prepared to connect the P type gallium nitride region with a source electrode, an additional leakage path is provided for holes generated by single-particle incidence, the possibility of parasitic BJT opening is reduced, the anti-radiation performance of the device is improved, and therefore the device can better adapt to space environment.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor power devices and manufacturing technology, and particularly relates to a gallium nitride-based reference vertical trench MOSFET device structure resistant to single event burnout and a manufacturing method thereof. BACKGROUND

[0002] The surge in energy consumption has led to an increasing demand for efficient power electronics for power generation, transportation, and electricity use. Silicon-based devices are commonly used in traditional power electronics applications, however, wide bandgap semiconductors such as gallium nitride are more efficient, and thus, gallium nitride is more effective in future energy applications. Among many vertical device structures, gallium nitride-based reference vertical trench MOSFET is an attractive device structure, the quasi-vertical structure makes it more cost-effective and easier to integrate with other devices (such as SBD, LED, etc.), and it is very suitable for ground and space applications of high-voltage, high-power density power converters. However, gallium nitride power MOSFETs can suffer catastrophic failure when subjected to heavy ion radiation, such as single event gate rupture (SEGR) or single event burnout (SEB). The occurrence of SEB depends on the opening of the parasitic BJT in the MOSFET device structure, which is opened by the short transient current generated by the movement of electron-hole pairs generated by heavy ion incidence under source-drain bias. Due to the regenerative feedback mechanism, the collector current in the BJT increases to the point where the second breakdown begins, creating a permanent short circuit between the source and the drain, rendering the MOSFET ineffective. SUMMARY

[0003] In order to overcome the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a gallium nitride-based reference vertical trench MOSFET device structure resistant to single event burnout and a manufacturing method thereof, which introduces an additional hole leakage path to enhance the single event burnout resistance of the gallium nitride-based reference vertical trench MOSFET device structure.

[0004] In order to achieve the above-mentioned purpose, the technical solution adopted by the present application is:

[0005] A single event burnout resistant gallium nitride based reference vertical trench MOSFET device structure, comprising a substrate layer, a composite buffer layer, a drain heavily doped N+ gallium nitride layer, a low doped N- gallium nitride drift layer, a P-type base region layer and a source heavily doped N+ gallium nitride layer arranged in sequence, a drain electrode is arranged on a side of the drain heavily doped N+ gallium nitride layer away from the composite buffer layer, a gate under P-type gallium nitride region corresponding to a gate trench is arranged on a side of the low doped N- gallium nitride drift layer away from the drain heavily doped N+ gallium nitride layer, a gate under metal is arranged at a bottom of the gate trench, and a gate dielectric is arranged on a wall of the gate trench or on the wall and the bottom of the gate trench; a P-type base region contact metal is arranged in the source heavily doped N+ gallium nitride layer and contacts the P-type base region layer, a gate electrode is arranged on the gate dielectric, and the P-type base region contact metal and the source heavily doped N+ gallium nitride layer both contact a source electrode, and the source electrode and the gate under metal are interconnected by an interconnection metal layer.

[0006] In one embodiment, the low doped N- gallium nitride drift layer is arranged in the middle of the drain heavily doped N+ gallium nitride layer, and two drain electrodes are symmetrically arranged on two sides of the low doped N- gallium nitride drift layer; the gate under P-type gallium nitride region is arranged in the middle of the low doped N- gallium nitride drift layer, the gate under metal is arranged in the middle of the gate trench, and the gate dielectric, the P-type base region layer and the source heavily doped N+ gallium nitride layer are symmetrically arranged about the gate under metal; the source heavily doped N+ gallium nitride layer on two sides of the gate trench is respectively arranged with one P-type base region contact metal.

[0007] In one embodiment, the gate trench has a depth of 600 nm-1 um; a P-type base region recess is opened on the source heavily doped N+ gallium nitride layer, the P-type base region contact metal is arranged in the P-type base region recess, and the P-type base region recess has a depth of 200 nm-500 nm; the source heavily doped N+ gallium nitride layer, the P-type base region layer and the low doped N- gallium nitride drift layer form a step structure with the drain heavily doped N+ gallium nitride layer, the drain electrode is arranged on a step surface of the step structure, and the total thickness of the source heavily doped N+ gallium nitride layer, the P-type base region layer and the low doped N- gallium nitride drift layer, i.e. the height of the step structure, is 1.5 um-15 um.

[0008] In one embodiment, the substrate layer is made of SiC or Si or sapphire and has a thickness of 100-1500 um; the composite buffer layer comprises a nucleation layer, a transition layer and a composite buffer layer; the nucleation layer is made of AlN and has a thickness of 50-300 nm; the transition layer is made of AlGaN with varying Al composition or AlGaN / GaN superlattice and has a thickness of 100 nm-1 um; and the buffer layer is made of GaN or AlGaN and has a thickness of 100 nm-10 um.

[0009] In one embodiment, the drain-heavily doped N+ type gallium nitride layer is made of heavily doped N-type GaN with a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The thickness is 100-600nm;

[0010] The lightly doped N-type gallium nitride drift layer is made of lightly doped N-type GaN with a doping concentration of 1×10⁻⁶. 15 -5×10 16 cm -3 The thickness is 1-20μm;

[0011] The material of the under-gate P-type gallium nitride region is heavily doped P-type GaN with a doping concentration of 5 × 10⁻⁶. 18 -5×10 19 cm -3 The thickness is 200-600nm;

[0012] The P-type base layer is made of heavily doped P-type GaN with a doping concentration of 5 × 10⁻⁶. 18 -5×10 19 cm -3 The thickness is 0.3-1μm;

[0013] The source-doped N+ type gallium nitride layer is made of heavily doped N-type GaN with a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The thickness is 300-600nm.

[0014] In one embodiment, the under-gate metal is disposed on the surface of the under-gate P-type gallium nitride region or embedded in the under-gate P-type gallium nitride region to form an ohmic contact; the gate dielectric is disposed on the surface of the under-gate P-type gallium nitride region and extends along the gate trench sidewall to the source heavily doped N+ type gallium nitride layer; the gate electrode, the gate dielectric, and the gate trench sidewall form a MOS structure; the source electrode and the source heavily doped N+ type gallium nitride layer form an ohmic contact; the drain electrode and the drain heavily doped N+ type gallium nitride layer form an ohmic contact; and the P-type base region contact metal and the P-type base region layer form an ohmic contact.

[0015] In one embodiment, the under-gate P-type gallium nitride region is formed by ion implantation and diffusion, and the gate dielectric is a SiO2 or Al2O3 insulating layer formed by deposition.

[0016] In one embodiment, passivation layers are uniformly distributed between the interconnect metal layer and the heavily doped N+ gallium nitride layer at the source, and between the interconnect metal layer and the gate electrode.

[0017] The application further provides a manufacturing method of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure.

[0018] S1: sequentially growing a composite buffer layer, a drain heavily doped N+ gallium nitride layer and a low-doped N- gallium nitride drift layer on a substrate layer;

[0019] S2: forming a gate-under P-type gallium nitride region by ion implantation and diffusion on a side of the low-doped N- gallium nitride drift layer away from the drain heavily doped N+ gallium nitride layer;

[0020] S3: after the gate-under P-type gallium nitride region is formed, continuing to grow a P-type base region layer and a source heavily doped N+ gallium nitride layer in the growth order of S1;

[0021] S4: etching a P-base recess in the source heavily doped N+ gallium nitride layer, etching a gate trench in the source heavily doped N+ gallium nitride layer and the P-type base region layer, and etching a step structure in the source heavily doped N+ gallium nitride layer, the P-type base region layer and the low-doped N- gallium nitride drift layer;

[0022] S5: preparing a P-type base region contact metal on the P-base recess;

[0023] S6: preparing a drain electrode on a step surface of the step structure, i.e. on the drain heavily doped N+ gallium nitride layer, to form an ohmic contact, and preparing a source electrode on the source heavily doped N+ gallium nitride layer and the P-type base region contact metal to form an ohmic contact;

[0024] S7: depositing a gate dielectric layer in the gate trench;

[0025] S8: preparing a gate electrode covering the gate dielectric layer;

[0026] S9: opening a hole at a position where the gate dielectric layer contacts the gate-under P-type gallium nitride region to prepare a gate-under metal to form an ohmic contact;

[0027] S10: connecting the source electrode and the gate-under metal by using an interconnection metal layer.

[0028] In one embodiment, S2 is performed by magnesium ion implantation and diffusion; and between S9 and S10, a passivation layer is first deposited on a surface of the device, then holes are opened at the source electrode and the gate-under metal, and an interconnection is formed by using the interconnection metal layer.

[0029] Compared with the prior art, the application has the following beneficial effects:

[0030] 1. The anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by the application introduces a gate-under P-type gallium nitride region under the gate on the basis of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure, provides an additional leakage path for the holes generated after the heavy ion incidence, and realizes the improvement of the anti-single-particle burnout performance.

[0031] 2. The anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by the application maintains the structure of the basic quasi-vertical trench MOSFET, and the introduced gate-under P-type gallium nitride region can also relieve the crowded electric field near the trench, thus improving the breakdown voltage and avoiding the damage of the original characteristics of the device caused by the new structure.

[0032] 3. Compared with the existing anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure, the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by the application only increases ion implantation and diffusion processes, and effectively improves the anti-single-particle burnout capability of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure and improves the product performance under the condition of limited increase in process difficulty and manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a schematic diagram of the existing anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure.

[0034] Figure 2 is a schematic diagram of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by the application.

[0035] Figure 3 is a schematic diagram of the manufacturing method of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by the application.

[0036] Fig. 4 is a process schematic diagram of the manufacturing method of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by the application.

[0037] BRIEF DESCRIPTION OF DRAWINGS

[0038] In the figure: 1 - substrate layer; 2 - composite buffer layer; 3 - drain heavily doped N+ type gallium nitride layer; 4 - low-doped N- type gallium nitride drift layer; 5 - gate-under P-type gallium nitride region; 6 - gate-under metal; 7 - P-type base region layer; 8 - source heavily doped N+ type gallium nitride layer; 9 - P-type base region contact metal; 10 - source electrode; 11 - gate dielectric; 12 - gate electrode; 13 - passivation layer; 14 - drain electrode; 15 - interconnection metal layer. DETAILED DESCRIPTION

[0039] The embodiments of the application will be described in detail below with reference to the accompanying drawings and examples.

[0040] Figure 1 As shown in the prior anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure, it can be seen that the source electrode 10 and the gate electrode 12 are both located on the device step structure (the source electrode 10 is located above the uppermost source heavily doped N+ type gallium nitride layer 8, and the gate electrode 12 is made above the gate dielectric 11 in the gate trench), and the drain electrode 14 of the device is located on the drain heavily doped N+ type gallium nitride layer below the device step structure.

[0041] The main body of the present application is the structure design of the device cell area, and the epitaxial growth, ion implantation, diffusion and other processes of the device are understood by those skilled in the art, so the present application is not described.

[0042] For the convenience of description, in the present application, the substrate layer 1 is "below", and the growth direction is "above". This orientation does not form a limitation on the present application. For example, the substrate layer 1 can also be considered as "above", and other layers are "below" it, or the substrate layer 1 can be considered as "left", and other layers are "right" to it.

[0043] The anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure manufacturing method provided by the present application will be further described in detail below in combination with the drawings and examples.

[0044] The present application provides an anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure and a manufacturing method thereof. On the basis of the prior anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure, a P-type gallium nitride structure is added below the gate to provide an additional leakage path for the holes generated by the heavy ion incidence, thereby effectively improving the anti-single-particle burnout performance of the anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure.

[0045] Example 1

[0046] Please refer to Figure 2 , Figure 2 is a structure schematic diagram of an anti-single-particle burnout gallium nitride reference vertical trench MOSFET device structure provided by an embodiment of the present application. According to the above-mentioned limitation that the substrate layer 1 is "below" and the growth direction is "above", the gallium nitride transistor provided by the present embodiment comprises, from bottom to top, a substrate layer 1, a composite buffer layer 2, a drain heavily doped N+ type gallium nitride layer 3, a low-doped N- type gallium nitride drift layer 4, a P-type base layer 7 and a source heavily doped N+ type gallium nitride layer 8.

[0047] The drain electrode 14 is arranged on the upper surface of the drain heavily doped N+ type gallium nitride layer 3 and located on both sides of the low-doped N- type gallium nitride drift layer 4.

[0048] The present application is provided with a gate-under P-type gallium nitride region 5 in the upper part of the low-doped N-type gallium nitride drift layer 4, which is located directly under the gate trench. The bottom of the gate trench is provided with a gate-under metal 6, and the sidewall of the gate trench is provided with a gate dielectric 11.

[0049] The P-type base region contact metal 9 is provided in the source heavily-doped N+type gallium nitride layer 8, and is in contact with the P-type base region layer 7.

[0050] The gate electrode 12 is provided on the gate dielectric 11, the source electrode 10 is in contact with the P-type base region contact metal 9 and the source heavily-doped N+type gallium nitride layer 8, and the source electrode 10 is connected to the gate-under metal 6 through an interconnection metal layer 15.

[0051] According to the structure of the present embodiment, by adding the gate-under P-type gallium nitride region 5 at the bottom of the gate trench, preparing the gate-under metal 6 and forming an ohmic contact, and connecting the source electrode 10 through the interconnection metal layer 15, an additional leakage path is provided for the holes generated by the single particle incidence, thereby reducing the possibility of the opening of the parasitic BJT and improving the radiation resistance of the device, which can make the device better adapt to the high radiation environment such as spaceflight.

[0052] Specifically, the gallium nitride of the gate electrode 12, the gate dielectric 11 and the gate-under P-type gallium nitride region 5 forms a MOS structure, and when a positive voltage is applied to the gate electrode 12 to a certain extent, an inversion layer is formed at the MOS interface (near the side wall of the recess on the P-GaN side). When the source is grounded and the drain is positively biased, the electrons can pass through the uppermost source heavily-doped N+type gallium nitride layer 8, the inversion channel of the P-type base region layer 7 and the low-doped N-type gallium nitride drift layer 4 in turn, and finally be collected by the drain electrode 14 through the drain heavily-doped N+type gallium nitride layer 3. When a heavy ion is incident on the gallium nitride-based vertical structure MOSFET device, many electron-hole pairs will be generated along the incident path. The electrons are absorbed by the drain through the drift region and the heavily-doped N+type gallium nitride, while the holes are absorbed by the source through the drift region, the P-type base region and the P-type base region contact metal. The mobility of the holes is smaller than that of the electrons, so if the holes cannot be quickly absorbed by the source, they may cause the parasitic BJT and impact ionization to interact and trigger avalanche multiplication under a high drain bias, resulting in continuous bipolar action and continuously increasing current, thereby causing SEB. The device of the present application adds the gate-under P-type gallium nitride region 5 to the basic structure, prepares the gate-under metal 6 and forms an ohmic contact, and connects the source electrode 10 and the P-type base region contact metal 9 through the interconnection metal, thereby providing an additional leakage path for the holes generated by the heavy ion incidence, reducing the possibility of the opening of the parasitic BJT, and improving the radiation resistance of the gallium nitride MOSFET device.

[0053] In some embodiments of the present invention, the source heavily doped N+ type gallium nitride layer 8, the P-type base layer 7, and the lightly doped N- type gallium nitride drift layer 4 form a single-step structure with the drain heavily doped N+ type gallium nitride layer 3. The drain electrode 14 is arranged on the step surface, i.e., the bottom surface, of the step structure, that is, the source electrode 10 and the drain electrode 14 are respectively located above and below the step structure. The lightly doped N- type gallium nitride drift layer 4 is located in the middle of the drain heavily doped N+ type gallium nitride layer 3, while the two drain electrodes 14 are symmetrically arranged on both sides of the lightly doped N- type gallium nitride drift layer 4. For example, the height of this step structure, i.e., the total thickness of the source heavily doped N+ type gallium nitride layer 8, the P-type base layer 7, and the lightly doped N- type gallium nitride drift layer 4, is 1.5 μm-15 μm. In embodiments of the present invention, it is further preferably 4.1 μm, and the bottom of the step structure is the drain heavily doped N+ type gallium nitride 3. This embodiment can better balance the on-resistance and breakdown voltage of the device, and avoid premature breakdown of the device.

[0054] In some embodiments of the present invention, the under-gate P-type gallium nitride region 5 is disposed in the middle of the lightly doped N-type gallium nitride drift layer 4, and the under-gate metal 6 is disposed in the middle of the gate trench, for example, the depth of which is 600 nm-1 μm. The gate dielectric 11, the P-type base layer 7, and the source heavily doped N+ type gallium nitride layer 8 are all symmetrically arranged about the under-gate metal 6, and the gate electrode 12 covers the gate trench (above the gate dielectric 11). This embodiment not only provides additional leakage paths for holes but also improves the electric field distribution near the gate, further enhancing the radiation resistance of the device.

[0055] In some embodiments of the present invention, a P-type base region contact metal 9 is disposed on each of the heavily doped N+ type gallium nitride layers 8 on both sides of the gate trench. Specifically, a P-type base region trench is formed on the heavily doped N+ type gallium nitride layer 8, and the P-type base region contact metal 9 is disposed in the P-type base region trench, covering the P-type base region trench. The depth of the P-type base region trench is 200nm-500nm.

[0056] In some embodiments of the present invention, the under-gate metal 6 is disposed on the surface of the under-gate P-type gallium nitride region 5 or embedded in the under-gate P-type gallium nitride region 5 to form an ohmic contact; the gate dielectric 11 is disposed on the surface of the under-gate P-type gallium nitride region 5 and extends along the gate trench sidewall to the source heavily doped N+ type gallium nitride layer 8; the gate electrode 12, the gate dielectric 11, and the gate trench sidewall form a MOS structure; the source electrode 10 forms an ohmic contact with the source heavily doped N+ type gallium nitride layer 8; the drain electrode 14 forms an ohmic contact with the drain heavily doped N+ type gallium nitride layer 3; and the P-type base contact metal 9 forms an ohmic contact with the P-type base layer 7.

[0057] In some embodiments of the present application, the P-type gallium nitride region 5 under the gate is formed by ion implantation and diffusion, and the gate dielectric 11 is an insulating layer of SiO2 or Al2O3 formed by deposition.

[0058] In some embodiments of the present application, a passivation layer 13 is provided between the interconnection metal layer 15 and the source heavily doped N+ gallium nitride layer 8, and between the interconnection metal layer 15 and the gate electrode 12.

[0059] In some embodiments of the present application, the materials are selected as follows:

[0060] The substrate layer 1 is made of SiC or Si or sapphire, and has a thickness of 100-1500 μm; further, it is made of Si and has a thickness of 675 μm.

[0061] The composite buffer layer 2 includes a nucleation layer, a transition layer and a composite buffer layer; the nucleation layer is made of AlN and has a thickness of 50-300 nm, further, it is made of AlN and has a thickness of 200 nm; the transition layer is made of AlGaN with varying Al composition, or AlGaN / GaN superlattice, and has a thickness of 100 nm-1 μm, further, it is made of AlGaN with varying Al composition and has a thickness of 750 nm; the buffer layer is made of GaN or AlGaN, and has a thickness of 100 nm-10 μm, further, it is made of GaN and has a thickness of 1 μm. The nucleation layer, the transition layer and the buffer layer are all unintentionally doped.

[0062] The material of the drain heavily doped N+ gallium nitride 3 is heavily doped N-type GaN, and has a doping concentration of 1x10 18 -5x10 18 cm -3 , and a thickness of 100-600 nm. Further, the doping concentration is 2x10 18 cm -3 , and the thickness is 200 nm.

[0063] The material of the low-doped N- gallium nitride drift layer 4 is lightly doped N-type GaN, and has a doping concentration of 1x10 15 -5x10 16 cm -3 , and a thickness of 1-20 μm. Further, the doping concentration is 2x10 18 cm -3 , and the thickness is 3.5 μm.

[0064] The material of the P-type gallium nitride region 5 under the gate is heavily doped P-type GaN, and has a doping concentration of 5x10 18 -5x10 19 cm -3 , and a thickness of 200-600 nm. Further, the doping concentration is 2x10 19 cm -3The thickness is 300nm.

[0065] The material of the P-type base layer 7 is heavily doped P-type GaN with a doping concentration of 5 × 10⁻⁶. 18 -5×10 19 cm -3 The thickness is 0.3-1 μm. Further selection was made with a doping concentration of 2 × 10⁻⁶. 19 cm -3 The thickness is 400nm.

[0066] The source-doped N+ type gallium nitride 8 material is heavily doped N-type GaN with a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The thickness is 300-600 nm. Further selection was made with a doping concentration of 1×10⁻⁶. 18 cm -3 The thickness is 500nm.

[0067] The first layer below the material of gate electrode 12 is Ti, Ni, Al, Ta, TiN, or TaN. The bottom two layers of the material for source electrode 10 and drain electrode 14 are Ti / Al, Ta / Al, or Mo / Al. The bottom layer of the material for P-type base contact metal 9 and under-gate metal 6 is Ni, Cr, or Pt. The first layer below the material of interconnect metal 15 is Ti or Al.

[0068] Further selection: the gate electrode 12 is made of Ni / Au from bottom to top, with a thickness of 50 / 300 nm. The source electrode 10 and drain electrode 14 are made of Ti / Al / Ni / Au from bottom to top, with a thickness of 20 / 120 / 40 / 50 nm. The P-type base contact metal 9 and the under-gate metal 6 are made of Ni / Au from bottom to top, with a thickness of 20 / 20 nm. The interconnect metal 15 is made of Ti / Au from bottom to top, with a thickness of 20 / 150 nm. The metal layer selection in this embodiment is based on the best real-world data obtained from experiments, which can maximize the optimization of device performance and reduce the ohmic resistance of its electrodes.

[0069] Example 2

[0070] Based on Embodiment 1 above, this embodiment provides a method for manufacturing a gallium nitride-based vertical trench MOSFET device structure resistant to single-event burn-out. Please refer to... Figure 3 and Figures 4a to 4o , Figure 3 This is a schematic diagram of a method for manufacturing a gallium nitride reference vertical trench MOSFET device structure resistant to single-particle burn-out, provided by an embodiment of the present invention. Figures 4a to 4oA process schematic diagram of a method for manufacturing a single-event burnout resistant gallium nitride reference vertical trench MOSFET device structure is provided for an embodiment of the present application. The specific preparation process is as follows:

[0071] S1: substrate cleaning: hydrogen is introduced into the reaction chamber at a high temperature of about 1000℃ to remove the contaminants on the surface of the Si substrate. Although this step is not necessary, it is still recommended to use this step.

[0072] S2: using the cleaned substrate as the substrate layer 1, a composite buffer layer 2, a heavily doped N+ type gallium nitride layer 3 for the drain and a low-doped N- type gallium nitride drift layer 4 are sequentially grown on the substrate layer 1. Specifically, when the composite buffer layer 2 includes a nucleation layer, a transition layer and a buffer layer, the composite buffer layer 2 is sequentially grown into a nucleation layer, a transition layer and a buffer layer. As shown in Figure 4a 、 4b , 4c, 4d.

[0073] Specifically, using MOCVD (Metal-organic Chemical Vapor Deposition) equipment and technology, a nucleation layer, a transition layer, a buffer layer, a heavily doped N+ type gallium nitride layer 3 for the drain and a low-doped N- type gallium nitride drift layer 4 are sequentially grown on the substrate.

[0074] S3: on the upper part of the low-doped N- type gallium nitride drift layer 4, a P-type gallium nitride region 5 under the gate is formed by ion implantation and diffusion, as shown in Figure 4e .

[0075] Specifically, first, a layer of SiO2 is deposited, a lithography process is used to make an etching window pattern, then RIE equipment (reactive ion etching machine) is used for SiO2 etching to form a SiO2 mask, magnesium ion implantation is performed in the area not covered by SiO2, and activation annealing is performed to form the P-type gallium nitride region 5 under the gate. Finally, the SiO2 mask is removed with HF or BOE.

[0076] S4: after the P-type gallium nitride region 5 under the gate is formed, a P-type base region layer 7 and a heavily doped N+ type gallium nitride layer 8 for the source are sequentially grown, as shown in Figure 4f 、 4g .

[0077] Specifically, using MOCVD (Metal-organic Chemical Vapor Deposition) equipment and technology, a P-type base region layer 7 and a heavily doped N+ type gallium nitride layer 8 for the source are sequentially grown on the existing epitaxial structure.

[0078] S5: etching out the gate trench, P-base recess and step structure in sequence, as shown in Figure 4h

[0079] Specifically, a lithography process is adopted to make the etching window pattern, then ICP equipment (inductively coupled plasma etching machine) is used for gallium nitride etching, and after etching, the device is soaked in 25% TMAH solution (temperature 85℃) for half an hour to repair the etching damage.

[0080] In the present application, the source heavily doped N+ gallium nitride layer 8 is etched to expose the P-type base layer 7 to form a P-base recess. The source heavily doped N+ gallium nitride layer 8 and the P-type base layer 7 are etched to expose the P-type gallium nitride region 5 under the gate to form a gate trench. The source heavily doped N+ gallium nitride layer 8, the P-type base layer 7 and the low-doped N- gallium nitride drift layer 4 are etched to expose the drain heavily doped N+ gallium nitride layer 3 to form a step structure.

[0081] S6: P-type base contact metal 9 is prepared on the exposed surface of the P-type base layer 7 in the P-base recess, as shown in Figure 4i

[0082] Specifically, a lithography process is adopted to make the P-type base contact metal 9 pattern, then electron beam evaporation technology is used to prepare the P-type base contact metal 9, the metal is Ni / Au 20 / 20nm, and after metal deposition and stripping, the device is annealed by rapid annealing (annealing temperature is 500℃, time is 30s).

[0083] S7: The drain electrode 14 is prepared on the step surface of the step structure, i.e. the drain heavily doped N+ gallium nitride layer 3, to form ohmic contact, i.e. the drain electrode 14 is made above the drain heavily doped N+ gallium nitride layer 3 of the etched step structure. The source electrode 10 is prepared on the source heavily doped N+ gallium nitride layer 8 and the P-type base contact metal 9 to form ohmic contact, i.e. the source electrode 10 is located above the source heavily doped N+ gallium nitride layer 8 which is the uppermost layer of the epitaxial structure, as shown in Figure 4j

[0084] Specifically, a lithography process is adopted to make the source electrode pattern and the drain electrode pattern, then electron beam evaporation technology is used to prepare the source electrode and the drain electrode, the metal is Ti / Al / Ni / Au 20 / 120 / 40 / 50nm, and after metal deposition and stripping, the device is annealed by rapid annealing (annealing temperature is 400℃, time is 30s).

[0085] S8: A layer of gate dielectric 11 is deposited above the gate trench, as shown in Figure 4k

[0086] ​​​​Specifically, the material of the gate dielectric 11 is SiO2 or Al2O3, and the thickness is 100 nm. After the deposition is completed, a photolithography process is used to form a shielding mask, and the wet etching is used to remove the excess gate dielectric 11, and only the part above the gate trench is left.

[0087] S9: The gate electrode 12 is prepared on the gate dielectric 11, as shown in FIG. 4. Figure 4l

[0088] Specifically, the gate electrode pattern is made by using the photolithography process, and then the gate electrode 12 is prepared by using the magnetron sputtering technology, the metal is Ni / Au 50 / 300 nm, and after the sputtering is completed, the device is annealed by using the rapid annealing method (the annealing temperature is 400°C, and the time is 10 min).

[0089] S10: The gate-down metal 6 is prepared by opening holes at the contact between the gate dielectric 11 and the gate-down P-type gallium nitride region 5, and the ohmic contact is formed, as shown in FIG. 5. Figure 4m

[0090] Specifically, the ohmic contact electrode pattern of the gate-down P-type gallium nitride region is made by using the photolithography process, and then the ohmic contact electrode of the gate-down P-type gallium nitride region is prepared by using the electron beam evaporation technology, the metal is Ni / Au 20 / 20 nm, and after the metal deposition and stripping, the device is annealed by using the rapid annealing method (the annealing temperature is 500°C, and the time is 30 s).

[0091] S11: A passivation layer 13 is deposited on the surface of the device, as shown in FIG. 6. Figure 4n

[0092] Although this step is not necessary, it is still recommended to perform the step. Specifically, the material of the passivation layer 13 is SiN x , and the thickness is 200 nm.

[0093] S12: The interconnection metal layer 15 is formed by opening holes above the source electrode 10 and the gate-down metal 6, as shown in FIG. 7. Figure 4o

[0094] Specifically, the window of the passivation opening is formed by using the photolithography process, the passivation layer 13 above the source electrode, the drain electrode 14 and the gate-down metal 6 is removed by using the wet etching, and then the interconnection metal pattern is made by using the photolithography process again, and then the interconnection metal layer 15 is prepared by using the vacuum evaporation technology, the metal is Ti / Au 20 / 100 nm, and then the metal stripping is performed in the acetone solution.

[0095] Thus, the preparation of the anti-single-particle burnout gallium nitride-based reference vertical trench MOSFET device structure is completed. The manufacturing process of the anti-single-particle burnout gallium nitride-based reference vertical trench MOSFET device structure of the embodiment is simple and easy to control, and is compatible with the traditional semiconductor process.​​​​

[0096] The above description is made in connection with the preferred embodiment of the application, and is not intended to limit the specific implementation of the application to these descriptions. For those skilled in the art, without departing from the concept of the application, some simple deductions or replacements can be made, which should be considered as falling within the protection scope of the application.

Claims

1. A single event burnout resistant gallium nitride based reference vertical trench MOSFET device structure comprising, in order, a substrate layer (1), a composite buffer layer (2), a drain heavily doped N + type gallium nitride layer (3), a low doped N - type gallium nitride drift layer (4), a P type base layer (7) and a source heavily doped N + type gallium nitride layer (8), a drain electrode (14) being arranged on the side of the drain heavily doped N + type gallium nitride layer (3) facing away from the composite buffer layer (2), characterized in that In the low-doped N - Gallium nitride drift layer (4) away from the drain heavily doped N + Type gallium nitride layer (3) of one side, with the gate trench corresponding to the gate P type gallium nitride area (5) is arranged, the slot bottom of the gate trench is provided with the gate metal (6), the gate metal (6) is arranged on the surface of the gate P type gallium nitride area (5) or embedded in the gate P type gallium nitride area (5) forms ohmic contact, the slot wall is provided with gate dielectric (11);The source heavily doped N + Type gallium nitride layer (8) is provided with P type base contact metal (9) in contact with the P type base layer (7), the gate dielectric (11) is provided with gate electrode (12), the P type base contact metal (9) and the source heavily doped N + Type gallium nitride layer (8) is in contact with the source electrode (10), and the source electrode (10) is interconnected with the gate metal (6) through an interconnection metal layer (15).

2. The single event burnout resistant gallium nitride based reference vertical trench MOSFET device structure of claim 1, wherein, The low-doped N - Gallium nitride drift layer (4) of type N- is arranged in the middle of the heavily doped N + Gallium nitride layer (3) of type P- is arranged on both sides of the low-doped N - Gallium nitride drift layer (4) of type N-; the gate-under P-type gallium nitride region (5) is arranged in the middle of the low-doped N - Gallium nitride drift layer (4) of type N-; the gate-under metal (6) is arranged in the middle of the gate trench; the gate dielectric (11), the P-type base region layer (7) and the heavily doped N + Gallium nitride layer (8) of type N+ are symmetrically arranged with respect to the gate-under metal (6); the heavily doped N + Gallium nitride layer (8) of type N+ is arranged with one P-type base region contact metal (9) respectively.

3. The single event burnout resistant gallium nitride based reference vertical trench MOSFET device structure according to claim 1 or 2, characterized in that The gate trench depth is 600 nm-1 µm; the source heavily doped N + The P-type base region contact metal (9) is arranged in the P-type base region recess, and the depth of the P-type base region recess is 200 nm-500 nm; the source heavily doped N + The P-type base region layer (7) and the low-doped N - The P-type base region layer (7) and the low-doped N + The P-type base region layer (7) and the low-doped N + The P-type base region layer (7) and the low-doped N - The total thickness of the P-type base region layer (7) and the low-doped N 4. The single event burnout resistant gallium nitride based reference vertical trench MOSFET device structure of claim 1, wherein, The substrate layer (1) is made of SiC or Si or sapphire, and has a thickness of 100-1500 µm; the composite buffer layer (2) comprises a nucleation layer, a transition layer and a buffer layer; the nucleation layer is made of AlN and has a thickness of 50-300 nm; the transition layer is made of AlGaN with varying Al component or AlGaN / GaN superlattice and has a thickness of 100 nm-1 µm; the buffer layer is made of GaN or AlGaN and has a thickness of 100 nm-10 µm.

5. The GaN-based reference vertical trench MOSFET device structure against single event burn-out according to claim 1, wherein, The drain is heavily doped N + The material of the gallium nitride layer (3) is heavily doped N-type GaN, with a doping concentration of 1 x 10 18 -5 x 10 18 cm -3 -3 cm-2, and a thickness of 100-600 nm. The low-doped N - The material of the gallium nitride drift layer (4) is lightly doped N-type GaN with a doping concentration of 1 x 10 15 -5 x 10 16 cm -3 -3 cm-3, and a thickness of 1-20 pm. The material of the P-type gallium nitride region (5) under the gate is heavily doped P-type GaN, with a doping concentration of 5x1018cm-3 and a thickness of 200-600 nm. 18 -5x1018cm-3 19 cm -3 , and a thickness of 200-600 nm. The material of the P-type base region layer (7) is heavily doped P-type GaN with a doping concentration of 5x1018cm-3 and a thickness of 0.3-1 pm. 18 -5x1018cm-3 19 cm -3 -1x1018cm-3 -5x1018cm-3 -1x1018cm-3 The source is heavily doped N + The material of the GaN layer (8) is heavily doped N-type GaN with a doping concentration of 1 x 10 18 -5 x 10 18 cm -3 -3 and a thickness of 300-600 nm.

6. The GaN-based reference vertical trench MOSFET device structure against single event burn-out according to claim 1, wherein, The gate dielectric (11) is arranged on the surface of the P-gallium nitride region (5) under the gate and extends along the side wall of the gate trench to the source heavily doped N + gallium nitride layer (8), the gate electrode (12) and the gate dielectric (11) and the side wall of the gate trench form a MOS structure; the source electrode (10) and the source heavily doped N + gallium nitride layer (8) form an ohmic contact; the drain electrode (14) and the drain heavily doped N + gallium nitride layer (3) form an ohmic contact; the P-type base region contact metal (9) and the P-type base region layer (7) form an ohmic contact.

7. The GaN-based reference vertical trench MOSFET device structure against single event burn-out according to claim 1, wherein, The gate dielectric (11) is an insulating layer of SiO2 or Al2O3 formed by deposition.

8. The GaN-based reference vertical trench MOSFET device structure against single event burn-out according to claim 1, wherein, The interconnection metal layer (15) is heavily doped with N + A passivation layer (13) is arranged between the interconnection metal layer (15) and the source electrode heavily doped with N 9. A method of fabricating a single event burnout immune GaN-based reference vertical trench MOSFET device structure as defined in claim 1, wherein, The method comprises the following steps: S1: on the substrate layer (1), a composite buffer layer (2), a drain heavily doped N + type gallium nitride layer (3) and a low-doped N - type gallium nitride drift layer (4) are sequentially grown S2: In the low-doped N - The P-type gallium nitride layer (3) is formed on the gallium nitride drift layer (4) far from the drain. + The P-type gallium nitride region (5) under the gate is formed by ion implantation and diffusion on one side of the P-type gallium nitride layer (3). S3: after the formation of the P-gallium nitride region (5) under the gate, continue to grow the P-base region layer (7) and the source heavily doped N + gallium nitride layer (8) in the growth order of S1. S4: heavily dope N to source + etching out P-base recess in the N-type GaN layer (8) and heavily dope N to source + etching out gate trench in the N-type GaN layer (8) and P-type base layer (7) and heavily dope N to source + etching out step structure in the N-type GaN layer (8), P-type base layer (7) and low-doped N - etching out step structure in the N-type GaN drift layer (4) S5: preparing a P-type base region contact metal (9) on the P-type base region recess; S6: on the step surface of the step structure, i.e. the heavily doped N + type gallium nitride layer (3), a drain electrode (14) is prepared to form an ohmic contact; on the heavily doped N + type gallium nitride layer (8) and the P type base region contact metal (9), a source electrode (10) is prepared to form an ohmic contact; S7: depositing a gate dielectric (11) on the gate trench; S8: preparing a gate electrode (12) covering the gate dielectric (11); S9: opening a hole at the contact position of the gate dielectric (11) and the P-type gallium nitride region (5) under the gate to prepare a metal under the gate (6) to form an ohmic contact; S10: connecting the source electrode (10) and the metal under the gate (6) by using an interconnection metal layer (15).

10. The method of fabricating a single event burnout immune GaN-based vertical trench MOSFET device structure as recited in claim 9, wherein, In the S2, the P-type gallium nitride region (5) under the gate is formed by magnesium ion implantation and diffusion; between the S9 and S10, a passivation layer (13) is first deposited on the surface of the device, then a hole is opened at the source electrode (10) and the metal under the gate (6), and the interconnection is formed by using the interconnection metal layer (15).

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