Peak current control circuit for a dc-dc converter

Abstract

Embodiments of the present disclosure provide a peak current control circuit for a DC-DC converter, which includes a voltage control circuit, a first voltage-controlled current generation circuit, a second voltage-controlled current generation circuit, a comparison voltage generation circuit, and a voltage comparator. The voltage control circuit provides a comparison current to the comparison voltage generation circuit via a first node, and controls a voltage of a second node according to a peak reference voltage. The first voltage-controlled current generation circuit generates a first current according to an input voltage and an output voltage. The second voltage-controlled current generation circuit limits a sum of the first current and the comparison current according to the voltage of the second node. The comparison voltage generation circuit generates a comparison voltage at the first node according to the comparison current. A first input terminal of the voltage comparator is coupled to the first node. A second input terminal of the voltage comparator is coupled to a first pole of a power tube and an inductor. The power tube is turned off when an inductor current peak value indication signal output from an output terminal of the voltage comparator flips to a valid level.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a peak current control circuit for a DC-DC converter. Background Technology

[0002] DC-DC converters (or DC-DC voltage converters) are widely used in various chip power supply applications. To prevent excessive current from burning out the chip due to abnormal conditions, the inductor current of the DC-DC converter needs to be limited. Typically, the inductor current flowing through the power transistor is monitored when the power transistor is turned on. If the inductor current exceeds the peak current, the power transistor is turned off and the freewheeling diode is turned on, allowing the inductor current to begin to decrease.

[0003] The output voltage ripple of a DC-DC converter is determined by the magnitude of the peak current. A larger peak current results in more energy stored in the inductor and a larger output voltage ripple. Therefore, it is necessary to set the peak current appropriately to avoid excessive output voltage ripple. Summary of the Invention

[0004] The embodiments described herein provide a peak current control circuit for a DC-DC converter.

[0005] According to a first aspect of this disclosure, a peak current control circuit for a DC-DC converter is provided. The peak current control circuit includes: a voltage control circuit, a first voltage-controlled current generating circuit, a second voltage-controlled current generating circuit, a comparison voltage generating circuit, and a voltage comparator. The voltage control circuit is configured to: provide a comparison current to the comparison voltage generating circuit via a first node, and control the voltage of a second node based on a peak reference voltage from a peak reference voltage terminal. The first voltage-controlled current generating circuit is configured to: generate a first current based on the input voltage and output voltage of the DC-DC converter, and provide the first current to the second voltage-controlled current generating circuit via the second node. The second voltage-controlled current generating circuit is configured to: generate a second current based on the voltage of the second node. The second current limits the sum of the first current and the comparison current. The comparison voltage generating circuit is configured to: generate a comparison voltage at the first node based on the comparison current. A first input terminal of the voltage comparator is coupled to the first node. A second input terminal of the voltage comparator is coupled to a first terminal of a power transistor and an inductor of the DC-DC converter. An inductor current peak indication signal is output from the output terminal of the voltage comparator. Specifically, the power transistor is turned off when the inductor current peak indicator signal flips to an active level.

[0006] In some embodiments of this disclosure, the comparison voltage generating circuit includes: a first transistor. The control electrode of the first transistor is coupled to the control electrode of a power transistor. The first electrode of the first transistor is coupled to a first node. The second electrode of the first transistor is coupled to the second electrode of the power transistor.

[0007] In some embodiments of this disclosure, the voltage control circuit includes a second transistor. The control electrode of the second transistor is coupled to a peak reference voltage terminal. The first electrode of the second transistor is coupled to a second node. The second electrode of the second transistor is coupled to a first node.

[0008] In some embodiments of this disclosure, the first voltage-controlled current generating circuit includes a first resistor and a third transistor. A first terminal of the first resistor is coupled to the input voltage terminal of the DC-DC converter. A second terminal of the first resistor is coupled to the first electrode of the third transistor. The control electrode of the third transistor is coupled to the output voltage terminal of the DC-DC converter. The second electrode of the third transistor is coupled to a second node.

[0009] In some embodiments of this disclosure, the second voltage-controlled current generating circuit includes a second resistor. A first terminal of the second resistor is coupled to a second node. A second terminal of the second resistor is coupled to a second voltage terminal.

[0010] In some embodiments of this disclosure, the peak current control circuit further includes a first sleep control circuit. The first sleep control circuit is configured to control the first voltage-controlled current generating circuit to stop generating the first current during a sleep period of the DC-DC converter.

[0011] In some embodiments of this disclosure, the first sleep control circuit includes a fourth transistor. The control electrode of the fourth transistor is coupled to an enable signal terminal. The first electrode of the fourth transistor is coupled to a second node. The second electrode of the fourth transistor is coupled to the output terminal of a first voltage-controlled current generation circuit. During the non-sleep period of the DC-DC converter, the enable signal from the enable signal terminal is at an active level. During the sleep period of the DC-DC converter, the enable signal is at an inactive level.

[0012] In some embodiments of this disclosure, the peak current control circuit further includes a bias current generation circuit. The bias current generation circuit is configured to: provide a bias current to the voltage comparator to enable normal operation of the voltage comparator during the non-sleep period of the DC-DC converter; and stop providing bias current to the voltage comparator to disable the voltage comparator during the sleep period of the DC-DC converter.

[0013] In some embodiments of this disclosure, the bias current generating circuit includes a fifth transistor, a sixth transistor, a first capacitor, and a third resistor. The control electrode of the fifth transistor is coupled to a bias voltage terminal. The first electrode of the fifth transistor is coupled to a first terminal of the third resistor. The second electrode of the fifth transistor is coupled to the bias current input terminal of a voltage comparator. The control electrode of the sixth transistor is coupled to an enable signal terminal. The first electrode of the sixth transistor is coupled to a second voltage terminal. The second electrode of the sixth transistor is coupled to a second terminal of the third resistor. The first terminal of the first capacitor is coupled to the bias voltage terminal. The second terminal of the first capacitor is coupled to the second voltage terminal. During the non-sleep period of the DC-DC converter, the enable signal from the enable signal terminal is at an active level. During the sleep period of the DC-DC converter, the enable signal is at an inactive level.

[0014] According to a second aspect of this disclosure, a peak current control circuit for a DC-DC converter is provided. The peak current control circuit includes: a first transistor to a sixth transistor, a first resistor to a third resistor, a first capacitor, and a voltage comparator. The control electrode of the first transistor is coupled to the control electrode of the power transistor of the DC-DC converter. The first electrode of the first transistor is coupled to the second electrode of the second transistor and the first input terminal of the voltage comparator. The second electrode of the first transistor is coupled to the second electrode of the power transistor. The control electrode of the second transistor is coupled to a peak reference voltage terminal. The first electrode of the second transistor is coupled to the first terminal of the second resistor and the first electrode of the fourth transistor. The second terminal of the second resistor is coupled to a second voltage terminal. The first terminal of the first resistor is coupled to the input voltage terminal of the DC-DC converter. The second terminal of the first resistor is coupled to the first electrode of the third transistor. The control electrode of the third transistor is coupled to the output voltage terminal of the DC-DC converter. The second electrode of the third transistor is coupled to the second electrode of the fourth transistor. The control electrode of the fourth transistor is coupled to an enable signal terminal. The control electrode of the fifth transistor is coupled to a bias voltage terminal. The first electrode of the fifth transistor is coupled to the first terminal of the third resistor. The second electrode of the fifth transistor is coupled to the bias current input terminal of the voltage comparator. The control terminal of the sixth transistor is coupled to the enable signal terminal. The first terminal of the sixth transistor is coupled to the second voltage terminal. The second terminal of the sixth transistor is coupled to the second terminal of the third resistor. The first terminal of the first capacitor is coupled to the bias voltage terminal. The second terminal of the first capacitor is coupled to the second voltage terminal. The second input terminal of the voltage comparator is coupled to the first terminal of the power transistor and the inductor of the DC-DC converter. An inductor current peak indication signal is output from the output terminal of the voltage comparator. The power transistor is off when the inductor current peak indication signal flips to an active level. During the non-sleep period of the DC-DC converter, the enable signal from the enable signal terminal is active. During the sleep period of the DC-DC converter, the enable signal is inactive.

[0015] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes a peak current control circuit as described in a first or second aspect of this disclosure.

[0016] According to a fourth aspect of this disclosure, a chip is provided. The chip includes the DC-DC converter described in a third aspect of this disclosure.

[0017] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a fourth aspect of this disclosure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0019] Figure 1 A schematic block diagram of a peak current control circuit for a DC-DC converter according to an embodiment of the present disclosure is shown.

[0020] Figure 2 An exemplary circuit diagram of a peak current control circuit for a DC-DC converter according to an embodiment of the present disclosure is shown; and

[0021] Figure 3 Further exemplary circuit diagrams of peak current control circuits for DC-DC converters according to embodiments of the present disclosure are shown.

[0022] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1 A schematic block diagram of a peak current control circuit 100 for a DC-DC converter according to an embodiment of the present disclosure is shown. Figure 1 The example also shows the upper transistor Q1, lower transistor Q2, inductor L, and output capacitor Cout of the DC-DC converter. Other components in the DC-DC converter are not shown to avoid obscuring the focus of this disclosure with unnecessary detail.

[0027] Figure 1 Let's take a buck converter as an example. Figure 1 In this example, the upper transistor Q1 is a power transistor, and the lower transistor Q2 is a freewheeling transistor. The control terminal of the upper transistor Q1 is provided with the upper transistor drive signal DR_Q1. The first terminal of the upper transistor Q1 is coupled to the second terminal of the lower transistor Q2 and the first terminal (node ​​SW) of the inductor L. The second terminal of the upper transistor Q1 is coupled to the input voltage terminal VIN. The control terminal of the lower transistor Q2 is provided with the lower transistor drive signal DR_Q2. The first terminal of the lower transistor Q2 is coupled to the second voltage terminal V2. The second terminal of the inductor L is coupled to the output voltage terminal VOUT and the first terminal of the output capacitor Cout. The second terminal of the output capacitor Cout is coupled to the second voltage terminal V2.

[0028] The peak current control circuit 100 according to an embodiment of this disclosure can also be used in a boost converter. In the boost converter, the upper transistor Q1 is a freewheeling transistor and the lower transistor Q2 is a power transistor.

[0029] The peak current control circuit 100 includes: a comparison voltage generation circuit 110, a voltage control circuit 120, a second voltage-controlled current generation circuit 140, a first voltage-controlled current generation circuit 130, and a voltage comparator CMP.

[0030] Voltage control circuit 120 is coupled to the first input of the comparison voltage generation circuit 110 and the voltage comparator CMP via a first node N1. Voltage control circuit 120 is coupled to the first voltage-controlled current generation circuit 130 and the second voltage-controlled current generation circuit 140 via a second node N2. Voltage control circuit 120 is also coupled to a peak reference voltage terminal Vref_peak. Voltage control circuit 120 is configured to: provide a comparison current Is to the comparison voltage generation circuit 110 via the first node N1, provide a comparison current Is to the second voltage-controlled current generation circuit 140 via the second node N2, and control the voltage of the second node N2 based on the peak reference voltage Vref_peak from the peak reference voltage terminal Vref_peak. In some embodiments of this disclosure, voltage control circuit 120 controls the voltage of the second node N2 to a constant value related to the peak reference voltage Vref_peak.

[0031] A first voltage-controlled current generating circuit 130 is coupled to a voltage control circuit 120 and a second voltage-controlled current generating circuit 140 via a second node N2. The first voltage-controlled current generating circuit 130 is configured to generate a first current I1 based on the input voltage VIN and output voltage VOUT of the DC-DC converter, and to provide the first current I1 to the second voltage-controlled current generating circuit 140 via the second node N2. In some embodiments of this disclosure, the first voltage-controlled current generating circuit 130 generates the first current I1 based on the difference between the input voltage VIN and the output voltage VOUT. In one example, I1 = (VIN - VOUT) / m. Where I1 represents the current value of the first current I1, VIN represents the voltage value of the input voltage VIN, VOUT represents the voltage value of the output voltage VOUT, and m is a constant.

[0032] The second voltage-controlled current generating circuit 140 is coupled to the voltage control circuit 120 and the first voltage-controlled current generating circuit 130 via the second node N2. The second voltage-controlled current generating circuit 140 receives a comparison current Is from the voltage control circuit 120. The second voltage-controlled current generating circuit 140 receives a first current I1 from the first voltage-controlled current generating circuit 130. The second voltage-controlled current generating circuit 140 is configured to generate a second current I2 based on the voltage of the second node N2. The second current I2 limits the sum of the first current I1 and the comparison current Is. In some embodiments of this disclosure, the second current I2 is equal to the sum of the first current I1 and the comparison current Is, i.e., I2 = I1 + Is. Here, I2 represents the current value of the second current I2, I1 represents the current value of the first current I1, and Is represents the current value of the comparison current Is. Since the voltage of the second node N2 is constant, the current value of the second current I2 is also constant.

[0033] The comparison voltage generation circuit 110 is coupled to the control terminal and the second terminal of the power transistor Q1. The comparison voltage generation circuit 110 is also coupled to the voltage control circuit 120 and the first input terminal of the voltage comparator CMP via the first node N1. The comparison voltage generation circuit 110 is configured to generate a comparison voltage Vp at the first node N1 based on the comparison current Is.

[0034] The first input terminal of the voltage comparator CMP is coupled to the first node N1. The second input terminal of the voltage comparator CMP is coupled to the first terminal of the power transistor Q1 and the first terminal of the inductor L of the DC-DC converter (i.e., coupled to node SW). The bias current input terminal of the voltage comparator CMP is coupled to a bias current source (not shown) to receive a bias current Ibias from the bias current source. The bias current Ibias provides the operating current for the voltage comparator CMP. The inductor current peak indication signal PeakOut is output from the output terminal of the voltage comparator CMP. The power transistor Q1 is turned off when the inductor current peak indication signal PeakOut toggles to an active level.

[0035] exist Figure 1 In the example, the first input of the voltage comparator CMP is the non-inverting input. The second input of the voltage comparator CMP is the inverting input. The valid level of the inductor current peak indicator signal PeakOut is high. The invalid level of the inductor current peak indicator signal PeakOut is low.

[0036] In the peak current control circuit 100, the voltage control circuit 120 controls the voltage at the second node N2 to a constant value. The second voltage-controlled current generating circuit 140 generates a second current I2 based on the voltage at the second node N2. Therefore, the value of the second current I2 is also constant. Since I2 = I1 + Is, if the first current I1 increases, the comparison current Is decreases. If the first current I1 decreases, the comparison current Is increases. The comparison voltage generating circuit 110 generates a comparison voltage Vp at the first node N1 based on the comparison current Is. When the power transistor Q1 is turned on, the inductor current IL increases (the current flowing through the power transistor Q1 increases). Q1 The voltage Vn at the second input of the voltage comparator CMP decreases as the voltage rises. When the voltage Vn at the second input of the voltage comparator CMP decreases to the comparison voltage Vp, the inductor current peak indication signal PeakOut flips to an active level, thereby controlling the power transistor Q1 to turn off through the DC-DC converter. At this time, the current I... Q1 The peak current Ipeak is reached. Since the comparison voltage Vp is related to the comparison current Is and Is = I2 - I1 = I2 - (VIN - VOUT) / m, and Ipeak is also related to Vp, therefore, Ipeak is related to (VIN - VOUT) / m. When the difference between the input voltage VIN and the output voltage VOUT fluctuates, the peak current Ipeak can change accordingly, thus making the ripple of the output voltage VOUT more stable.

[0037] Figure 2 An exemplary circuit diagram of a peak current control circuit 200 for a DC-DC converter according to an embodiment of the present disclosure is shown. The comparison voltage generation circuit 210 includes a first transistor M1. The control electrode of the first transistor M1 is coupled to the control electrode of a power transistor Q1. The first electrode of the first transistor M1 is coupled to a first node N1. The second electrode of the first transistor M1 is coupled to the second electrode of the power transistor Q1.

[0038] The voltage control circuit 220 includes a second transistor M2. The control electrode of the second transistor M2 is coupled to the peak reference voltage terminal Vref_peak. The first electrode of the second transistor M2 is coupled to the second node N2. The second electrode of the second transistor M2 is coupled to the first node N1.

[0039] The first voltage-controlled current generating circuit 230 includes a first resistor R1 and a third transistor M3. The first terminal of the first resistor R1 is coupled to the input voltage terminal VIN of the DC-DC converter. The second terminal of the first resistor R1 is coupled to the first terminal of the third transistor M3. The control terminal of the third transistor M3 is coupled to the output voltage terminal VOUT of the DC-DC converter. The second terminal of the third transistor M3 is coupled to the second node N2. The first current I1 is equal to the current flowing through the first resistor R1; therefore, I1 = (VIN - VOUT) / R1. Here, R1 represents the resistance value of the first resistor R1, VIN represents the input voltage VIN, and VOUT represents the output voltage VOUT. The threshold voltage of the third transistor M3 can be ignored here.

[0040] The second voltage-controlled current generating circuit 240 includes a second resistor R2. The first end of the second resistor R2 is coupled to the second node N2. The second end of the second resistor R2 is coupled to the second voltage terminal V2.

[0041] In the peak current control circuit 200, the voltage at the second node N2 is equal to (Vref_peak - Vth_M2). Here, Vref_peak represents the peak reference voltage Vref_peak, and Vth_M2 represents the threshold voltage of the second transistor M2. The second current I2 = (Vref_peak - Vth_M2) / R2. Here, R2 represents the resistance of the second resistor. Is = I2 - I1 = (Vref_peak - Vth_M2) / R2 - (VIN - VOUT) / R1. When power transistor Q1 is turned on, the inductor current IL increases (the current flowing through power transistor Q1 increases by 1 / 2). Q1 The voltage Vn at the second input of the voltage comparator CMP decreases as the voltage rises. When the voltage Vn at the second input of the voltage comparator CMP decreases to the comparison voltage Vp, the inductor current peak indication signal PeakOut flips to an active level, thereby controlling the power transistor Q1 to turn off through the DC-DC converter. At this time, the current I... Q1 The peak current Ipeak is reached. Since Vp = Vn at this point, the gate-source voltage of the first transistor M1 is equal to the gate-source voltage of the power transistor Q1. Therefore, Ipeak = Is × k = ((Vref_peak - Vth_M2) / R2 - (VIN - VOUT) / R1) × k. Here, Ipeak represents the peak current value of the inductor current IL, and k represents the ratio of the width-to-length ratio of the power transistor Q1 to that of the first transistor M1. When the difference between the input voltage VIN and the output voltage VOUT fluctuates, the peak current Ipeak can change accordingly, thus making the ripple of the output voltage VOUT more stable.

[0042] exist Figure 2In the example, the second voltage terminal V2 is grounded. The first transistor M1 and the second transistor M2 are NMOS transistors. The third transistor M3 is a PMOS transistor. The first input terminal of the voltage comparator CMP is the non-inverting input terminal. The second input terminal of the voltage comparator CMP is the inverting input terminal. The effective level of the inductor current peak indication signal PeakOut is high. The ineffective level of the inductor current peak indication signal PeakOut is low. Those skilled in the art should understand that, based on the above inventive concept... Figure 2 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 2 The examples shown have different settings.

[0043] In some applications, DC-DC converters enter a sleep phase when the inductor current drops to zero. If the quiescent current of the peak current control circuit can be reduced when the DC-DC converter enters this sleep phase, the power consumption of the DC-DC converter can be reduced. Therefore, embodiments of this disclosure propose... Figure 3 The peak current control circuit 300 shown is shown.

[0044] exist Figure 2 Based on the peak current control circuit 200 shown, Figure 3 The peak current control circuit 300 shown may further include a first sleep control circuit 350. The first sleep control circuit 350 is configured to control the first voltage-controlled current generating circuit 230 to stop generating the first current I1 during the sleep period of the DC-DC converter. The first sleep control circuit 350 is also configured to transfer the first current I1 generated by the first voltage-controlled current generating circuit 230 to the second voltage-controlled current generating circuit 240 during the non-sleep period of the DC-DC converter.

[0045] exist Figure 3 In the example, the first sleep control circuit 350 may include a fourth transistor M4. The control electrode of the fourth transistor M4 is coupled to the enable signal terminal EN. The first electrode of the fourth transistor M4 is coupled to the second node N2. The second electrode of the fourth transistor M4 is coupled to the output terminal of the first voltage-controlled current generation circuit 230. During the non-sleep period of the DC-DC converter, the enable signal EN from the enable signal terminal EN is at an active level. During the sleep period of the DC-DC converter, the enable signal EN is at an inactive level. Therefore, when the DC-DC converter is in a non-sleep period, the fourth transistor M4 is turned on, and a first current I1 is provided to the first voltage-controlled current generation circuit 230. When the DC-DC converter is in a sleep period, the fourth transistor M4 is turned off, the first current I1 is zero, and the static power consumption of the DC-DC converter can be reduced.

[0046] In addition, Figure 2 Based on the peak current control circuit 200 shown, Figure 3 The peak current control circuit 300 shown may further include a bias current generation circuit 360. The bias current generation circuit 360 is configured to: provide bias current to the voltage comparator CMP during the non-sleep period of the DC-DC converter to enable the voltage comparator CMP to operate normally; and stop providing bias current to the voltage comparator CMP during the sleep period of the DC-DC converter to stop the voltage comparator CMP from operating.

[0047] The bias current generating circuit 360 may include: a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a third resistor R3. The control electrode of the fifth transistor M5 is coupled to the bias voltage terminal Vbias. The first electrode of the fifth transistor M5 is coupled to the first terminal of the third resistor R3. The second electrode of the fifth transistor M5 is coupled to the bias current input terminal of the voltage comparator CMP. The control electrode of the sixth transistor M6 is coupled to the enable signal terminal EN. The first electrode of the sixth transistor M6 is coupled to the second voltage terminal V2. The second electrode of the sixth transistor M6 is coupled to the second terminal of the third resistor R3. The first terminal of the first capacitor C1 is coupled to the bias voltage terminal Vbias. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2. During the non-sleep period of the DC-DC converter, the enable signal EN from the enable signal terminal EN is at an active level. During the sleep period of the DC-DC converter, the enable signal EN is at an inactive level.

[0048] During the DC-DC converter's sleep period, the enable signal EN is at an inactive level. At this time, the sixth transistor M6 is off, the bias current Ibias is zero, and the static power consumption of the DC-DC converter can be reduced.

[0049] In summary, Figure 3 In the example, during the DC-DC converter's sleep period, the first current I1 is zero and the bias current Ibias is zero. The first transistor M1 is turned off, therefore, the comparison current Is is also zero. Thus, the quiescent current of the entire peak current control circuit 300 is zero, achieving zero power consumption.

[0050] When the voltage comparator CMP needs to resume operation, the enable signal EN flips to an active level, and the sixth transistor M6 turns on. Since the bias voltage Vbias is always present, there is no need to charge the first capacitor C1, thus the bias current Ibias can be generated quickly, allowing the voltage comparator CMP to resume operation rapidly. At the same time, the fourth transistor M4 turns on, and the quiescent currents of the first current I1, the comparison current Is, and the second current I2 can be established quickly.

[0051] exist Figure 3 In the example, the second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, and the fourth transistors M4 through M6 are NMOS transistors. The third transistor M3 is a PMOS transistor. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0052] Embodiments of this disclosure also provide a DC-DC converter. This DC-DC converter includes a peak current control circuit according to embodiments of this disclosure.

[0053] Embodiments of this disclosure also provide a chip. This chip includes a DC-DC converter according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0054] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0055] In summary, the peak current control circuit for a DC-DC converter according to embodiments of the present disclosure can dynamically control the magnitude of the peak current based on the input voltage and output voltage of the DC-DC converter, thereby reducing output voltage ripple. The peak current control circuit for a DC-DC converter according to embodiments of the present disclosure can also reduce quiescent current during sleep periods, thereby reducing power consumption. Furthermore, the peak current control circuit for a DC-DC converter according to embodiments of the present disclosure can also quickly resume operation when exiting a sleep period.

[0056] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0057] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0058] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A peak current control circuit for a DC-DC converter, comprising: The circuit includes a voltage control circuit, a first voltage-controlled current generation circuit, a second voltage-controlled current generation circuit, a comparison voltage generation circuit, and a voltage comparator. The voltage control circuit is configured to provide a comparison current to the comparison voltage generation circuit via the first node, and control the voltage of the second node based on the peak reference voltage from the peak reference voltage terminal. The first voltage-controlled current generating circuit is configured to generate a first current based on the input voltage and output voltage of the DC-DC converter, and provide the first current to the second voltage-controlled current generating circuit via the second node; The second voltage-controlled current generating circuit is configured to generate a second current based on the voltage of the second node, wherein the second current limits the sum of the first current and the comparison current; The comparison voltage generating circuit is configured to generate a comparison voltage at the first node based on the comparison current; The first input terminal of the voltage comparator is coupled to the first node, and the second input terminal of the voltage comparator is coupled to the first terminal of the power transistor of the DC-DC converter and the inductor of the DC-DC converter. The inductor current peak indication signal is output from the output terminal of the voltage comparator. Specifically, the power transistor is turned off when the inductor current peak indicator signal flips to an active level.

2. The peak current control circuit according to claim 1, wherein, The comparison voltage generating circuit includes: a first transistor, Wherein, the control electrode of the first transistor is coupled to the control electrode of the power transistor, the first electrode of the first transistor is coupled to the first node, and the second electrode of the first transistor is coupled to the second electrode of the power transistor; when the first transistor is a MOS transistor, the first electrode and the second electrode of the first transistor are the other two ends except for the controlled intermediate terminal; when the first transistor is a BJT, the first electrode and the second electrode of the first transistor are the emitter and collector of the BJT, respectively.

3. The peak current control circuit according to claim 1, wherein, The voltage control circuit includes: a second transistor, Wherein, the control electrode of the second transistor is coupled to the peak reference voltage terminal, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the first node; when the second transistor is a MOS transistor, the first electrode and the second electrode of the second transistor are the other two terminals except for the controlled intermediate terminal; when the second transistor is a BJT, the first electrode and the second electrode of the second transistor are the emitter and collector of the BJT, respectively.

4. The peak current control circuit according to claim 1, wherein, The first voltage-controlled current generating circuit includes: a first resistor and a third transistor. Wherein, the first end of the first resistor is coupled to the input voltage terminal of the DC-DC converter, and the second end of the first resistor is coupled to the first terminal of the third transistor; The control electrode of the third transistor is coupled to the output voltage terminal of the DC-DC converter, and the second electrode of the third transistor is coupled to the second node. When the third transistor is a MOS transistor, the first and second electrodes of the third transistor are the other two terminals except for the controlled intermediate terminal. When the third transistor is a BJT, the first and second electrodes of the third transistor are the emitter and collector of the BJT, respectively.

5. The peak current control circuit according to any one of claims 1 to 4, wherein, The second voltage-controlled current generating circuit includes: a second resistor, The first end of the second resistor is coupled to the second node, and the second end of the second resistor is coupled to the second voltage terminal.

6. The peak current control circuit according to any one of claims 1 to 4, further comprising: First sleep control circuit, The first sleep control circuit is configured to control the first voltage-controlled current generating circuit to stop generating the first current during the sleep period of the DC-DC converter.

7. The peak current control circuit according to claim 6, wherein, The first sleep control circuit includes: a fourth transistor, Wherein, the control electrode of the fourth transistor is coupled to the enable signal terminal, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the output terminal of the first voltage-controlled current generating circuit; when the fourth transistor is a MOS transistor, the first electrode and the second electrode of the fourth transistor are the other two terminals except for the controlled intermediate terminal; when the fourth transistor is a BJT, the first electrode and the second electrode of the fourth transistor are the emitter and collector of the BJT, respectively. During the non-sleep period of the DC-DC converter, the enable signal from the enable signal terminal is at an active level; during the sleep period of the DC-DC converter, the enable signal is at an inactive level.

8. The peak current control circuit according to any one of claims 1 to 4, further comprising: Bias current generation circuit The bias current generating circuit is configured to: provide bias current to the voltage comparator during the non-sleep period of the DC-DC converter to enable the voltage comparator to operate normally; and stop providing bias current to the voltage comparator during the sleep period of the DC-DC converter to enable the voltage comparator to stop operating.

9. The peak current control circuit according to claim 8, wherein, The bias current generating circuit includes: a fifth transistor, a sixth transistor, a first capacitor, and a third resistor. The control electrode of the fifth transistor is coupled to the bias voltage terminal, the first electrode of the fifth transistor is coupled to the first terminal of the third resistor, and the second electrode of the fifth transistor is coupled to the bias current input terminal of the voltage comparator. When the fifth transistor is a MOS transistor, the first and second electrodes of the fifth transistor are the other two terminals except for the controlled intermediate terminal. When the fifth transistor is a BJT, the first and second electrodes of the fifth transistor are the emitter and collector of the BJT, respectively. The control electrode of the sixth transistor is coupled to the enable signal terminal, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the second terminal of the third resistor. When the sixth transistor is a MOS transistor, the first electrode and the second electrode of the sixth transistor are the other two terminals except for the controlled intermediate terminal. When the sixth transistor is a BJT, the first electrode and the second electrode of the sixth transistor are the emitter and collector of the BJT, respectively. The first terminal of the first capacitor is coupled to the bias voltage terminal, and the second terminal of the first capacitor is coupled to the second voltage terminal; During the non-sleep period of the DC-DC converter, the enable signal from the enable signal terminal is at an active level; during the sleep period of the DC-DC converter, the enable signal is at an inactive level.

10. A peak current control circuit for a DC-DC converter, comprising: The first to sixth transistors, the first to third resistors, the first capacitor, and the voltage comparator, wherein the first to sixth transistors are all transistors, and when the transistor is a MOS transistor, the first and second terminals of the transistor are the other two terminals except for the controlled intermediate terminal, and when the transistor is a BJT, the first and second terminals of the transistor are the emitter and collector of the BJT, respectively. Wherein, the control electrode of the first transistor is coupled to the control electrode of the power transistor of the DC-DC converter, the first electrode of the first transistor is coupled to the second electrode of the second transistor and the first input terminal of the voltage comparator, and the second electrode of the first transistor is coupled to the second electrode of the power transistor; The control electrode of the second transistor is coupled to the peak reference voltage terminal, and the first electrode of the second transistor is coupled to the first terminal of the second resistor and the first electrode of the fourth transistor; The second end of the second resistor is coupled to the second voltage terminal; The first end of the first resistor is coupled to the input voltage terminal of the DC-DC converter, and the second end of the first resistor is coupled to the first terminal of the third transistor; The control terminal of the third transistor is coupled to the output voltage terminal of the DC-DC converter, and the second terminal of the third transistor is coupled to the second terminal of the fourth transistor; The control electrode of the fourth transistor is coupled to the enable signal terminal; The control electrode of the fifth transistor is coupled to the bias voltage terminal, the first electrode of the fifth transistor is coupled to the first terminal of the third resistor, and the second electrode of the fifth transistor is coupled to the bias current input terminal of the voltage comparator. The control terminal of the sixth transistor is coupled to the enable signal terminal, the first terminal of the sixth transistor is coupled to the second voltage terminal, and the second terminal of the sixth transistor is coupled to the second terminal of the third resistor; The first terminal of the first capacitor is coupled to the bias voltage terminal, and the second terminal of the first capacitor is coupled to the second voltage terminal; The second input terminal of the voltage comparator is coupled to the first terminal of the power transistor and the inductor of the DC-DC converter, and the output terminal of the voltage comparator outputs an inductor current peak indication signal. Specifically, the power transistor is turned off when the inductor current peak indication signal flips to an active level; the enable signal from the enable signal terminal is at an active level during the non-sleep period of the DC-DC converter; and the enable signal is at an inactive level during the sleep period of the DC-DC converter.

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