Redundant master clock method for 5g and tsn converged network

Abstract

The application relates to a redundant master clock method of a 5G and TSN fusion network, belongs to the field of industrial internet, and comprises the following steps: S1: in the 5G and TSN fusion network, a master clock candidate list is established through node parameters and link parameters based on an optimal master clock selection algorithm, and the master clock candidate list is used to describe the process of reconfiguring a master clock; S2: based on the established master clock candidate list, multiple master clocks are allowed to run simultaneously in a working clock domain through an improved state decision algorithm, and a slave clock is simultaneously time-synchronized by a master clock located at a 5G base station and a master clock located at a user equipment (UE) to reduce synchronization errors caused by link congestion and link failure factors. The application reduces the time required for master clock reselection configuration, improves the synchronization accuracy of system time synchronization, and improves the reliability of time synchronization of the 5G and TSN fusion network.

Description

Technical Field

[0001] This invention belongs to the field of industrial internet and relates to a redundant master clock method for a 5G and TSN converged network. Background Technology

[0002] With the development of Industry 4.0, the Industrial Internet requires comprehensive interconnection between various devices and data storage systems in smart factories. These devices have strict timing constraints and must respond accurately to events at specified times. Precise time synchronization provides a common time reference for the entire network and is a key core technology of the Industrial Internet.

[0003] Time-Sensitive Networking (TSN), derived from Ethernet technology, provides bounded low latency, low jitter, and highly reliable data transmission services. Its time synchronization relies on the Generalized Precise Time Protocol (gPTP), comprising two parts: the Optimal Master Clock Algorithm (BMCA) and a time synchronization algorithm. The BMCA algorithm consists of a data comparison set algorithm and a state determination algorithm, selecting the optimal master clock by comparing the clock performance of all network nodes in the system. The time synchronization algorithm causes the master clock to periodically send time synchronization messages containing timestamps. Slave nodes calculate and estimate their time offset relative to the master clock based on the received messages and adjust their time accordingly. In this way, TSN achieves time synchronization between the master and slave clocks.

[0004] Fifth-generation cellular network (5G) technology, as a wireless communication technology, boasts advantages such as flexible deployment, no need for cabling, and mobility support. 5G networks primarily employ on-site deployment to receive GPS, BeiDou, and other signal positioning schemes for time synchronization. Base stations directly acquire the Global Navigation Satellite System (GNSS) clock source through receiving antennas. Through beam scanning and measurement operations, the base station and user equipment establish a physical link connection. The base station then sends a beam carrying synchronization information to the user equipment, which adjusts its time accordingly to synchronize with the base station.

[0005] Smart factories require unified communication between different systems across horizontal and vertical domains, which involves supporting real-time capabilities and heterogeneous traffic. Furthermore, smart factory scenarios involve numerous mobile use cases, making mobility and scalability key requirements for future communication technologies. Therefore, the convergence of TSN and 5G is fundamental to achieving deterministic, low-latency, mobile, and scalable communication. However, TSN and 5G have different time synchronization mechanisms; thus, achieving a converged time synchronization technology between the two becomes crucial. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a method for reconfiguring the master clock, which reduces the communication volume and latency generated during the master clock reconfiguration process and improves synchronization accuracy; it also proposes a redundant master clock method, which improves the reliability and synchronization accuracy of time synchronization in 5G and TSN converged networks.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A method for redundant master clock in a 5G and TSN converged network includes the following steps:

[0009] S1: In a 5G and TSN converged network, based on the best master clock selection algorithm, a master clock candidate list is established through node parameters and link parameters, and the master clock candidate list is used to describe the process of reconfiguring the master clock.

[0010] S2: Based on the established master clock candidate list, multiple master clocks are allowed to run simultaneously in one working clock domain through an improved state decision algorithm. The slave clocks are synchronized simultaneously by the master clock located at the 5G base station and the master clock located at the user equipment (UE) to mitigate synchronization errors caused by link congestion and link failure.

[0011] Furthermore, the optimal master clock selection algorithm selects the master clock with the best clock performance and establishes a tree-like synchronization hierarchy. It also determines the master-slave direction of the clock by determining the port status of each terminal. The optimal master clock algorithm consists of a dataset comparison algorithm and a state decision algorithm.

[0012] The dataset comparison algorithm uses information contained in the synchronization message to find the optimal port configuration;

[0013] Each terminal node, based on the state decision algorithm, searches for the clock vector in the dataset comparison algorithm and the local dataset to determine the recommended port state; the port state includes master port state, slave port state, passive port state, and disabled port state; each valid synchronization link includes a master port state and a slave port state, while the passive port state and disabled port state are not responsible for transmitting messages.

[0014] Furthermore, the synchronization message is forwarded from one terminal node to another within the same working clock domain. The synchronization message contains six clock attributes used to determine clock performance, namely, clock node priority 1, clock level, clock precision, priority 2, topology information participating in the algorithm judgment, and clock variance. The measurement basis for priority 1 and priority 2 includes the clock type of the clock node, the estimated clock error, and the estimated value of the clock variance. By continuously comparing the clock vectors containing six elements of the two terminals, the best master clock and the most suitable port can be found from all network nodes.

[0015] Furthermore, in the optimal master clock selection algorithm, the network is described as a directed graph consisting of a set of vertices ν and a set of edges ε; vertex v i ∈v is associated with clock i. Edge e i→i+1 ∈ε is the starting vertex v i and the endpoint vertex v i+1 Directional links between them; vertex v i There are one or more connections v i and v j port Each port is considered the best possible master clock, and its synchronization path to all other remaining ports is determined by this. The set is called the synchronization layer. Synchronization path It is a list;

[0016] S11: Obtain the clock weight w for each clock based on six clock attributes. c (i):

[0017] w c (i)=f c (v i .prio1,v i .class,v i .acc,v i .var,v i .prio2,v i .id)

[0018] Where v i .prio1 indicates priority 1, v i .class indicates clock class, v i .acc indicates clock precision, v i .var represents the clock variance, v i .prio2 indicates priority 2, v i .id represents a clock identifier;

[0019] The clock weights are normalized so that their values ​​are between 0 and 1; the smaller the value, the better the clock properties.

[0020] S12: Set the reference set and calculate vertex v i To vertex v j Link weight w l (i,j):

[0021] w l (i,j)=f l (e i→j.fail,e i→j .err,e i→j .delay,e i→j .cong)

[0022] The reference set includes the failure probability (e i→j .fail), grouping error rate (e i→j .err), propagation delay (e i→ j .delay), congestion coefficient (e i→j .cong);

[0023] The link weights are normalized so that their values ​​are between 0 and 1; the smaller the value, the better the link attribute.

[0024] S13: Combine clock weights and link weights into a combined link weight w cl (i,j), evaluate the clock properties of each master clock candidate to all other nodes and links;

[0025] w cl (i,j)=(λ·w c (i)+(1-λ)·w l (i,j))

[0026] Where λ is the factor that affects clock weight or link weight. The combined link weight is normalized so that the value of the combined link weight is between 0 and 1. The smaller the value, the better the link attribute.

[0027] S14: Evaluate the synchronization path of each master clock candidate in the network to obtain a master clock candidate list.

[0028] Furthermore, step S14, which evaluates the synchronization path of each master clock candidate in the network to obtain the master clock candidate list, specifically includes the following steps: given a network consisting of a set of vertices ν and a set of edges ε;

[0029] S141: Identify a candidate master clock node and reset its synchronization metric to 0;

[0030] S142: Find the shortest path from it to all other slave nodes using the shortest path algorithm, calculate the combined link weights of the corresponding paths, and sum these combined link weights. Defined as the corresponding hybrid synchronization factor;

[0031] S143: Repeat step S142 for all remaining candidate master clock nodes to obtain the hybrid synchronization factor of all candidate master clock nodes;

[0032] S144: Traverse all possible paths from all master clock nodes to all other nodes, and define the sum of the number of these paths as the redundancy of the corresponding candidate master clock node;

[0033] S145: Establish a master clock candidate sequence list in ascending order of hybrid synchronization factor.

[0034] Furthermore, in step S2, the step of allowing multiple master clocks to run simultaneously in a single working clock domain based on the established master clock candidate list and through an improved state decision algorithm is achieved by improving the state decision algorithm of the optimal master clock selection algorithm, forcing nodes in the passive port state to run in the master node state. Specifically, this includes the following steps:

[0035] S21: Determine whether a synchronization message was sent within the timeout period. If not, restart the determination after receiving the synchronization message; if yes, proceed to the next step.

[0036] S22: Confirm the stage order in the master clock candidate list;

[0037] S23: Determine if the node's MAC address is equal to the master clock's MAC address. If not, return to step S22. If yes, change all ports of the node to master port mode.

[0038] S24: Determine whether to send a synchronization message. If not, return to step S22; if yes, send a synchronization message.

[0039] Furthermore, step S2, which describes simultaneously timing the slave clock using the master clock located at the 5G base station and the master clock located at the UE to mitigate synchronization errors caused by link congestion and link failure, specifically includes:

[0040] To improve the reliability of the master clock, two master clocks are set up in the time synchronization architecture of the 5G and TSN converged network, located on the 5G base station and the user equipment (UE) respectively; the master clock 1 located on the 5G base station provides time synchronization for the TSN terminals on the network side, and the master clock 2 located on the user equipment (UE) provides time synchronization for the TSN terminals on the device side.

[0041] First, the master clock 1 obtains its time source through GPS or the BeiDou satellite system;

[0042] Then, Master Clock 1 sends time to Master Clock 2 through the built-in time synchronization mechanism of the 5G system, thus completing the time synchronization between the two master clocks.

[0043] This divides the time synchronization process of the 5G and TSN converged network into two independent gPTP domains: one for network-side TSN device time synchronization, which is timed by master clock 1 via the gPTP protocol, and the other for device-side TSN device time synchronization, which is timed by master clock 2 via the gPTP protocol.

[0044] The beneficial effects of this invention are as follows: This invention improves the efficiency of reconfiguring the master clock, reduces the synchronization error and synchronization delay of the system, and improves the synchronization accuracy; when the master clock fails, using this redundant master clock method will make the time synchronization accuracy almost error-free, and this method improves the reliability of time synchronization in 5G and TSN converged networks.

[0045] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0047] Figure 1 A transparent time synchronization architecture diagram for a 5G and TSN converged network;

[0048] Figure 2 Flowchart of the improved port decision algorithm;

[0049] Figure 3 Diagram of redundant master clock architecture;

[0050] Figure 4 Reconfigure the delay graph of the master clock for two master clock algorithms;

[0051] Figure 5 A comparison chart of synchronization errors between the network-side and the clock system.

[0052] Figure 6 A comparison chart of synchronization error values ​​between the device and the clock system;

[0053] Figure 7 This is a comparison chart of system synchronization error values ​​when a fault occurs. Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0055] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0056] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0057] like Figure 1 As shown, to integrate 5G with TSN, 3GPP provides an architectural model for converged networks. It introduces TSN converters (TTs) at both the network and device levels into 5GS, namely NW-TT and DS-TT. NW-TT is integrated into the User Plane Function (UPF), while DS-TT is integrated into the User Equipment (UE), with radio connectivity provided to the UE by the gNB base station. 5GS (including NW-TT and DS-TT) is referred to as a Virtual TSN Bridge (VTB). It consists of only one UPF associated with one NW-TT, but may include multiple UEs.

[0058] For TSN networks, the 5GS function acts as one or more TSN bridges. A 5GS bridge consists of a port on the UPF side, a user plane tunnel between the UE and the UPF, and a port on the DS-TT side. For each 5GS bridge in a TSN network, the port on the NW-TT supports connectivity to the TSN network, while the port on the DS-TT side is associated with a PDU session, thus providing connectivity to the TSN network. The VTB supports time synchronization via IEEE 802.1AS to become a standards-compliant TSN virtual bridge. Therefore, the VTB can use a transparent clock approach, where 5GS is used as a transparent clock between the two TTs. In this case, the VTB does not need to synchronize with the external GM, but instead sends gPTP messages from the port to the master port and uses the 5GS timescale for correction. Simultaneously, both the DS-TT and NW-TT use boundary clocks, synchronizing themselves with the TSN GM and participating in the measurement of propagation delay.

[0059] Depending on the industrial scenario, there are multiple ways to map the master clock and synchronization device. Generally, the master clock can be located on any device that can provide master clock functionality. However, different 5G network and TSN integration layouts and the requirements of cyber-physical control applications require more ways to map the master clock, including the following: (1) located on the network side on the TSN device connected to the 5G network via NW-TT; (2) located on the core network device of the 5G network; (3) located on the radio access network device of the 5G network; (4) located on the user equipment; (5) located on the UE side on the TSN device connected to the 5G network via DS-TT.

[0060] A time-aware network consists of a time-aware system, which includes time-aware terminals and time-aware bridges. Terminals are the sources or receivers of data streams and consist of terminal devices such as sensors and actuators; bridges are responsible for data transmission and include network forwarding devices such as switches and routers. The optimal master clock algorithm selects the master clock with the best clock performance and establishes a spanning tree-like synchronization hierarchy. It determines the master-slave direction of the clock by determining the port state of each terminal. The optimal master clock algorithm consists of a dataset comparison algorithm and a state decision algorithm.

[0061] (1) Dataset Comparison Algorithm: The dataset comparison algorithm uses information contained in the synchronization message to find the optimal port configuration. The synchronization message is forwarded from one terminal node to another within the same working clock domain. The synchronization message contains six parameters used to determine clock performance: priority 1 of the clock node, clock class, clock accuracy, priority 2, and topology information used in the algorithm's judgment. The metrics for priority 1 and priority 2 include the clock type of the clock node, the estimated clock error, and the estimated clock variance.

[0062] By continuously comparing the six-element clock vectors of the two terminals, it is possible to find the optimal master clock and the most suitable port from all network nodes.

[0063] (2) State Decision Algorithm: Each terminal node determines the recommended port state through a state decision algorithm. These port states are determined primarily by comparing the clock vector in the dataset comparison algorithm with the local dataset. Port states include master port state, slave port state, passive port state, and disabled port state. Each valid synchronization link contains a master port state and a slave port state, while the passive and disabled port states are not responsible for message transmission.

[0064] (3) Redundancy of the optimal master clock algorithm: IEEE 802.1AS adds support for redundant synchronization and hot backup protection operations. Redundancy and reliability of synchronization are increased by establishing a redundant synchronization hierarchy for a single time domain. End nodes may receive the same synchronization message through different synchronization paths, but IEEE 802.1AS lacks provisions for discarding duplicate synchronization messages.

[0065] Hot backup protection introduces a primary master clock and a secondary master clock. The primary master clock establishes a master clock and operates according to IEEE 802.1AS. A secondary time domain is established from the primary master clock, containing all clock nodes in the primary time domain. The secondary master clock is synchronized with the primary master clock, thus providing the primary master clock's reference time to all clock nodes in the secondary time domain. When a link failure occurs in the primary time domain, the primary master clock disconnects from the primary time domain, and all clock nodes can seamlessly switch to the secondary time domain, avoiding delays caused by re-performing the optimal master clock algorithm. However, time domain switching may lead to increased signaling resources and is prone to switching errors.

[0066] In time-sensitive networks, the optimal master clock algorithm is the mechanism for designating the reference clock source, i.e., the master clock. Originally designed for wired networks, the optimal master clock algorithm selects the master clock through a rigorous comparison of predetermined clock attributes. In converged wired and wireless networks, it lacks consideration of the basic network information required for master clock selection. Furthermore, related research indicates that the synchronization quality of wireless networks is affected by the transmission link. As timing information is transmitted through the network and corrected, it accumulates correction errors due to uncertain wireless communication links and volatile network equipment. Moreover, the optimal master clock algorithm considers the statically and manually configured priority 1 as a critical parameter for master clock selection, which is a sensitive source of error in dynamic network environments.

[0067] If the current master clock fails, a switchover from the old master to a new master is required. In this situation, the slave nodes must resynchronize with the new master node. During the resynchronization process, the slave clocks will fluctuate, causing significant synchronization errors. If multiple master clocks are operating simultaneously, redundant operations can mitigate the impact of the switchover on synchronization quality.

[0068] The optimal master clock selection algorithm obtains the clock attributes of each terminal and its possible synchronization paths to all other terminal nodes, then constructs a candidate table of optimal master clocks based on these node parameters and link parameters, and performs a reselection process of the optimal master clock through the candidate table.

[0069] In the optimal master clock selection algorithm, the network is described as a directed graph consisting of a set of vertices v and a set of edges ε. Vertex v i ∈v is associated with clock i. Edge e i→i+1 ∈ε is the starting vertex v i and the endpoint vertex v i+1 The directional link between them. Vertex v i There are one or more connections v i and v j port

[0070] Each port is considered the best possible master clock, and its synchronization path to all other remaining ports is determined by this. The set is called the synchronization layer. Synchronization path It is a list.

[0071] 1) Clock Model: Clocks on the synchronization path can introduce synchronization errors due to inaccurate timestamps. These inaccuracies are caused by factors such as time offset, time drift, finite oscillator frequency, or random noise. To quantify clock performance, the clock attributes already established in the optimal master clock algorithm are utilized. These attributes allow us to find the clock weight w corresponding to each clock. c (i). Clock weight is a function f c (1) The result uses the clock attributes established in the best master clock as input. These clock weights are normalized so that the weight values ​​are between 0 and 1, and the smaller the value, the better the clock attribute.

[0072] w c (i)=f c (v i .prio1,v i .class,v i .acc,v i .var,v i .prio2,vi .id) (1)

[0073] 2) Link Model: Intermediate links in the synchronization path do not introduce direct errors to synchronization like intermediate vertices. However, they can introduce uncertainty due to potential link failures and packet loss. This uncertainty typically does not occur in wired network environments. However, in 5G and TSN converged networks, the dynamic network environment introduces these uncertainties, including link failures, packet loss, and propagation delays that lead to timeouts. Simultaneously, in order to find vertex v... i To vertex v j Link weight w i (i,j), choose the following parameters as the reference set:

[0074] Failure probability: (e i→j .fail)

[0075] Grouping error rate: (e i→j .err)

[0076] Propagation delay: (e i→j .delay)

[0077] Congestion coefficient: (e i→j .cong)

[0078] Link weight w l (i,j) is a function f l (2) The result is that the function uses the above reference set as input. Similar to the clock weight, the link weight is also normalized, with the weight value between 0 and 1, and the smaller the value, the better the link attribute.

[0079] w l (i,j)=f l (e i→j .fail,e i→j .err,e i→j .delay,e i→j .cong) (2)

[0080] To evaluate the clock attributes of each master clock candidate to all other nodes and links, clock weights and link weights are combined into a composite link weight w. cl (i,j) can be found using equation (3). λ is a factor that affects the clock weight or link weight. The corresponding combined link weight value is also between 0 and 1, and the smaller the value, the better.

[0081] w cl (i,j)=(λ·w c (i)+(1-λ)·w l (i,j)) (3)

[0082] A master clock candidate list is obtained by evaluating the synchronization path of each master clock candidate in the network. This helps in finding the optimal master clock and alternative solutions. The following algorithm describes the creation process of the master clock candidate list. Given a network consisting of a set of vertices ν and a set of edges ε, this method finds the synchronization metrics of all possible candidate master clock nodes. First, a candidate master clock node is identified, and its synchronization metric is reset to 0. Then, the shortest path algorithm is used to find the shortest path from it to all other slave nodes, and the combined link weights of the corresponding paths are calculated. The sum of these combined link weights is then calculated. This is defined as the corresponding hybrid synchronization factor. By repeating the above operation for all remaining candidate master clock nodes, the hybrid synchronization factor of all candidate master clock nodes can be obtained. Simultaneously, to check the redundancy of these candidate master clock nodes, all possible paths from each master clock node to all other nodes are traversed, and the sum of the number of these paths is defined as the redundancy of that candidate master clock node. Then, a master clock candidate sequence list is built in ascending order of hybrid synchronization factor, thus easily finding the optimal master clock and its candidate nodes.

[0083]

[0084]

[0085] Generally speaking, the optimal master clock selection algorithm not only determines which clock node becomes the optimal master clock, but also determines the operating state of each node. This function is mainly implemented through a state decision algorithm. To enable multiple master clocks to run simultaneously, some modifications have been made to the state decision algorithm.

[0086] According to the state decision algorithm, in a working clock domain, typically only one node can operate in the master state. Other candidate nodes for the master node must be in a passive state, and they cannot exchange timing packet messages with slave nodes. To enable multiple master clocks to operate simultaneously, nodes in the passive port state are forced to operate in the master node state. The specific steps are as follows... Figure 2 As shown.

[0087] ①: Determine whether a synchronization message was sent within the timeout period. If not, restart the determination after receiving the synchronization message; if yes, proceed to the next step.

[0088] ②: Confirm the stage order in the master clock candidate list;

[0089] ③: Determine if the node's MAC address is equal to the master clock's MAC address. If not, return to step ②; if so, change all ports of the node to master port mode.

[0090] ④: Determine whether to send a synchronization message. If not, return to step ②; if yes, send a synchronization message.

[0091] like Figure 3 As shown, to improve the reliability of the master clock, two master clocks are proposed in the time synchronization architecture of the 5G and TSN converged network, located on the 5G base station and the user equipment (UE), respectively. Master clock 1, located on the 5G base station, provides time synchronization for the TSN terminals on the network side, while master clock 2, located on the UE, provides time synchronization for the TSN terminals on the device side.

[0092] Master Clock 1 obtains its time source via GPS or BeiDou satellite systems. Then, Master Clock 1 synchronizes its time with Master Clock 2 through the 5G system's time synchronization mechanism, completing the time synchronization between the two master clocks. In this way, the time synchronization process of the entire converged network is divided into two independent gPTP domains: one for network-side TSN device time synchronization, synchronized by Master Clock 1 using the gPTP protocol; and the other for device-side TSN device time synchronization, synchronized by Master Clock 2 using the gPTP protocol.

[0093] Experimental evaluation:

[0094] In order to objectively reflect the impact of different propagation delay estimation methods on time synchronization accuracy, the following performance indicators are defined by comparing the two methods: "optimal master clock selection algorithm" and "optimal master clock selection algorithm using sequence list": (1) Delay: the delay required when reconfiguring the master clock. The smaller the delay, the better. (2) Synchronization error: the redundant master clock algorithm based on hybrid synchronization factor mainly considers improving the synchronization accuracy. Therefore, the smaller the synchronization error, the higher the synchronization accuracy.

[0095] The experiment assumes that the time synchronization system error follows a zero-mean Gaussian distribution, with the variance constrained between [-3, 3]. The propagation delay error from the UE to the outside of the gNB in ​​the time synchronization system is 0. The size of the 5G service area is 100m × 100m, and it is also assumed that the UE knows the location of the base station.

[0096] Figure 4 The graph shows a comparison of the latency of reconfiguring the master clock using BMCA and the sequence-list-based master clock selection algorithm. As can be seen from the graph, the latency of both algorithms gradually increases as the reconfiguration process progresses. Reconfiguring the master clock using BMCA takes about 500ms, while the sequence-list-based master clock selection algorithm takes about 466ms, improving the efficiency of master clock reconfiguration by 6.8%.

[0097] Figure 5The graph shows a comparison of system synchronization errors on the network side under two scenarios: a single master clock algorithm and a redundant master clock algorithm based on a hybrid synchronization factor. It can be seen that the overall system synchronization error decreases after using the redundant master clock algorithm based on the hybrid synchronization factor. Furthermore, the synchronization error decreases more significantly with the increase of the priority coefficients of node weight and link weight. When λ increases to 0.9, the system synchronization latency decreases by 0.13 μs, and the synchronization accuracy improves by 10.2%. This indicates that even in a 5G and TSN converged network environment, the clock attributes of the terminal itself have a greater impact on synchronization quality.

[0098] Figure 6 The graph shows a comparison of system synchronization errors for the device-side slave clock under two scenarios: a single master clock algorithm and a redundant master clock algorithm based on a hybrid synchronization factor. Similarly, using the redundant master clock algorithm based on the hybrid synchronization factor also resulted in an overall decrease in system synchronization error. Furthermore, the synchronization error decreased accordingly with the increase of the priority coefficient λ. This indicates that, when the device measures the master clock, the clock attributes of the node itself have a greater impact on synchronization quality. When λ is set to 0.9, the system synchronization error decreased by 0.10 μs, and the synchronization accuracy improved by 8.9%.

[0099] Figure 7 This graph compares the system errors when using a single master clock algorithm and a redundant master clock algorithm in the event of a master clock failure. As can be seen from the graph, when using the single master clock algorithm, the time synchronization accuracy is significantly affected by the master clock switching operation when the master clock fails. However, when using the redundant master clock algorithm, the time synchronization accuracy is almost error-free. This demonstrates that the redundant master clock algorithm improves the reliability of time synchronization in 5G and TSN converged networks.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for redundant master clock in a 5G and TSN converged network, characterized in that: Includes the following steps: S1: In a 5G and TSN converged network, based on the best master clock selection algorithm, a master clock candidate list is established through node parameters and link parameters, and the master clock candidate list is used to describe the process of reconfiguring the master clock. S2: Based on the established master clock candidate list, an improved state decision algorithm is used to allow multiple master clocks to run simultaneously in one working clock domain, and to simultaneously synchronize the slave clocks through the master clock located at the 5G base station and the master clock located at the user equipment (UE). In the optimal master clock selection algorithm, the network is described as a directed graph consisting of a set of vertices. ν and a set of edges ε Composition; Vertex With clock Related; edge It is the starting point and the vertex. and the final vertex Directional links between vertices; vertices There are one or more connections and port Each port is considered as the optimal master clock, and its synchronization path to all other remaining ports is also considered. The set is called the synchronization layer. Synchronization path It is a list; S11: Obtain the clock weight corresponding to each clock based on six clock attributes. : in Indicates priority 1. Indicates clock level, Indicates clock precision. Represents clock variance. Indicates priority 2. Indicates a clock identifier; The clock weights are normalized so that their values ​​are between 0 and 1; the smaller the value, the better the clock properties. S12: Set the reference set and calculate the vertices. To the top Link weights between : The reference set includes failure probabilities Grouping error rate Propagation delay Congestion coefficient ; The link weights are normalized so that their values ​​are between 0 and 1; the smaller the value, the better the link attribute. S13: Combine clock weights and link weights into a combined link weight. Evaluate the clock properties of each master clock candidate to all other nodes and links; in These are factors that affect clock weight or link weight. Normalize the combined link weight so that its value is between 0 and 1. The smaller the value, the better the link attribute. S14: Evaluate the synchronization path of each master clock candidate in the network to obtain a master clock candidate list; Step S14, which evaluates the synchronization path of each master clock candidate in the network to obtain the master clock candidate list, specifically includes the following steps: given a set of vertices ν and a set of edges ε The network formed; S141: Identify a candidate master clock node and reset its synchronization metric to 0; S142: Find the shortest path from it to all other slave nodes using the shortest path algorithm, calculate the combined link weights of the corresponding paths, and sum these combined link weights. Defined as the corresponding hybrid synchronization factor; S143: Repeat step S142 for all remaining candidate master clock nodes to obtain the hybrid synchronization factor of all candidate master clock nodes; S144: Traverse all possible paths from all master clock nodes to all other nodes, and define the sum of the number of these paths as the redundancy of the corresponding candidate master clock node; S145: Establish a master clock candidate sequence list in ascending order of hybrid synchronization factor; In step S2, the step of allowing multiple master clocks to run simultaneously in a single working clock domain based on the established master clock candidate list and through an improved state decision algorithm is achieved by improving the state decision algorithm of the optimal master clock selection algorithm, forcing nodes in the passive port state to run in the master node state. Specifically, this includes the following steps: S21: Determine whether a synchronization message was sent within the timeout period. If not, restart the determination after receiving the synchronization message; if yes, proceed to the next step. S22: Confirm the stage order in the master clock candidate list; S23: Determine if the node's MAC address is equal to the master clock's MAC address. If not, return to step S22. If yes, change all ports of the node to master port mode. S24: Determine whether to send a synchronization message. If not, return to step S22; if yes, send a synchronization message. Step S2, which involves simultaneously timing the slave clock using the master clock located at the 5G base station and the master clock located at the user equipment (UE), specifically includes: In the time synchronization architecture of the 5G and TSN converged network, two master clocks are set up, one on the 5G base station and the other on the user equipment (UE). Master clock 1 on the 5G base station provides time synchronization for the TSN terminals on the network side, and master clock 2 on the user equipment (UE) provides time synchronization for the TSN terminals on the device side. First, the master clock 1 obtains its time source through GPS or the BeiDou satellite system; Then, Master Clock 1 sends time to Master Clock 2 through the built-in time synchronization mechanism of the 5G system, thus completing the time synchronization between the two master clocks. This divides the time synchronization process of the 5G and TSN converged network into two independent gPTP domains: one for network-side TSN device time synchronization, which is timed by master clock 1 via the gPTP protocol, and the other for device-side TSN device time synchronization, which is timed by master clock 2 via the gPTP protocol.

2. The redundant master clock method for a 5G and TSN converged network according to claim 1, characterized in that: The optimal master clock selection algorithm selects the master clock with the best clock performance and establishes a tree-like synchronization hierarchy. It also determines the master-slave direction of the clock by determining the port status of each terminal. The optimal master clock algorithm consists of a dataset comparison algorithm and a state decision algorithm. The dataset comparison algorithm uses information contained in the synchronization message to find the optimal port configuration; Each terminal node, based on the state decision algorithm, searches for the clock vector in the dataset comparison algorithm and the local dataset to determine the recommended port state; Port states include master port state, slave port state, passive port state, and disabled port state; each valid synchronization link contains a master port state and a slave port state, while the passive port state and disabled port state are not responsible for transmitting messages.

3. The redundant master clock method for a 5G and TSN converged network according to claim 2, characterized in that: The synchronization message is forwarded from each terminal node to another terminal node within the same working clock domain. The synchronization message contains six clock attributes used to determine clock performance, namely, the clock node's priority 1, clock level, clock precision, priority 2, topology information participating in the algorithm's judgment, and clock variance. The measurement basis for priority 1 and priority 2 includes the clock type of the clock node, the estimated clock error, and the estimated value of the clock variance. By continuously comparing the six-element clock vectors of the two terminals, it is possible to find the optimal master clock and the most suitable port from all network nodes.

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