FPGA clock layout routing method and system

Abstract

The application relates to the technical field of clock layout wiring, and discloses an FPGA clock layout wiring method and system, which is applied to an FPGA device containing multiple clock domains, and comprises the following steps: reducing the boundary frame of the clock in each clock domain until the number of clocks in each clock domain is legal; allocating clock resources to the clock so that the boundary frames of the clocks allocated to the same clock resource do not overlap, and the clock resources of the clock do not exceed the range of the corresponding boundary frame; after the clock resource allocation is completed, a clock balance tree is constructed in the boundary frame of each clock so that the delay of each clock from the source to each destination node is the same; and the routing algorithm is used to realize the routing from the clock source to the root node of the clock balance tree. The clock resources are allocated in advance and the clock balance tree is constructed, so that the congestion problem of the resources in the layout wiring process is avoided, and the attenuation and interference of the signals in the transmission process are effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of clock placement and routing technology, and specifically to an FPGA clock placement and routing method and system. Background Technology

[0002] FPGA (Field Programmable Gate Array) is a programmable digital logic device that can be used to implement various complex digital logic functions. It includes a more complex clock architecture logic on top of its configurability, used for synchronous operation, timing control, performance optimization, and design simplification. However, the physical structure of the clock network in an FPGA is pre-fabricated and cannot be adjusted for different application scenarios. Generally, an FPGA device is divided into multiple clock domains, each containing limited clock resources. This means that the number of clocks allocated to each clock domain cannot exceed a preset value, which is far less than the total number of clocks an FPGA needs to provide. For high-utilization designs, as the design scale and complexity increase, FPGAs often need to support hundreds of clocks. Therefore, the clock architecture, under the constraint of additional clock limitations, further complicates placement and routing. Traditional FPGA placement and routing methods are increasingly unable to support large-scale clock structures.

[0003] Therefore, there is an urgent need for a placement and routing method that can support FPGA ultra-large scale clocks. Summary of the Invention

[0004] In view of this, this application provides an FPGA clock placement and routing method and system that can support the placement and routing of FPGA ultra-large scale clocks. The technical solution is as follows.

[0005] In a first aspect, the present invention provides an FPGA clock placement and routing method, the method being applied to an FPGA device comprising multiple clock domains, the method comprising:

[0006] Narrow the bounding box of clocks within each clock domain until the number of clocks in each clock domain is legal;

[0007] The clock resources of the clocks are allocated such that the bounding boxes of clocks allocated to the same clock resources do not overlap, and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes.

[0008] After the clock resources are allocated, a clock balancing tree is built within the bounding box of each clock to ensure that the delay of each clock from the source to each destination node is the same.

[0009] The routing algorithm is used to route from the clock source to the root node of the clock balance tree.

[0010] In one alternative implementation, narrowing the bounding box of clocks within a clock domain until the number of clocks within each clock domain is valid includes:

[0011] Set capacity limits for each clock domain; these capacity limits characterize the maximum number of clocks in each clock domain.

[0012] An iterative method is used to adjust the bounding boxes of clocks within each clock domain, ensuring that the total number of clocks within a clock domain does not exceed the capacity limit corresponding to that clock domain.

[0013] In one alternative implementation, the allocation of clock resources for the clock includes:

[0014] Obtain the distance and layout parameters between clocks within each clock domain;

[0015] Based on the distance and layout parameters, a unique resource identifier is assigned to each clock, ensuring that the bounding boxes of clocks allocated to the same clock resource do not overlap, and that the clock resource of a clock does not exceed the range of its corresponding bounding box.

[0016] In one alternative implementation, constructing a clock balance tree within the bounding boxes of each clock includes:

[0017] Select the root node of the clock balance tree within the current clock's bounding box;

[0018] Starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes traversed in the path from the root node to any target node is equal.

[0019] In one alternative implementation, the routing algorithm for routing from the clock source to the root node of the clock balancing tree includes:

[0020] The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and after visiting the adjacent nodes, starts visiting from the adjacent nodes again until the root node of the clock balance tree is reached, thus obtaining the traversal path.

[0021] Based on the traversal access path, the target access path is obtained, realizing the routing from the clock source to the root node of the clock balance tree.

[0022] The FPGA clock layout and routing method provided by this invention has the following advantages.

[0023] This invention discloses an FPGA clock placement and routing method applied to an FPGA device comprising multiple clock domains. By narrowing the bounding boxes of clocks within each clock domain until the number of clocks within each domain is legal, the number of clocks within a clock domain is legalized. This ensures that the number of clocks in each clock domain does not exceed the resource capacity of that clock domain, and that placement and routing can effectively support these clocks. After legalization, clock resources are allocated so that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of a clock do not exceed the corresponding bounding box range, alleviating the placement and routing resource congestion problem caused by ultra-large-scale clocks. After clock resource allocation, a clock balancing tree is constructed within the bounding boxes of each clock, ensuring that the delay from the source to each destination node is the same for each clock, reducing signal synchronization problems caused by clock skew. This structure ensures consistent clock signal transmission time, effectively solving the clock skew problem in the FPGA placement and routing process, thereby optimizing the system's clock performance. By implementing a routing algorithm to route the clock source to the root node of the clock balancing tree, the shortest possible path is ensured, thereby minimizing clock signal delay and avoiding additional skew and latency introduced by excessively long clock transmission paths. The FPGA clock placement and routing method provided by this invention, through pre-allocation of clock resources, can support hundreds of clock scales with limited clock routing resources, ensuring no resource congestion issues occur in subsequent placement and routing processes. Furthermore, the construction of the clock balancing tree in this embodiment further reduces clock skew while satisfying the complex constraints of placement and routing, enhancing signal integrity, effectively reducing signal attenuation and interference during transmission, and improving overall system performance.

[0024] Secondly, the present invention provides an FPGA clock placement and routing system, which is applied to an FPGA device comprising multiple clock domains, the system comprising:

[0025] The legalization module is used to narrow down the bounding box of clocks within a clock domain until the number of clocks in each clock domain is legal.

[0026] The clock resource allocation module is used to allocate clock resources to clocks so that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of clocks do not exceed the range of the corresponding bounding box.

[0027] The balanced tree construction module is used to build a clock balanced tree within the bounding box of each clock after clock resources are allocated, so that the delay of each clock from the source to each destination node is the same.

[0028] The routing module is used to implement routing from the clock source to the root node of the clock balance tree through routing algorithms.

[0029] In one alternative implementation, the legalization module is specifically used for:

[0030] Set capacity limits for each clock domain; these capacity limits characterize the maximum number of clocks in each clock domain.

[0031] An iterative method is used to adjust the bounding boxes of clocks within each clock domain, ensuring that the total number of clocks within a clock domain does not exceed the capacity limit corresponding to that clock domain.

[0032] In one optional implementation, the clock resource allocation module is specifically used for:

[0033] Obtain the distance and layout parameters between clocks within each clock domain;

[0034] Based on the distance and layout parameters, a unique resource identifier is assigned to each clock, ensuring that the bounding boxes of clocks allocated to the same clock resource do not overlap, and that the clock resource of a clock does not exceed the range of its corresponding bounding box.

[0035] In one alternative implementation, the balanced tree construction module is specifically used for:

[0036] Identify the source node, target node, and branch nodes from the clock source;

[0037] Select the root node of the clock balance tree within the current clock's bounding box;

[0038] Starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes traversed in the path from the root node to any target node is equal.

[0039] In one alternative implementation, the routing module is specifically used for:

[0040] The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and after visiting the adjacent nodes, starts visiting from the adjacent nodes again until the root node of the clock balance tree is reached, thus obtaining the traversal path.

[0041] Based on the traversal access path, the target access path is obtained, realizing the routing from the clock source to the root node of the clock balance tree.

[0042] Thirdly, the present invention provides a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the FPGA clock layout and routing method of the first aspect or any corresponding embodiment described above.

[0043] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the FPGA clock placement and routing method of the first aspect or any corresponding embodiment thereof.

[0044] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the FPGA clock placement and routing method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a method flow for an FPGA clock placement and routing method according to an exemplary embodiment.

[0047] Figure 2 This is a detailed flowchart illustrating an FPGA clock placement and routing method according to an exemplary embodiment.

[0048] Figure 3 This is a schematic diagram illustrating the construction of a clock balance tree according to an exemplary embodiment.

[0049] Figure 4 This is a schematic diagram illustrating the construction of a clock source to a balanced tree route according to an exemplary embodiment.

[0050] Figure 5 This is a schematic diagram of the structure of an FPGA clock layout and routing system provided in an embodiment of this application.

[0051] Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] It should be understood that the term "instruction" mentioned in the embodiments of this application can be a direct instruction, an indirect instruction, or an indication of a relationship. For example, A instructing B can mean that A directly instructs B, such as B being able to obtain information through A; it can also mean that A indirectly instructs B, such as A instructing C, so B can obtain information through C; or it can mean that there is a relationship between A and B.

[0054] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0055] In the embodiments of this application, "predefined" can be achieved by pre-storing corresponding codes, tables or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method.

[0056] FPGA (Field Programmable Gate Array) is a programmable digital logic device that can be used to implement various complex digital logic functions. It includes a more complex clock architecture logic on top of its configurability, used for synchronous operation, timing control, performance optimization, and design simplification. However, the physical structure of the clock network in an FPGA is pre-fabricated and cannot be adjusted for different application scenarios. Generally, an FPGA device is divided into multiple clock domains, each containing limited clock resources. This means that the number of clocks allocated to each clock domain cannot exceed a preset value, which is far less than the total number of clocks an FPGA needs to provide. For high-utilization designs, as the design scale and complexity increase, FPGAs often need to support hundreds of clocks. Therefore, the clock architecture, under the constraint of additional clock limitations, further complicates placement and routing. Traditional FPGA placement and routing methods are increasingly unable to support large-scale clock structures. This makes it necessary to adopt new technologies to support the placement and routing of ultra-large-scale FPGA clocks.

[0057] Therefore, this invention provides an FPGA clock placement and routing method. By pre-allocating clock resources, it can support hundreds of clocks with limited clock routing resources, ensuring that resource congestion does not occur in the subsequent placement and routing process. Furthermore, the construction of the clock balancing tree in this embodiment further reduces clock skew while meeting the complex constraints of placement and routing, enhancing signal integrity, effectively reducing signal attenuation and interference during transmission, and improving overall system performance.

[0058] This embodiment provides an FPGA clock placement and routing method, which is applied to an FPGA device that includes multiple clock domains. The method flow is as follows: Figure 1 As shown, it includes the following steps.

[0059] S101. Narrow the bounding box of clocks within the clock domain until the number of clocks in each clock domain is valid.

[0060] During the FPGA clock placement phase, especially the global placement phase, clock resources often lack sufficient constraints, potentially causing the number of clocks in each clock domain to exceed its resource capacity. Therefore, it's necessary to narrow down the bounding box of clocks within each clock domain until the number of clocks in all clock domains is legal. Legality means ensuring that, given clock resources, the number of clocks in each clock domain does not exceed the resource capacity of that clock domain, and that placement and routing can effectively support these clocks.

[0061] S102. Allocate clock resources to clocks such that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of clocks do not exceed the range of their corresponding bounding boxes.

[0062] To avoid placement and routing resource conflicts caused by an excessive number of clocks, after legalizing the number of clocks, clock resources need to be allocated to ensure that there is no overlap between the bounding boxes of each clock and to prevent mutual interference in resource usage among clocks during placement and routing. Specifically, each clock is assigned a unique resource identifier based on its placement location to ensure that these resources do not conflict.

[0063] S103. After the clock resources are allocated, a clock balancing tree is built within the bounding box of each clock to ensure that the delay of each clock from the source to each destination node is the same.

[0064] Clock skew is a common problem in FPGA design, potentially leading to signal synchronization errors and even system instability. This embodiment addresses this issue by constructing an H-tree (clock balancing tree). An H-tree is a symmetrical and uniformly distributed tree structure that ensures equal clock delays from the clock source node to each sink node, reducing signal synchronization problems caused by clock skew. This structure ensures consistent clock signal transmission time, thereby optimizing system clock performance.

[0065] S104. Implement routing from the clock source to the root node of the clock balance tree through a routing algorithm.

[0066] In FPGA design, the clock source is typically located in the Clock Management Tile (CMT). The routing problem from the CMT to the root node of the clock balancing tree is a crucial aspect of clock tree design. Using routing algorithms ensures that the route from the clock source to the clock balancing tree is the shortest possible, thereby minimizing clock signal delay and avoiding additional skew and latency introduced by excessively long clock transmission paths.

[0067] The FPGA clock placement and routing method provided in this embodiment, through pre-allocation of clock resources, can support hundreds of clock scales with limited clock routing resources, ensuring that resource congestion will not occur in the subsequent placement and routing process. Furthermore, the construction of the clock balancing tree in this embodiment further reduces clock skew while meeting the complex constraints of placement and routing, enhancing signal integrity, effectively reducing signal attenuation and interference during transmission, and improving overall system performance.

[0068] To better illustrate the above embodiments, the steps described above will be explained in detail below, and the specific process is as follows: Figure 2 As shown.

[0069] Step S101, narrowing the bounding boxes of clocks within clock domains until the number of clocks in each clock domain is legal, involves the following steps: First, defining resource constraints within each clock domain, specifically the maximum number of clocks supported by each clock domain, i.e., the capacity of each clock domain. Then, the clock layout problem is transformed into a flow network problem, where the capacity of each clock source, clock network, and clock domain is considered as nodes and edges in the network. The capacity limit of each clock domain determines the maximum flow of each node. Next, an iterative method is used to adjust the bounding boxes of the clocks so that the number of clocks within a clock domain does not exceed its maximum supported value. In each iteration, the layout of clocks within the clock domain is adjusted according to flow allocation and constraints. Each adjustment attempts to narrow the bounding boxes of clock signals exceeding the clock domain's capacity until all clock domains meet the legality conditions. After several iterations, the number of clocks in the clock domains gradually becomes legal. At this point, it is determined whether the target state has been reached, i.e., the number of clocks in all clock domains no longer exceeds the capacity limit. If convergence is achieved, the iteration stops.

[0070] The above iterative algorithms can be iterative minimum cost flow-based algorithms, such as SPFA (Shortest Path Faster Algorithm), Successive Shortest Path Algorithm, or Cycle-Canceling Algorithm.

[0071] Step S102 involves assigning clock signals to different resources while ensuring that the layout of these clocks does not conflict, thereby avoiding interference from clock resource occupation. The placement and routing process can be viewed as a graph coloring problem. Each clock is considered a node in the graph, and the placement conflict between two clocks is considered an edge connection. If the bounding boxes of two clocks overlap, there is a conflict between them, and different resources should be assigned. The problem then becomes a graph coloring problem, where each clock node needs to be assigned a "color," with different colors representing different resources, ensuring that adjacent nodes (clocks) do not share the same resources. The specific process includes: first, detecting whether there are conflicts between clocks. Clock conflicts typically depend on their position in the layout, the size of their bounding boxes, distances, and the degree of interference between them. By calculating the distance between clocks and layout parameters, it is determined which clock signals need to be assigned different resource identifiers. Subsequently, a unique resource identifier (color) is assigned to each clock node, ensuring that no two adjacent nodes (i.e., clocks with conflicting layouts) have the same resource identifier.

[0072] The above allocation methods can employ graph-based allocation algorithms, such as greedy algorithms. These algorithms scan the nodes of the graph and select the smallest resource number for each node to ensure that adjacent nodes do not share the same resources. While this method may not find the optimal solution, it usually provides a close approximation. Backtracking algorithms try all possible resource allocations to find the optimal solution that satisfies the conditions. This method is more accurate but computationally expensive, making it suitable for small-scale layout problems. Heuristic algorithms, such as genetic algorithms or simulated annealing, use specific heuristic search strategies to find a better solution.

[0073] The basic idea of ​​the H-tree structure in step S103 is to select the root node of the clock balance tree within the bounding box of the current clock; starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes traversed in the path from the root node to any target node is equal. Specifically, the H-tree structure is a recursive tree structure that ensures that the length of each branch in each level is equal, thereby ensuring that the delay of the clock signal received by each target node is consistent. This can effectively reduce clock skew and improve the clock performance and system stability of FPGA design. The structure of the H-tree includes: the source node (Clock Source), which is usually the starting point of the clock signal and the root node of the H-tree; branch nodes that recursively divide the clock signal path, with each branch having the same length and characteristics to ensure that each target node receives an equal delay; and sink nodes, which are the nodes that finally receive the clock signal, usually the various modules or logic units within the FPGA.

[0074] The specific construction process of the above H-tree is as follows: Figure 3 As shown, the process includes: selecting a clock source as the root node, representing the starting point of the clock signal, from which all other nodes will receive the signal. The clock source signal is then distributed to two child nodes, which are branches of the clock signal. These two child nodes are then distributed to more distant child nodes, forming a recursive structure. The number of branch nodes at each level is equal, and the length of each branch path is also equal. This ensures that the path delay from all target nodes to the source node is equal, thereby reducing clock skew. During each distribution, symmetry between subtrees is ensured, guaranteeing that each node is at the same level and has the same propagation path length as other nodes. Recursion stops when a leaf node (sink node) is reached. Each leaf node is the final clock target node.

[0075] In practical design, constructing a clock tree requires consideration of not only symmetry but also optimization of physical parameters such as delay, power consumption, and routing resources. Optimization strategies can be employed to optimize the H-tree. For example, optimizing branch lengths reduces propagation delay differences between different paths, thereby minimizing clock skew. Optimizing the tree height balances the distance between all leaf nodes and the root node. In actual FPGA or IC designs, routing resources are limited. Therefore, selecting appropriate branch numbers and structures avoids an overly complex tree, reducing routing area. Optimizing different resistors and capacitors in the tree prevents asymmetry caused by excessive propagation delays at certain nodes. Optimizing each path in the H-tree ensures that the clock signal reaches each target node with the smallest possible propagation delay. A specific method is to use dynamic programming algorithms to calculate the shortest delay for each path, ensuring consistent signal arrival times. Finally, adjusting the tree hierarchy ensures that the length and load of each branch are as balanced as possible at each level, reducing delay differences between long and short paths.

[0076] In step S104, the routing design from the clock source to the root node of the clock balancing tree needs to consider not only the transmission distance of the clock signal but also ensure that the delay and skew of the clock signal are minimized. The routing algorithm finds the shortest path from the clock source to each target node, thereby reducing signal transmission delay. The specific process includes: starting with the clock source (CMT), adding it to the queue; traversing the nodes directly connected to the clock source layer by layer and adding these nodes to the queue; expanding the nodes according to the hierarchical structure, ensuring that each node is visited within the shortest path; and finally, finding the shortest path from the clock source to the root node of the clock balancing tree.

[0077] The routing algorithm described above can be a BFS-based algorithm, the process of which is as follows: Figure 4 As shown, the BFS algorithm is a graph traversal algorithm that visits all adjacent nodes level by level along the graph's hierarchical structure. Its core idea is to start from an initial node (source node), visit all nodes adjacent to the current node, and then sequentially visit unvisited adjacent nodes. Specifically, starting from the clock source node, a queue is initialized, the clock source node is added to the queue, and it is marked as visited. Nodes are sequentially removed from the queue, and all adjacent nodes (i.e., connected logical blocks, clock allocation resources, etc.) are checked. For each adjacent node, if it has not been visited, it is added to the queue, and its path is recorded. After all target nodes have been traversed, a clock tree can be constructed based on the recorded paths. This tree guarantees that the path from the clock source to each receiving node is the shortest.

[0078] In summary, the FPGA clock placement and routing method provided in this embodiment of the invention is applied to an FPGA device containing multiple clock domains. By narrowing the bounding boxes of clocks within each clock domain until the number of clocks in each domain is legal, the number of clocks within each clock domain is legalized, ensuring that the number of clocks in each clock domain does not exceed the resource carrying capacity of that clock domain, and that placement and routing can effectively support these clocks. After legalization, clock resources are allocated so that the bounding boxes of clocks allocated to the same clock resource do not overlap, and that the clock resources of a clock do not exceed the range of its corresponding bounding box, alleviating the placement and routing resource congestion problem caused by ultra-large-scale clocks. After clock resource allocation, a clock balancing tree is constructed within the bounding boxes of each clock, ensuring that the delay of each clock from the source to each destination node is the same, reducing signal synchronization problems caused by clock skew. Through this structure, the transmission time of clock signals can be kept consistent, effectively solving the clock skew problem in the FPGA placement and routing process, thereby optimizing the clock performance of the system. By implementing a routing algorithm to route the clock source to the root node of the clock balancing tree, the shortest possible path is ensured, thereby minimizing clock signal delay and avoiding additional skew and latency introduced by excessively long clock transmission paths. The FPGA clock placement and routing method provided by this invention, through pre-allocation of clock resources, can support hundreds of clock scales with limited clock routing resources, ensuring no resource congestion issues occur in subsequent placement and routing processes. Furthermore, the construction of the clock balancing tree in this embodiment further reduces clock skew while satisfying the complex constraints of placement and routing, enhancing signal integrity, effectively reducing signal attenuation and interference during transmission, and improving overall system performance.

[0079] This application also provides an FPGA clock placement and routing system for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0080] This application provides an FPGA clock placement and routing system. Figure 5 This is a schematic diagram of an FPGA clock placement and routing system provided in an embodiment of this application. The system is applied to an FPGA device, which includes multiple clock domains. The system includes:

[0081] The legalization module 501 is used to narrow down the bounding box of clocks within the clock domain until the number of clocks in each clock domain is legal.

[0082] The clock resource allocation module 502 is used to allocate clock resources to clocks so that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of clocks do not exceed the range of the corresponding bounding box.

[0083] The balanced tree construction module 503 is used to construct a clock balanced tree within the bounding box of each clock after the clock resources are allocated, so that the delay of each clock from the source to each destination node is the same.

[0084] The routing module 504 is used to implement routing from the clock source to the root node of the clock balance tree through a routing algorithm.

[0085] In one alternative implementation, the legalization module 501 is specifically used for:

[0086] Set capacity limits for each clock domain; these capacity limits characterize the maximum number of clocks in each clock domain.

[0087] An iterative method is used to adjust the bounding boxes of clocks within each clock domain, ensuring that the total number of clocks within a clock domain does not exceed the capacity limit corresponding to that clock domain.

[0088] In one optional implementation, the clock resource allocation module 502 is specifically used for:

[0089] Obtain the distance and layout parameters between clocks within each clock domain;

[0090] Based on the distance and layout parameters, a unique resource identifier is assigned to each clock, ensuring that the bounding boxes of clocks allocated to the same clock resource do not overlap, and that the clock resource of a clock does not exceed the range of its corresponding bounding box.

[0091] In one alternative implementation, the balanced tree construction module 503 is specifically used for:

[0092] Select the root node of the clock balance tree within the current clock's bounding box;

[0093] Starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes traversed in the path from the root node to any target node is equal.

[0094] In one alternative implementation, the routing module 504 is specifically used for:

[0095] The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and after visiting the adjacent nodes, starts visiting from the adjacent nodes again until the root node of the clock balance tree is reached, thus obtaining the traversal path.

[0096] Based on the traversal access path, the target access path is obtained, realizing the routing from the clock source to the root node of the clock balance tree.

[0097] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0098] In this embodiment, the FPGA clock layout and routing system is presented in the form of functional units. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0099] This invention also provides a computer device having the above-described features. Figure 5 The diagram shows the FPGA clock layout and routing system.

[0100] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 6 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0101] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0102] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0103] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0104] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0105] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0106] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0107] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0108] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. An FPGA clock placement and routing method, characterized in that, The method is applied to an FPGA device, the FPGA device comprising multiple clock domains, the method comprising: Narrow the bounding box of clocks within each clock domain until the number of clocks in each clock domain is legal; The clock resources of the clocks are allocated such that the bounding boxes of clocks allocated to the same clock resources do not overlap, and the clock resources of the clocks do not exceed the range of the corresponding bounding boxes. After the clock resources are allocated, a clock balancing tree is built within the bounding box of each clock to ensure that the delay of each clock from the source to each destination node is the same. A routing algorithm is used to route from the clock source to the root node of the clock balance tree; The allocation of clock resources includes: Obtain the distance and layout parameters between clocks within each clock domain; Based on the distance and layout parameters, a unique resource identifier is assigned to each clock, such that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resource of a clock does not exceed the range of its corresponding bounding box. The allocation of clock resources also includes: Treat each clock as a node in the graph, and connect two clocks with edges if there is a layout conflict between them. If the bounding boxes of two clocks overlap, there is a conflict between the two clocks, and different resources are allocated to them. Assign a color to each clock node, with different colors representing different resources, to ensure that adjacent nodes do not share the same resources.

2. The method according to claim 1, characterized in that, The process of narrowing the bounding box of clocks within each clock domain until the number of clocks in each clock domain is legal includes: Set capacity limits for each clock domain; the capacity limits are used to characterize the maximum number of clocks in each clock domain. An iterative method is used to adjust the bounding boxes of clocks within each clock domain, ensuring that the total number of clocks within a clock domain does not exceed the capacity limit corresponding to that clock domain.

3. The method according to claim 1, characterized in that, The construction of the clock balance tree within the bounding box of each clock includes: Select the root node of the clock balance tree within the current clock's bounding box; Starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes traversed in the path from the root node to any target node is equal.

4. The method according to claim 3, characterized in that, The routing algorithm implemented from the clock source to the root node of the clock balance tree includes: The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and after visiting the adjacent nodes, it starts visiting from the adjacent nodes until the root node of the clock balance tree is reached, thus obtaining the traversal path. Based on the traversal access path, the target access path is obtained, realizing the routing from the clock source to the root node of the clock balance tree.

5. An FPGA clock placement and routing system, characterized in that, The system is applied to an FPGA device, the FPGA device comprising multiple clock domains, and the system includes: The legalization module is used to narrow down the bounding box of clocks within a clock domain until the number of clocks in each clock domain is legal. The clock resource allocation module is used to allocate clock resources to clocks so that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resources of clocks do not exceed the range of the corresponding bounding box. The balanced tree construction module is used to build a clock balanced tree within the bounding box of each clock after clock resources are allocated, so that the delay of each clock from the source to each destination node is the same. The routing module is used to implement routing from the clock source to the root node of the clock balance tree through routing algorithms; Specifically, the clock resource allocation module is used for: Obtain the distance and layout parameters between clocks within each clock domain; Based on the distance and layout parameters, a unique resource identifier is assigned to each clock, such that the bounding boxes of clocks allocated to the same clock resource do not overlap, and the clock resource of a clock does not exceed the range of its corresponding bounding box. The clock resource allocation module is also used for: Treat each clock as a node in the graph, and connect two clocks with edges if there is a layout conflict between them. If the bounding boxes of two clocks overlap, there is a conflict between the two clocks, and different resources are allocated to them. Assign a color to each clock node, with different colors representing different resources, to ensure that adjacent nodes do not share the same resources.

6. The system according to claim 5, characterized in that, The legalization module is specifically used for: Set capacity limits for each clock domain; the capacity limits are used to characterize the maximum number of clocks in each clock domain. An iterative method is used to adjust the bounding boxes of clocks within each clock domain, ensuring that the total number of clocks within a clock domain does not exceed the capacity limit corresponding to that clock domain.

7. The system according to claim 5, characterized in that, The balanced tree construction module is specifically used for: Select the root node of the clock balance tree within the current clock's bounding box; Starting from the root node, branch nodes are expanded hierarchically until the target node within the bounding box is reached; wherein, the number of branch nodes traversed in the path from the root node to any target node is equal.

8. The system according to claim 7, characterized in that, The routing module is specifically used for: The routing algorithm starts from the current node of the clock source, visits the adjacent nodes of the current node, and after visiting the adjacent nodes, it starts visiting from the adjacent nodes until the root node of the clock balance tree is reached, thus obtaining the traversal path. Based on the traversal access path, the target access path is obtained, realizing the routing from the clock source to the root node of the clock balance tree.

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