A method and apparatus for detecting voids in surface mount resistance solder joints.

Abstract

This invention relates to the field of electronic manufacturing, and more specifically, to a method and apparatus for detecting voids in surface mount resistor solder joints. The key technical points are: S1. Setting a void rate upper limit in the production management system to evaluate whether the measured void rate is acceptable; S2. Training a segmentation network oriented towards voids in the soldering area using a self-supervised model; S3. Activating an X-ray source to rotate and scan the sample under the X-ray beam, and reconstructing a three-dimensional model of the surface mount resistor solder joint from multiple 2D images using a projection matching method; S4. Segmenting the solder joint area using the network oriented towards voids in the soldering area according to the three-dimensional model, obtaining the location and shape of the voids; S5. Performing volume calculation to obtain the total volume of the solder joint voids and the total volume of the solder joint voids, then dividing the total volume of the solder joint voids by the total volume of the solder joint to calculate the measured void rate; S6. Determining whether the measured void rate exceeds the void rate upper limit. The advantages of this invention are that it can clearly and intuitively display the internal structure of the tested object, has a strong ability to identify internal defects, and greatly reduces the number of training samples.

Description

Technical Field

[0001] This invention relates to the field of electronic manufacturing, and more specifically, to a method and apparatus for detecting voids in surface mount resistor solder joints. Background Technology

[0002] In recent years, many countries around the world have launched their own manufacturing industry upgrading plans, with Germany's Industry 4.0 being a prime example. In my country, manufacturing is not only a pillar industry of the national economy but also a major battleground for innovation and industrial upgrading. The electronics manufacturing sector is currently the most thoroughly globalized and market-driven field. Pursuing high technology and low costs is an inevitable trend in the development of the electronics industry. With the development of electronic information technology, electronic products have become an integral part of people's lives. Printed circuit boards (PCBs), as important components of electronic products, are developing towards higher efficiency and smaller size. Various defects are prone to occur during the surface mount process, and research on algorithms for detecting these defects has attracted a large number of researchers. Reflow soldering, due to its high soldering efficiency and easy temperature control, is widely used in surface mount technology. During the reflow soldering process of surface mount components, when the molten solder cools and solidifies, the gas generated in the solder that does not escape will be "frozen," forming voids. These voids reduce the mechanical strength of the solder joint, affecting its reliability and lifespan. In the quality standards of solder joints, voids play a decisive role in quality, especially in large-scale solder joints. From a heat transfer perspective, voids can lead to module malfunctions and even damage during normal operation. Therefore, detecting and evaluating void defects inside the solder joints of surface mount components is an essential step in actual production. As integrated circuit devices on PCBs become increasingly dense and miniaturized, manual inspection is not only costly but also inefficient and inaccurate.

[0003] To address the aforementioned issues, Chinese Patent CN114022464A discloses an adaptive detection algorithm for internal voids in surface mount resistor solder joints. The key technical points are: using 2D-X-Ray imaging to acquire internal images; proposing an adaptive partitioning strategy to divide the surface mount resistor image into regions; then using a shape-prior-based adaptive grayscale level set method for void detection in darker areas; and proposing an adaptive circular convolution kernel for void detection in brighter areas. Finally, employing a shape factor and average grayscale strategy, the algorithm achieves the detection of internal voids in surface mount resistor solder joints.

[0004] The above solution solves the problem of detecting voids inside surface mount resistor solder joints, but its imaging accuracy is low, it requires a large number of training samples, and it is very ineffective for the widely used double-sided reflow soldering boards, causing the images of the solder joints on both sides to overlap and become extremely difficult to distinguish. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a method and device for detecting voids in patch resistor solder joints, which has the advantages of clearly and intuitively displaying the internal structure of the object being tested, having a strong ability to identify internal defects, and reducing the number of training samples.

[0006] The above-mentioned technical objective of this invention is achieved through the following technical solution: a method for detecting voids in surface mount resistor solder joints.

[0007] S1. Set a maximum void ratio in the production management system to evaluate whether the measured void ratio is qualified.

[0008] S2. Train a segmentation network for the voids in the weld area using a self-supervised model;

[0009] S3. Start the X-ray source and rotate the sample under the X-ray beam. Reconstruct a three-dimensional model of the patch resistance solder joint from multiple 2D images using the projection matching method.

[0010] S4. Based on the three-dimensional model, the weld area is segmented using a network oriented towards weld area void segmentation to obtain the position and shape of the weld void;

[0011] S5. Perform volume calculation to obtain the total volume of solder joint voids and the total volume of solder joint voids. Then divide the total volume of solder joint voids by the total volume of the solder joint to calculate the measured void rate.

[0012] S6. Determine whether the measured void ratio exceeds the upper limit of the void ratio. In one embodiment, the self-supervised model is a model that uses an autoencoder as a self-supervised learning model, and establishes a compressed representation of the data through training data to regenerate the input data.

[0013] In one embodiment, the segmentation network is a U-Net network, which outputs a label image of the same size as the input image by mapping the X-ray image to the location of the hole in the welding area.

[0014] In one embodiment, the implementation steps of the projection matching method are as follows:

[0015] S301. Select the image whose ray direction differs the least from the normal vector of the reference image from multiple 2D projection images as the reference image, and match the other images to it in turn.

[0016] S302. Use the cross-projection matching algorithm to search for the position of the pixel with the best matching degree, thereby determining the matching relationship between images;

[0017] S303. By sequentially matching all images, a three-dimensional model of the patch resistor solder joint is obtained. In one embodiment, the step of obtaining the location and shape of the solder joint void further includes:

[0018] S401. Input the 3D model image block to be predicted into the trained U-net network to obtain a binary image with a gray value of 0 or 1.

[0019] S402. The binary image is processed using morphological processing to obtain the location and shape information of the solder joint void.

[0020] In one embodiment, the volume calculation step further includes:

[0021] S501. Import the 3D model of the weld joint into the finite element analysis software and use the software's volume measurement tool to calculate the total volume of the weld joint.

[0022] S502. Import the 3D model of the weld point into Unigraphics 3D modeling software for meshing to generate a 3D network model.

[0023] S503. Use the software's measurement tools to measure the height and diameter of the weld joint void;

[0024] S504. Calculate the volume of the weld joint cavity based on its height and diameter, and sum the calculated volumes of the weld joint cavities to obtain the total volume of the weld joint cavities.

[0025] In one embodiment, the void ratio is the ratio of the void volume of the solder joint to the total volume of the solder joint.

[0026] In one embodiment, the determination is made using visual inspection or microscopic methods.

[0027] According to another invention, a detection device for voids in patch resistance solder joints is provided. The detection device includes: an X-ray source, an image receiver, a stage, and a moving guide mechanism. The stage is disposed at the movable end of the moving guide mechanism. The X-ray source is disposed on one side of the stage, and the image receiver is disposed on the other side of the stage. The stage and the image receiver are disposed on the extension line of the emitting end of the X-ray source.

[0028] In one embodiment, the moving guide rail mechanism includes a gearbox, a servo motor, a screw, an encoder, and a controller.

[0029] This invention addresses the issues of requiring a large number of training samples and poor performance on double-sided reflow soldering boards by employing 3D-X-Ray. 3D-X-Ray provides high-density and rapid measurement points and images, and measures internal geometry and defect proportions. It utilizes a layered technique, focusing the beam onto any layer and projecting the corresponding image onto a rotating receiving surface. This results in highly clear images at intersection points, while images on other layers are eliminated. Therefore, independent imaging of solder joints on both sides of the board is possible. Because it clearly and intuitively displays the internal structure of the tested object and has a strong ability to identify internal defects, the number of training samples can be significantly reduced. Attached Figure Description

[0030] Figure 1 This is a structural diagram of the detection device based on the voids in the patch resistor solder joint in this invention;

[0031] Figure 2 This is a flowchart of the detection method in this invention.

[0032] In the diagram: 1. X-ray source; 2. Image receiver; 3. Stage; 4. Transfer guide mechanism. Detailed Implementation

[0033] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, unless otherwise explicitly specified.

[0036] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0038] A method for detecting voids in surface mount resistance solder joints, such as... Figure 2 As shown, it includes the following steps:

[0039] S1. A void rate upper limit is preset in the production management system (MES), which is used to evaluate whether the void rate of the solder joint is qualified.

[0040] S2. Train a segmentation network for the voids in the weld area using a self-supervised model;

[0041] In one example, an X-ray source is used to photograph the patch resistor solder joint to obtain an image of the area to be measured. After data acquisition, the acquired image data is sampled.

[0042] Specifically, an autoencoder is used as a self-supervised learning model. An autoencoder is a neural network consisting of an encoder and a decoder. Its purpose is to build a compressed representation of the data through training data and to regenerate the input data.

[0043] The segmentation network, a U-Net network, is trained using data labels obtained from a self-supervised model. This network maps X-ray images to holes one-to-one and outputs a label image of the same size as the input image. After training, the model is evaluated to determine its performance on the test set. If the performance is unsatisfactory, training parameters and the loss function can be adjusted to optimize the model.

[0044] S3. Start the X-ray source and rotate the sample under the X-ray beam to continuously acquire multiple 2D images. Process the acquired 2D images and reconstruct a three-dimensional model from the multiple 2D images using the projection matching method.

[0045] Specifically, the implementation steps of the projection matching method are as follows:

[0046] S301. Select the image whose ray direction differs the least from the normal vector of the reference image from multiple 2D projection images as the reference image, and match the other images to it in turn.

[0047] S302. Use the cross-projection matching algorithm to search for the position of the pixel with the best matching degree, thereby determining the matching relationship between images;

[0048] S303. By matching all images sequentially, a three-dimensional model of the patch resistor solder joint is obtained.

[0049] S4. Based on the three-dimensional model of the chip resistor solder joint, the solder joint area is segmented using a network oriented towards solder area void segmentation to obtain the location and shape of the solder joint void.

[0050] Specifically, the steps for obtaining the location and shape of solder joint voids also include:

[0051] S401. Input the 3D model image block to be predicted into the trained U-net network to obtain a binary image with a gray value of 0 or 1.

[0052] Furthermore, a grayscale value of 0 or 1 is used to indicate whether the pixel belongs to the solder joint area.

[0053] S402. The binary image is processed using morphological processing to obtain the location and shape information of the solder joint void.

[0054] S5. Perform volume calculation to obtain the total volume of solder joint voids and the total volume of solder joints. Then divide the total volume of solder joint voids by the total volume of solder joints to calculate the measured void rate.

[0055] Specifically, the volume calculation steps also include:

[0056] S501. Import the 3D model of the weld joint into the finite element analysis software and use the software's volume measurement tool to calculate the total volume of the weld joint.

[0057] S502. Import the 3D model of the weld point into Unigraphics 3D modeling software for meshing to generate a 3D network model.

[0058] S503. Use the software's measurement tools to measure the height and diameter of the weld joint void;

[0059] S504. Calculate the volume of the weld joint cavity based on its height and diameter, and sum the calculated volumes of the weld joint cavities to obtain the total volume of the weld joint cavities.

[0060] The height and diameter of the weld joint cavity can be measured, and the volume of the cavity can be calculated using the following formula:

[0061] V=(πd 2 / 4)×h

[0062] Where d is the diameter of the cavity, h is the height (depth) of the cavity, π is pi, and V is the volume of the cavity. The volume of the cavity can be calculated by substituting the measured diameter and height of the cavity into the formula. The calculated cavity volumes are then summed to obtain the total volume of the cavity. The void ratio is the ratio of the cavity volume to the total volume of the solder joint, which can be calculated using the above two steps.

[0063] S6. Use visual inspection or microscopic methods to judge and compare the void ratio;

[0064] Based on the above scheme, the measured void rate of the solder joint is compared with the preset upper limit of void rate. If the measured void rate of the solder joint is less than or equal to the limit, it is determined that the void rate of the solder joint meets the specification requirements. If the measured void rate exceeds the limit, it means that the void rate of the solder joint has exceeded the specification requirements and corresponding measures need to be taken for treatment or repair.

[0065] Based on the above scheme, in a complete operational example:

[0066] The production management system presets a void rate upper limit of 0.1%, which is used to evaluate whether the void rate of solder joints is acceptable. An X-ray source is used to image the surface mount resistor solder joints to obtain images of the area to be measured. An autoencoder is used as a self-supervised learning model. The data labels obtained from the self-supervised model are used to train a segmentation network. The segmentation network is a U-Net network that can map the X-ray image to the location of voids and output a label image of the same size as the input image.

[0067] An X-ray source was activated, and the sample was rotated and scanned under the X-ray beam to continuously acquire 300 2D images. These 2D images were then processed, and a 3D model was reconstructed from them using the projection matching method. The specific solution process for the projection matching method is as follows:

[0068] (1) First, acquire multiple images of 2D patch resistor solder joints, take them from the same viewpoint and at the same distance, and preprocess the images with median filtering to remove noise;

[0069] (2) Rotate each 2D image to the same pose according to the shooting viewpoint for matching. Use camera intrinsics and image coordinates to map 3D space to 2D image coordinates, and complete the mapping using software (MATLAB) and camera calibration tools;

[0070] (3) Then, using the cross-projection matching algorithm, the two images are forward-projected, backward-projected, and difference-rotated. The matching degree of the two images is compared, and the parameters such as translation, rotation, scaling, and distortion between the images are determined by maximizing the matching degree.

[0071] (4) Repeat step (3) to match all images, obtain the geometric transformation parameters between adjacent images, register the images, and transform them into images in the same coordinate system;

[0072] (5) Next, three-dimensional reconstruction is performed. The matched 2D images are superimposed and stereoscopic imaging technology is used to reconstruct the matched 2D images from different angles using the imaging principle to obtain three-dimensional volume data.

[0073] (6) Finally, the reconstructed three-dimensional volume data is post-processed to perform smoothing, noise reduction and repair to obtain the three-dimensional model of the patch resistance solder joint.

[0074] Next, based on the 3D model of the surface mount resistance solder joint, a network oriented towards solder area void segmentation is used to segment the solder joint region, obtaining the location and shape of the solder joint voids. The specific solution process of the void segmentation network using the U-net segmentation algorithm is as follows:

[0075] (1) Data preprocessing: First, the three-dimensional model of the patch resistance solder joint is cut into multiple three-dimensional image blocks. The size of each block is consistent with the size of the input layer of the U-net network, and the image blocks are converted into grayscale images.

[0076] (2) Constructing the U-net network: The U-net network is constructed using an encoder-decoder structure with convolutional layers, deconvolutional layers, and skip connections, so that the network can consider features at multiple scales at the same time and improve the segmentation effect.

[0077] (3) Training the model: The model is trained using the labeled solder joint area and non-solder joint area.

[0078] (4) Segmenting the solder joint region: The 3D model image block to be predicted is input into the trained U-net network to obtain the output result. The output result is a binary image with a grayscale value of 0 or 1, indicating whether the pixel belongs to the solder joint region. After binarization, the first step is to use a dilation-erosion method, implemented using the OpenCV function cv2.morphologyEx(). Dilation can fill small holes, making the solder joint more connected, while erosion can eliminate noise points, making the solder joint edges clearer. Next, the connected component algorithm is used to analyze the connected components of the binary image to find the connected regions of the solder joint holes, implemented using the OpenCV function cv2.connectedComponentsWithStats(), to obtain the position and size information of each hole. Finally, the shape and position information of each hole are extracted, and the contour extraction or fitting method is used, implemented using the OpenCV function cv2.findContours().

[0079] The volume of each solder joint void is calculated to obtain the total volume of the voids. Based on the 3D model of the surface mount resistor solder joint, the total volume of the solder joint is calculated, and the void ratio is calculated by dividing the total volume of the voids by the total volume of the solder joint. Solder joint total volume V1 calculation: The 3D model of the solder joint is imported into Finite Element Analysis (FEA) software, and the total volume of the solder joint is calculated using the software's volume measurement tool. Solder joint void total volume V2 calculation: The 3D model of the solder joint is imported into 3D modeling software (Unigraphics), meshed, and a 3D mesh model is generated. The height and diameter of the solder joint voids are measured using the software's measurement tool. Calculation of the measured void ratio:

[0080] The measured void rate of the weld joint is compared with the preset upper limit of void rate. If the measured void rate is less than or equal to the upper limit of void rate of 0.1%, it means that the void rate of the weld joint meets the requirements and the quality is good. If the measured void rate exceeds 0.1%, rework or replacement of welding materials is required to improve the quality of the weld joint.

[0081] like Figure 1 As shown, the present invention also provides a detection device for voids in patch resistance solder joints, which includes: an X-ray source 1, an image receiver 2, a stage 3, and a moving guide mechanism 4. The stage 3 is disposed at the movable end of the moving guide mechanism 4, the X-ray source 1 is disposed on one side of the stage 3, the image receiver 2 is disposed on the other side of the stage 3, and the stage 3 and the image receiver 2 are disposed on the extension line of the emitting end of the X-ray source 1.

[0082] Based on the above scheme, in one example:

[0083] The first step involves precisely labeling the images. The sampler of the digital image processing system samples the void and non-void regions in the image. An autoencoder is used as a self-supervised learning model. The data labels obtained from the self-supervised model are used to train the U-Net segmentation network. This enables the segmentation of voids in the weld area for images from different angles. Based on the positional relationship of voids in different layers on multi-angle images, the interference of voids in double-sided reflow soldering plates is eliminated, resulting in accurate segmentation results. A common welding imaging angle is along the weld axis. The U-Net segmentation network can accurately segment voids in the vicinity of the weld. Another imaging angle is the direction perpendicular to the weld axis. The U-Net segmentation network can more accurately segment voids and other areas around the weld, including the fusion zone and heat-affected zone on both sides of the weld.

[0084] The second step is to start X-ray source 1, so that the sample is rotated and scanned under the X-ray beam to continuously acquire multiple 2D images. The acquired 2D images are processed and reconstructed into a three-dimensional model by projection matching method.

[0085] The third step is to segment the solder joint area based on the three-dimensional model of the chip resistor solder joint, and obtain the location and shape of the solder joint voids by using a network oriented towards the segmentation of solder area voids.

[0086] The fourth step is to calculate the volume of each solder joint void to obtain the total volume of the void. The total volume of the solder joint is calculated based on the three-dimensional model of the chip resistor solder joint, and the void rate is calculated. Finally, the void rate is judged and compared by visual inspection or microscopic method to determine the qualification of each solder ball.

[0087] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for detecting a chip resistor joint cavity based on a chip resistor joint cavity, characterized in that, The method comprises the following steps: S1, presetting an upper limit of a cavity rate in a production management system for evaluating whether a measured cavity rate is qualified; S2, training a segmentation network for a welding area cavity through a self-supervised model; S3, starting an X-Ray source, rotating and scanning a sample under an X-Ray beam, and reconstructing multiple 2D images into a three-dimensional model of a patch resistance welding spot through a projection matching method; S4, segmenting a welding spot area using the network for welding area cavity segmentation according to the three-dimensional model to obtain a position and shape of a welding spot cavity; S5, performing volume calculation to obtain a total volume of the welding spot cavity and a total volume of the welding spot, and then dividing the total volume of the welding spot cavity by the total volume of the welding spot to calculate the measured cavity rate; S6, judging whether the measured cavity rate exceeds the upper limit of the cavity rate; The implementation steps of the projection matching method are as follows: S301, selecting an image with the smallest difference between a normal vector of a reference image and a ray direction from multiple 2D projection images as the reference image, and sequentially matching other images with the reference image; S302, selecting a cross projection matching algorithm to search for a pixel point position with the best matching degree to determine the matching relationship between images; S303, obtaining a three-dimensional model of the patch resistance welding spot by sequentially matching all images; The step of obtaining the position and shape of the welding spot cavity further comprises: S401, inputting a three-dimensional model image block to be predicted into a trained U-net network to obtain a binary image with a gray value of 0 or 1; S402, processing the binary image using morphological processing to obtain position and shape information of the welding spot cavity.

2. The method for detecting a chip resistor welding point cavity according to claim 1, characterized in that: The self-supervised model is a model using an autoencoder as a self-supervised learning model, which establishes a compressed representation of data through training data to regenerate input data.

3. The method for detecting a chip resistor joint hole based on the chip resistor joint hole according to claim 1, characterized in that: The segmentation network is a U-Net network, which outputs a label image with the same size as the input image by one-to-one correspondence between the X-ray image and the position of the welding area cavity.

4. The method for detecting a chip resistor joint hole based on the chip resistor joint hole according to claim 1, characterized in that, The step of volume calculation further comprises: S501, importing the welding spot three-dimensional model into a finite element analysis software to calculate the total volume of the welding spot using the volume measurement tool of the software; S502, importing the welding spot three-dimensional model into Unigraphics three-dimensional modeling software for meshing processing to generate a three-dimensional network model; S503, measuring the height and diameter size of the welding spot cavity using the measurement tool of the software; S504, calculating the welding spot cavity volume according to the height and diameter size of the welding spot cavity, and accumulating the calculated welding spot cavity volume to obtain the total volume of the welding spot cavity.

5. The method for detecting a chip resistor joint hole based on the chip resistor joint hole according to claim 1, characterized in that: The cavity rate is the ratio of the welding spot cavity volume to the total volume of the welding spot.

6. The method of claim 1, wherein: The judgment is made using visual observation or a microscope method.

7. A device for detecting a chip resistor joint cavity based on the detection of a chip resistor joint cavity, for implementing the method for detecting a chip resistor joint cavity based on the detection of a chip resistor joint cavity according to any one of claims 1-6, characterized in that: The device comprises an X-Ray source, an image receiver, a sample stage, and a moving guide rail mechanism, the sample stage is arranged at the movable end of the moving guide rail mechanism, the X-Ray source is arranged at one side of the sample stage, the image receiver is arranged at the other side of the sample stage, and the sample stage and the image receiver are arranged on the extension line of the emission end of the X-Ray source.

8. The apparatus for detecting a chip resistor joint hole based on a chip resistor joint according to claim 7, wherein: The mobile guide rail mechanism comprises a gearbox, a servo motor, a screw rod, an encoder and a controller. The mobile guide rail mechanism comprises a gearbox, a servo motor, a screw rod, an encoder and a controller.

Images