Synchronous triggering system and method, quantum control system

Abstract

The application discloses a synchronous triggering system and method and a quantum control system, and the synchronous triggering system comprises a central control device, a plurality of routing board cards and a plurality of function board cards, and the synchronization triggering of a triggering signal is ensured through a three-stage triggering synchronization system, wherein the first stage provides a plurality of groups of triggering signals for the corresponding routing board cards for the central control device, and the initial time of the output of each group of triggering signals is adjusted so that the time when each cabinet receives the triggering signal is the same; the second stage is that the communication lines from each routing board card to the plurality of function board cards connected thereto are equal in length; and the third stage is that the triggering signals reach the plurality of data processing devices at the same time after the AND operation processing of the AND gate chips so as to synchronously trigger the data processing devices.

Description

Technical Field

[0001] This invention relates to the field of quantum measurement and control technology, and in particular to a synchronous triggering system and method, and a quantum control system. Background Technology

[0002] Quantum chips are the core components for running quantum computing. A quantum chip integrates multiple qubits. To ensure the normal operation of these qubits, a dedicated quantum control system is needed. Within this system, multiple signal modules provide various control signals to each qubit, such as frequency control signals and quantum state control signals. Furthermore, the results of the quantum computation completed by the qubits need to be acquired through a data acquisition module. With technological advancements, the number of qubits on quantum chips has increased to hundreds, thousands, or even tens of thousands. Consequently, the number of functional modules within the quantum control system also increases, and the signal routing becomes increasingly complex. When running quantum computing tasks on a quantum chip, it is difficult to guarantee complete synchronization of triggering when multiple functional modules manipulate, measure, and read the data from several qubits performing the same task. This significantly reduces the accuracy of the task results.

[0003] Therefore, how to achieve synchronous triggering during the manipulation, measurement, and readout of each quantum bit is a technical problem that urgently needs to be solved in this field.

[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a synchronous triggering system and method, and a quantum control system, for realizing synchronous triggering during the manipulation, measurement and reading operations of each quantum bit.

[0006] To achieve the above objectives, the present invention proposes a synchronous triggering system, comprising:

[0007] The central control device connects to several routing boards and provides several sets of trigger signals to the corresponding routing boards. It adjusts the initial time of each set of trigger signal outputs so that each chassis receives the trigger signal at the same time.

[0008] A plurality of routing boards, each of which is connected to a plurality of functional boards, wherein the communication lines from each routing board to the connected functional boards are of equal length, and the routing boards are used to forward the trigger signal to the functional boards;

[0009] Several functional boards, each of which has an AND gate chip and several data processing devices, wherein the trigger signal is processed by the AND operation of the AND gate chip and then simultaneously reaches the several data processing devices to synchronously trigger the data processing devices.

[0010] Optionally, the synchronization triggering system further includes:

[0011] A reference clock is used to provide a reference clock signal to the central control device and the routing board.

[0012] Optionally, the reference clock is also used to provide a reference clock signal to the functional board.

[0013] Optionally, the number of central control devices is at least two, and at least two central control devices operate based on the same reference clock signal of the reference clock.

[0014] Optionally, the routing board is used to output a feedback signal to the central control device based on the trigger signal;

[0015] The central control device is also used to acquire a first time set, wherein the first time set is the time set consumed from the output of the trigger signal by the central control device to the receipt of the feedback signals from each of the routing boards by the central control device;

[0016] The central control device is also used to calibrate the initial time of the trigger signal sent by the central control device to each of the routing boards based on the first time set when the elements in the first time set are not completely equal.

[0017] Optionally, each of the routing boards and several of the functional boards connected to the routing boards are housed in the same chassis, with the routing boards located in the middle of the chassis and the functional boards located on both sides of the routing boards.

[0018] Optionally, the functional board further includes a board body, wherein the AND gate chip and several data processing devices are all disposed on the board body.

[0019] Optionally, each of the data processing devices is communicatively connected to several functional devices, which are used to perform corresponding actions according to the instructions of the data processing device.

[0020] Based on the same inventive concept, this invention also proposes a synchronous triggering method, comprising:

[0021] The central control device provides several sets of trigger signals to the corresponding routing boards, and adjusts the initial time of each set of trigger signal outputs so that each chassis receives the trigger signal at the same time. The central control device is connected to several routing boards.

[0022] The routing board forwards the trigger signal to the AND gate chip of the function board, wherein each routing board is connected to several function boards, and the communication lines from each routing board to the connected several function boards are of equal length;

[0023] The trigger signal, after being processed by the AND operation of the AND gate chip, simultaneously reaches several data processing devices to synchronously trigger the data processing devices. The functional board includes the AND gate chip and several data processing devices.

[0024] Based on the same inventive concept, the present invention also proposes a quantum control system, including the synchronous triggering system described in any of the above-described features.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The synchronous triggering system proposed in this invention includes a central control device, several routing boards, and several functional boards. A three-level synchronous triggering system ensures synchronous triggering of trigger signals. The first level provides several sets of trigger signals to the corresponding routing boards from the central control device, adjusting the initial output time of each set of trigger signals to ensure that each chassis receives the trigger signal at the same time. The second level ensures that the communication lines from each routing board to the connected functional boards are of equal length. The third level ensures that the trigger signals, after being processed by an AND gate chip, simultaneously reach the several data processing devices to synchronously trigger them. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a synchronous triggering system proposed in an embodiment of this application;

[0028] Figure 2 for Figure 1 Structural diagram of the central control equipment;

[0029] Figure 3 This is a flowchart illustrating a synchronization triggering method according to another embodiment of this application;

[0030] Among them, 100-central control equipment, 200-routing board, 300-functional board, 301-AND gate chip, 302-data processing device, 303-functional device, and 400-reference clock. Detailed Implementation

[0031] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0032] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0034] Most existing quantum computers employ a combination of a host computer, a quantum control system, and quantum chips to perform quantum computing tasks. Typically, the host computer receives the user's quantum computing task, processes it, and forms a quantum circuit. This quantum circuit is then mapped onto the topology of the corresponding quantum chip. The quantum circuit contains the quantum logic gates required for the task, the measurement operations for the final quantum computing result, and the timing sequence of each operation. Upon receiving this information from the quantum circuit, the quantum control system translates it into corresponding instructions to enable the relevant hardware devices to operate and complete the quantum computing task.

[0035] Generally, a quantum chip contains multiple qubits (also called quantum bits) and data transmission lines. Each qubit includes a detector and a qubit device coupled together. The qubit device can be an artificial superconducting qubit constructed using a superconducting Josephson junction and capacitance to ground, and the detector can be a resonant cavity. The qubit device has a first control signal line and a second control signal line, and the detector coupled to the qubit device has a third control signal line. The first control signal line transmits quantum state control signals to regulate the quantum state information of the qubit device; the second control signal line transmits frequency control signals to regulate the frequency parameters of the qubit device; and the third control signal line transmits both measurement signals for reading from the detector and outputs the readback signals returned by the detector, thus achieving indirect reading and measurement of the qubit device's state. Therefore, the quantum control system used for qubit manipulation and measurement in the quantum chip needs to generate and output three control signals, respectively, to the first to third control signal lines to achieve the manipulation and measurement of the qubits in the quantum chip.

[0036] In practical applications, the applicant discovered that because the quantum logic gates involved in quantum computing tasks need to be completed before the corresponding qubits decohere, the precision requirements for control signals are very high when quantum chips are used to process quantum computing tasks. When executing quantum computing tasks, it is often necessary to simultaneously control or read out multiple qubits, which requires ensuring that the signals output by the quantum control system to multiple qubits can be triggered synchronously.

[0037] Based on the above findings, in order to ensure that signals sent to multiple qubits can be triggered synchronously, embodiments of this application provide a synchronization triggering system, please refer to... Figure 1 The system includes: a central control device 100 connected to several routing boards 200, used to provide several sets of trigger signals to the corresponding routing boards 200, and to adjust the initial time of each set of trigger signal output so that the time when each chassis receives the trigger signal is the same. Several routing boards 200, each routing board 200 connected to several function boards 300, with equal-length communication lines from each routing board 200 to the connected function boards 300, the routing boards 200 used to forward the trigger signals to the function boards 300. Several function boards 300, each function board 300 having an AND gate chip 301 and several data processing devices 302, the trigger signals being processed by the AND operation of the AND gate chip 301 and then simultaneously arriving at the several data processing devices 302 to synchronously trigger the data processing devices 302.

[0038] Unlike existing technologies, the synchronous triggering system proposed in this embodiment includes a central control device 100, several routing boards 200, and several functional boards 300. A three-level synchronous triggering system ensures the synchronous triggering of trigger signals. The first level involves the central control device 100 providing several sets of trigger signals to the corresponding routing boards 200, adjusting the initial output time of each set of trigger signals to ensure that each chassis receives the trigger signal at the same time. The second level involves the communication lines from each routing board 200 to the connected functional boards 300 being of equal length. The third level involves the trigger signals being processed by the AND operation of the AND gate chip 301 and simultaneously reaching the several data processing devices 302 to synchronously trigger the data processing devices 302.

[0039] For further information, please continue to refer to [link / reference]. Figure 1 Since the hardware devices need to work according to a certain timing sequence, in order to make the hardware devices in the synchronous triggering system work according to the same clock, the synchronous triggering system also includes a reference clock 400. The reference clock 400 is used to provide a reference clock 400 signal to the central control device 100 and the routing board 200. The reference clock 400 is also used to provide a reference clock 400 signal to the function board 300.

[0040] It should be noted that the reference clock 400 proposed in this embodiment can be an atomic clock, a highly accurate timing device. There are various types of atomic clocks, such as cesium atomic clocks, hydrogen atomic clocks, rubidium atomic clocks, and CPT atomic clocks. In this embodiment, the reference clock 400 is preferably a rubidium atomic clock. In other embodiments, other types of atomic clocks can be selected; there are no restrictions, and the choice can be made according to actual needs. Furthermore, the data processing device 302 is a device with data forwarding and processing functions, and can generally be an FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit), MPU (Microprocessor Unit), or DSP (Digital Signal Processor). In this embodiment, the data processing device 302 is preferably an FPGA; in other embodiments, other devices with similar data processing functions can be selected; there are no restrictions. The central control device 100 is an intelligent device with data processing capabilities, such as an FPGA, MCU, MPU, or DSP. In this embodiment, the central control device 100 is preferably an FPGA.

[0041] Those skilled in the art will understand that the interfaces that any hardware device can provide are always limited. It is foreseeable that after the successful development of large-scale or ultra-large-scale quantum chips in the future, the number of qubits that need to be controlled will increase exponentially. At this time, the synchronous triggering system needs to ensure the synchronous triggering of a large number of qubits. The synchronous triggering system proposed in this application can meet the needs of large-scale quantum chips to a certain extent. We only need to extend the structure proposed above, specifically by increasing the number of central control devices 100, and all of the central control devices 100 operate based on the same reference clock 400 signal. Of course, since the number of channels of the reference clock 400 is also limited, when the number of channels of one reference clock 400 is insufficient, multiple reference clocks 400 can be used to jointly provide the reference clock 400 signal. One reference clock 400 serves as the master clock, and all the other reference clocks 400 serve as slave clocks. The master clock is used to provide the reference clock 400 to all slave clocks, and the slave clocks are used to provide the reference clock 400 signal to the hardware in the synchronous triggering system. This can be understood as the horizontal extension of the synchronous triggering system proposed in this application. Furthermore, the synchronization triggering system proposed in this application can be vertically expanded. Specifically, in this embodiment, the central control device can be an intelligent device with data processing capabilities. When dealing with the synchronization triggering of a large number of qubits, the central control device can also be composed of an intelligent device with data processing capabilities connected to several router devices. Please refer to [reference needed]. Figure 2 The router component connects to several routing boards, and this structure can also meet the synchronous triggering requirements of a large number of qubits. It should be noted that the above is only an illustrative example; besides the above solution, there are many other similar solutions, which will not be elaborated here. The specific solution for large-scale quantum chips can be selected according to actual needs.

[0042] Furthermore, in the first-level synchronization of the synchronous triggering system, the central control device 100 calibrates the initial transmission time of the trigger signal sent by the routing board 200. Specifically, the routing board 200 is used to output a feedback signal to the central control device 100 based on the trigger signal. The central control device 100 is also used to acquire a first time set, wherein the first time set is the set of time consumed from the output of the trigger signal by the central control device 100 to the receipt of the feedback signals from each of the routing boards 200. The central control device 100 is also used to calibrate the initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 based on the first time set when the elements in the first time set are not completely equal.

[0043] The synchronous triggering system proposed in this embodiment involves a central control device 100 outputting a trigger signal to multiple routing boards 200 based on a reference clock 400 signal. The multiple routing boards 200 output feedback signals based on the reference clock 400 signal and the trigger signal, respectively, to obtain a first time set. When the elements in the first time set are not completely equal, the initial time of the trigger signal sent by the central control device 100 to each routing board 200 is calibrated based on the first time set. This calibration process effectively achieves trigger synchronization. Furthermore, by providing a reference clock 400 signal to both the central control device 100 and the routing boards 200 using the same reference clock 400, all devices in the quantum control system can perform related actions in the same timing sequence, further ensuring the accuracy of the calibration process and reducing the difficulty of ensuring synchronous calibration of the quantum control system.

[0044] All routing boards 200 synchronize using the reference clock 400 signal as a reference. If a routing board 200 immediately returns the feedback signal upon receiving the trigger signal, it could lead to clock timing disorder. Since the routing board 200 operates according to a specific timing sequence, it needs to process the received information for a period of time upon receiving the trigger signal. For example, assuming the routing board 200 is set to trigger operation on the rising edge of the clock sequence, if it receives the trigger signal on the falling edge, and immediately returns the signal, the signal returned to the central control device 100 will inevitably be incorrect because the routing board 200 has not actually received the trigger signal. This ultimately results in inaccurate trigger synchronization calibration for the quantum control system. The applicant proposes that all routing boards 200 wait for a certain clock cycle after receiving the trigger signal before returning the feedback signal, which effectively solves the above problem.

[0045] Based on the above concept, the plurality of routing boards 200 output feedback signals based on the reference clock 400 signal and the trigger signal respectively. After receiving the trigger signal, the plurality of routing boards 200 wait for a second time before outputting feedback signals based on the reference clock 400 signal respectively.

[0046] In this embodiment, the second time can be a plurality of clock cycles of the reference clock 400.

[0047] Since the trigger synchronization accuracy achieved by relying on only one calibration process may not meet the needs of quantum computing, in order to improve the trigger synchronization accuracy, the applicant proposes the following scheme: based on the initial time after calibration, the central control device 100 returns to output a trigger signal to multiple routing boards 200 according to the reference clock 400 signal and the set initial time, until all elements in the first time set are equal.

[0048] The scheme for adjusting the initial time of the trigger signals sent by the central control device 100 to each of the routing boards 200 using the first time set can be selected according to actual needs. In this embodiment, three preferred schemes are provided for selection. The three schemes proposed in this embodiment are preferred implementation schemes. In actual applications, other schemes can also be selected, which will not be elaborated here. The following describes these three preferred schemes in detail:

[0049] The first option is:

[0050] Based on the first time set, a third time set is obtained, wherein the third time set is the set of time consumed from the output of the trigger signal by the central control device 100 to the receipt of the trigger signal by each of the routing boards 200;

[0051] The longest time in the third time set is taken as the fourth time.

[0052] The initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 is adjusted based on the fourth time adjustment.

[0053] Specifically, the routing board 200 corresponding to the fourth time is the first routing board 200; the initial time for adjusting the trigger signal sent by the central control device 100 to each routing board 200 based on the fourth time may include:

[0054] The initial time of the trigger signal output by the central control device 100 to all routing boards 200 except the first routing board 200 is delayed, so that the trigger signal output by the central control device 100 arrives at each of the routing boards 200 at the same time.

[0055] The second option is:

[0056] Based on the first time set, a third time set is obtained, wherein the third time set is the set of time consumed from the output of the trigger signal by the central control device 100 to the receipt of the trigger signal by each of the routing boards 200;

[0057] The shortest time in the third time set is taken as the fifth time.

[0058] The initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 is adjusted based on the fifth time.

[0059] Specifically, the routing board 200 corresponding to the fifth time is the second routing board 200; the initial time for adjusting the trigger signal sent by the central control device 100 to each routing board 200 based on the fifth time may include:

[0060] The central control device 100 outputs the trigger signal to all routing boards 200 except the second routing board 200 at the initial time, so that the trigger signal output by the central control device 100 arrives at each routing board 200 at the same time.

[0061] The third option is:

[0062] Based on the first time set, a third time set is obtained, wherein the third time set is the set of time consumed from the output of the trigger signal by the central control device 100 to the receipt of the trigger signal by each of the routing boards 200;

[0063] The selected third routing board 200 in the third time set corresponds to the sixth time.

[0064] The initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 is adjusted based on the sixth time.

[0065] Specifically, the initial time for adjusting the trigger signal sent by the central control device 100 to each of the routing boards 200 based on the sixth time may include:

[0066] The central control device 100 outputs the trigger signal to all routing boards 200 except the third routing board 200 at the initial time, and performs delayed transmission processing or advanced transmission processing to ensure that the trigger signal output by the central control device 100 arrives at each of the routing boards 200 at the same time.

[0067] In this embodiment, each element in the third time set is obtained using the following formula:

[0068] t = T / 2;

[0069] Where t is the time consumed from the output of the trigger signal by the central control device 100 to the receipt of the trigger signal by one of the routing boards 200, and T is determined based on the elements in the first time set. It should be noted that if multiple routing boards 200 receive the trigger signal and all wait for the second time, then T = T1 - t2, where T1 is an element in the first time set and t2 is the second time. If multiple routing boards 200 receive the trigger signal without waiting for the second time, then T = T1.

[0070] Those skilled in the art should understand that, in addition to the three schemes described above, there may be other similar schemes. The choice of which scheme to use in a specific practical application can be adjusted as needed, and no restrictions are imposed here.

[0071] Furthermore, the trigger signal mentioned in the above three schemes is the signal used in the calibration process. It can be the signal used in the actual application of quantum computing. However, in order to ensure that the trigger synchronization calibration accuracy of the quantum control system is high enough, the trigger signal mentioned in the above three schemes may not be the signal used in the actual application of quantum computing. In particular, the frequency of the trigger signal is higher than the frequency of the signal used in the actual application of quantum computing. For example, if the frequency of the signal used in the actual application of quantum computing is 1MHz, then the frequency of the trigger signal can be set to 10MHz.

[0072] Furthermore, in the second-level synchronization of the synchronous triggering system, each of the routing boards 200 and several of the functional boards 300 connected to the routing boards 200 are arranged in the same chassis. The routing boards 200 are arranged in the middle of the chassis, and the several functional boards 300 are arranged on both sides of the routing boards 200.

[0073] Furthermore, in the third-level synchronization of the synchronous triggering system, the functional board 300 also includes a board body, wherein the AND gate chip 301 and several data processing devices 302 are all disposed on the board body.

[0074] Those skilled in the art will understand that, in this embodiment, the function of the functional device 303 is to generate various signals required for manipulating, measuring, and reading qubits. These signals are typically ADCs or DACs. ADCs are used to acquire information from the resonant cavity, while DACs are used to generate quantum state control signals for quantum state information manipulation or frequency control signals for frequency parameter manipulation. For example, in practical applications, when performing quantum computing using a quantum chip, corresponding operations need to be performed on the corresponding qubits. Suppose that quantum state information manipulation of the qubits is required, and the precision of the qubit control signal is very high. Sometimes, multiple qubits need to be manipulated simultaneously. Therefore, we often need multiple DACs to simultaneously perform corresponding actions to generate the corresponding control signals. This requires the corresponding trigger signals to simultaneously trigger the corresponding functional device 303 to generate the required control signals and output them to the corresponding qubits in the quantum chip. The functional board 300 proposed in this embodiment can effectively ensure that the trigger signals sent to multiple DACs synchronously trigger their corresponding data processing devices 302 to achieve synchronous triggering of multiple DACs, ultimately improving the precision of quantum computing running on the quantum chip.

[0075] Furthermore, each of the data processing devices 302 is communicatively connected to several functional devices 303, which are used to execute corresponding actions according to the instructions of the data processing devices 302. It should be noted that... Figure 1 This is merely an illustrative example and should not be construed as limiting the scope of this application. Figure 1 Each data processing device 302 is connected to only one functional device 303. In practical applications, each data processing device 302 can be connected to multiple functional devices 303, which is not limited here. In this embodiment, each data processing device 302 is preferably connected to four functional devices 303. In specific applications, this can be understood as four ADCs or four DACs connected to each FPGA. Those skilled in the art should understand that in other embodiments, each data processing device 302 can also be connected to other numbers of functional devices 303, which is not limited here and can be adjusted according to actual needs. In addition, the AND gate chip 301 is placed close to two adjacent FPGAs, and the output of the high-speed AND gate chip 301 is distributed to the two FPGAs with strict equal-length control of the shortest path.

[0076] Please continue to refer to this. Figure 1 By connecting multiple data processing devices 302 to the AND gate chip 301, the needs of large-scale quantum chips can be met. Furthermore, since the triggering of multiple data processing devices 302 within a single functional board 300 needs to be fully synchronized, the structure of the AND gate chip 301 can also ensure that multiple trigger signals arrive at the corresponding data processing device 302 simultaneously.

[0077] In this embodiment of the invention, each of the data processing devices 302 requires a trigger signal. Therefore, in order to ensure that each of the data processing devices 302 has a trigger signal, the number of data processing devices 302 is equal to the number of input terminals of the AND gate chip 301.

[0078] It should be noted that the data processing device 302 is a device with data forwarding and processing functions, and can generally be an FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit), MPU (Microprocessor Unit), or DSP (Digital Signal Processor). In this embodiment, the data processing device 302 is preferably an FPGA, but other devices with similar data processing functions can be used in other embodiments, and there are no restrictions here.

[0079] Those skilled in the art will understand that the functional board 300 requires a corresponding functional device 303 to achieve the corresponding function. For example, a device with analog-to-digital conversion (ADC) function is needed to perform ADC conversion, and a device with digital-to-analog conversion (DAC) function is needed to perform digital-to-analog conversion. The device with ADC function can be implemented using a pure circuit structure or an AD chip (i.e., an ADC). Similarly, the device with DAC function can be implemented using a pure circuit structure or a DA chip (i.e., a DAC). In this embodiment, the functional device 303 is preferably an ADC or a DAC.

[0080] In addition, in this embodiment, the AND gate chip 301 can be selected according to actual needs, and may include, but is not limited to, HMC746, 7408TTL, 7409TTL, 74X11, 74X21, CD4081, CD4082, etc., without limitation.

[0081] Specifically, the main body of the board can be a PCB (Printed Circuit Board), and the data processing device 302, the AND gate chip 301, and the functional device 303 are all disposed on the PCB.

[0082] In this embodiment, the AND gate chip 301 and the functional device 303 are preferably connected via traces on the top signal layer of the PCB board, and the AND gate chip 301 and the data processing device 302 are connected via traces on the top signal layer of the PCB board. When using top signal layer traces, one side of the transmission line is a dielectric and the other side is air, resulting in a lower equivalent dielectric constant than the intermediate layers and a smaller transmission line delay. This characteristic allows for faster signal transmission speeds on the top signal layer, making it suitable for routing high-speed signals such as 2.5GHz or 3.125GHz. When routing high-speed signals, avoid vias as much as possible. If vias are absolutely necessary, they can be drilled from the top layer to the bottom layer, or from the bottom layer to the top signal layer. There is no stub effect associated with vias, a feature not present in inner layer routing.

[0083] Those skilled in the art should understand that, in addition to the components listed in this embodiment, the functional board 300 also has some peripheral circuits or devices. For example, the functional board 300 also includes a communication interface, which is disposed on the board body and connected to the data processing device 302. There are also some other devices, which are not listed here.

[0084] Please refer to Figure 3 Based on the same inventive concept, this application also proposes a synchronous triggering method, including:

[0085] S10: The central control device provides several sets of trigger signals to the corresponding routing boards, and adjusts the initial time of each set of trigger signal output so that the time when each chassis receives the trigger signal is the same, wherein the central control device is connected to several routing boards;

[0086] S20: The routing board forwards the trigger signal to the AND gate chip of the function board, wherein each routing board is connected to several function boards, and the communication lines from each routing board to the connected several function boards are of equal length;

[0087] S30: The trigger signal is processed by the AND operation of the AND gate chip and simultaneously reaches several data processing devices to synchronously trigger the data processing devices, wherein the function board has the AND gate chip and several data processing devices.

[0088] Based on the same inventive concept, embodiments of this application also propose a quantum control system, including the synchronous triggering system described in any of the above-described features.

[0089] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0090] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A synchronous triggering system, characterized in that, include: The central control device connects to several routing boards and provides several sets of trigger signals to the corresponding routing boards. It adjusts the initial time of each set of trigger signal outputs so that each chassis receives the trigger signal at the same time. A plurality of routing boards, each of which is connected to a plurality of functional boards, wherein the communication lines from each routing board to the connected functional boards are of equal length, and the routing boards are used to forward the trigger signal to the functional boards; Several functional boards, each of which has an AND gate chip and several data processing devices, wherein the trigger signal is processed by the AND operation of the AND gate chip and then simultaneously reaches the several data processing devices to synchronously trigger the data processing devices.

2. The synchronous triggering system as described in claim 1, characterized in that, The synchronization triggering system also includes: A reference clock is used to provide a reference clock signal to the central control device and the routing board.

3. The synchronous triggering system as described in claim 2, characterized in that, The reference clock is also used to provide a reference clock signal to the functional board.

4. The synchronous triggering system as described in claim 2, characterized in that, The number of central control devices is at least two, and at least two central control devices operate based on the same reference clock signal of the reference clock.

5. The synchronous triggering system as described in claim 1, characterized in that, The routing board is used to output a feedback signal to the central control device based on the trigger signal; The central control device is also used to acquire a first time set, wherein the first time set is the time set consumed from the output of the trigger signal by the central control device to the receipt of the feedback signals from each of the routing boards by the central control device; The central control device is also used to calibrate the initial time of the trigger signal sent by the central control device to each of the routing boards based on the first time set when the elements in the first time set are not completely equal.

6. The synchronous triggering system as described in claim 1, characterized in that, Each of the routing boards and several of the functional boards connected to the routing boards are housed in the same chassis. The routing boards are located in the middle of the chassis, and the functional boards are located on both sides of the routing boards.

7. The synchronous triggering system as described in claim 1, characterized in that, The functional board also includes a board body, wherein the AND gate chip and several data processing devices are all disposed on the board body.

8. The synchronous triggering system as described in claim 7, characterized in that, Each of the data processing devices is communicatively connected to several functional devices, which are used to perform corresponding actions according to the instructions of the data processing device.

9. A synchronous triggering method, characterized in that, include: The central control device provides several sets of trigger signals to the corresponding routing boards, and adjusts the initial time of each set of trigger signal outputs to make the time when each chassis receives the trigger signal the same. The central control device is connected to several of the routing boards. The routing board forwards the trigger signal to the AND gate chip of the function board, wherein each routing board is connected to several function boards, and the communication lines from each routing board to the connected several function boards are of equal length; The trigger signal, after being processed by the AND operation of the AND gate chip, simultaneously reaches several data processing devices to synchronously trigger the data processing devices. The functional board includes the AND gate chip and several data processing devices.

10. A quantum control system, characterized in that, Including the synchronous triggering system as described in any one of claims 1 to 8.

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