Bandgap Reference Voltage Source with Offset and Noise Cancellation and Base Current Compensation

Abstract

The present invention discloses a bandgap reference voltage source with offset and noise cancellation and base current compensation, comprising: a bandgap reference core circuit for outputting a temperature-independent voltage; a base current compensation circuit for balancing the collector currents of transistors in the bandgap reference core circuit to make the circuit more tend to an ideal state; a folded cascode operational amplifier for introducing deep negative feedback to clamp the output voltage of the bandgap reference core circuit; a start-up circuit for enabling the bandgap reference circuit to be powered on and operate in a correct stable state; and an output stage circuit for outputting a reference voltage with zero temperature coefficient. This circuit increases the feedback coefficient of the core loop, reduces the influence of the offset voltage and low-frequency noise from the operational amplifier on the output reference voltage; at the same time, eliminates the influence of the base current of the BJTs in the core circuit on the collector current density, reduces the temperature coefficient of the output reference voltage, and realizes the optimization of the temperature characteristics.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a bandgap reference voltage source with offset and noise elimination and base current compensation. Background Art

[0002] With the development of microelectronics technology, small electronic devices, such as wearable devices and implantable medical devices, have also developed rapidly, and people's performance requirements for these devices have increased. At the front end of the biological signal, multiple VREFs generated by reference voltage sources are required. The bandgap reference source can provide a DC voltage that is almost unaffected by power supply voltage and temperature changes. It is the core circuit of many analog circuits, digital circuits, and mixed signal circuits. Bandgap reference circuits are usually divided into two structures: voltage mode and current mode. Among them, the voltage mode bandgap reference is usually not lower than 1.2V due to its structural limitations, and cannot be used in low-voltage scenarios. Therefore, when a low reference voltage is required, a current mode bandgap reference is generally used.

[0003] However, for the application scenarios of bandgap reference, the noise and offset of the traditional current-mode bandgap BGR (bandgap reference, reference voltage source) are serious, which has a great impact on the accuracy of the output voltage, which restricts the performance of wearable devices and implantable medical devices. In addition, due to the influence of base current, the collector current of the transistor is not equal, so that the temperature characteristics of the bandgap reference deviate from the ideal situation. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a bandgap reference voltage source with offset and noise elimination and base current compensation. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0005] A bandgap reference voltage source with offset and noise elimination and base current compensation, comprising a bandgap reference core circuit, a base current compensation circuit, a folded common source and common gate operational amplifier, a startup circuit and an output stage circuit; wherein,

[0006] The bandgap reference core circuit is used to output a voltage that is independent of temperature;

[0007] The base current compensation circuit is connected to the bandgap reference core circuit and is used to balance the collector current of the transistor in the bandgap reference core circuit so as to make the circuit more ideal;

[0008] The folded cascode operational amplifier is connected to the bandgap reference core circuit and is used to introduce deep negative feedback to clamp the output voltage of the bandgap reference core circuit;

[0009] The startup circuit is connected to the bandgap reference core circuit and is used to power on the bandgap reference circuit to operate in the correct stable state;

[0010] The output stage circuit is connected to the bandgap reference core circuit and is used to output a reference voltage with zero temperature coefficient.

[0011] Advantages of the present invention:

[0012] 1. On the one hand, the bandgap reference voltage source with offset and noise cancellation and base current compensation provided by the present invention designs a high-performance bandgap reference core circuit, increases the feedback coefficient of the core loop, and reduces the influence of the offset voltage and low-frequency noise from the operational amplifier on the output reference voltage; on the other hand, it designs a base current compensation circuit, and eliminates the influence of the base current of the BJT in the core circuit on the collector current density by means of pumping and sinking currents, reduces the temperature coefficient of the output reference voltage, and realizes the optimization of the temperature characteristics;

[0013] 2. The bandgap reference voltage source with offset and noise cancellation and base current compensation provided by the present invention is based on the 0.18μm standard CMOS process. Under the conditions of a power supply voltage of 1.2V and a temperature of 27°C, the output voltage of the bandgap reference source is 600.30mV, the power consumption is 27.06μW, and the integrated noise in the range of 0.1Hz to 100Hz is 7.612μVrms; in the temperature range of -45°C to 125°C, the temperature coefficient is 17.78ppm / °C, and the maximum output error is 0.14%.

[0014] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0015] Figure 1 is a structural block diagram of a bandgap reference voltage source with offset and noise cancellation and base current compensation provided by an embodiment of the present invention;

[0016] Figure 2 is a detailed circuit diagram of a bandgap reference voltage source with offset and noise cancellation and base current compensation provided by an embodiment of the present invention;

[0017] Figure 3 is a detailed circuit diagram of a folded cascode operational amplifier provided by an embodiment of the present invention;

[0018] Figure 4 is a structural diagram of offset and low-frequency noise suppression and a partial small-signal equivalent circuit diagram of a current-mode bandgap reference voltage source provided by an embodiment of the present invention;

[0019] Figure 5 is a related structural diagram of a traditional current-mode BGR;

[0020] Figure 6 is the start-up waveform diagram of the current-mode bandgap reference circuit provided by the embodiment of the present invention;

[0021] Figure 7 is the change curve of the output reference voltage of the current-mode bandgap reference circuit provided by the embodiment of the present invention with temperature;

[0022] Figure 8 is the change curve of the output reference voltage of the traditional current-mode bandgap reference with temperature;

[0023] Figure 9 is the simulation diagram of the offset suppression ability of the current-mode bandgap reference circuit provided by the embodiment of the present invention;

[0024] Figure 10 is the simulation diagram of the offset suppression ability of the traditional current-mode bandgap reference;

[0025] Figure 11 is the AC simulation diagram of the folded cascode operational amplifier provided by the embodiment of the present invention;

[0026] Figure 12 is the change curve of the equivalent output noise of the current-mode bandgap reference circuit provided by the embodiment of the present invention with frequency;

[0027] Figure 13 is the change curve of the equivalent output noise of the traditional current-mode bandgap reference with frequency;

[0028] Figure 14 is the simulation curve of the average output voltage and 1σ error of the current-mode bandgap reference circuit provided by the embodiment of the present invention with temperature change.

[0029] Figure 15 is the simulation curve of the average output voltage and 1σ error of the traditional current-mode bandgap reference with temperature change.

[0030] Figure 16 is the simulation curve of the static total current of the current-mode bandgap reference circuit with offset and noise cancellation and base current compensation provided by the embodiment of the present invention with temperature change. Detailed implementation manners

[0031] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0032] Embodiment 1

[0033] Please refer to Figure 1 , Figure 1It is a structural block diagram of a bandgap reference voltage source with offset and noise cancellation and base current compensation provided by an embodiment of the present invention, which includes a bandgap reference core circuit, a base current compensation circuit, a folded cascode operational amplifier, a startup circuit, and an output stage circuit; wherein,

[0034] The bandgap reference core circuit is used to output a voltage independent of temperature;

[0035] The base current compensation circuit is connected to the bandgap reference core circuit and is used to balance the collector currents of the transistors in the bandgap reference core circuit to make the circuit more ideal;

[0036] The folded cascode operational amplifier is connected to the bandgap reference core circuit and is used to introduce deep negative feedback to clamp the output voltage of the bandgap reference core circuit;

[0037] The startup circuit is connected to the bandgap reference core circuit and is used to make the bandgap reference circuit powered on and work in the correct stable state;

[0038] The output stage circuit is connected to the bandgap reference core circuit and is used to output a reference voltage with zero temperature coefficient.

[0039] Further, please refer to Figure 2 , Figure 2 It is a detailed circuit diagram of a bandgap reference voltage source with offset and noise cancellation and base current compensation provided by an embodiment of the present invention, wherein,

[0040] The bandgap reference core circuit includes a first core NPN BJT Q3, a second core NPN BJT Q4, a third core NPN BJT Q5, a first core PMOS M P5 , a second core PMOS M P6 , a third core PMOS M P7 , a first core resistor R4, a second core resistor R5, a third core resistor R6, and a fourth core resistor R7; wherein,

[0041] The source terminal of the first core PMOS M P5 is connected to VDD, its gate terminal is connected to the output terminals of the startup circuit and the folded cascode operational amplifier, and its drain terminal is connected to the collector of the first core NPN BJT Q3 and the inverting input terminal of the folded cascode operational amplifier;

[0042] The source terminal of the second core PMOS M P6 is connected to VDD, its gate terminal is connected to the output terminal of the folded cascode operational amplifier, and its drain terminal is connected to the collector of the second core NPN BJT Q4;

[0043] The source terminal of the third core PMOS M P7The source terminal of [it] is connected to VDD, its gate terminal is connected to the output terminal of the folded cascode operational amplifier, and its drain terminal is connected to the collector of the third core NPN BJT Q5;

[0044] The emitter of the first core NPN BJT Q3 is connected to GND, and its base is connected to the collector of the second core NPN BJT and the positive input terminal of the folded cascode operational amplifier;

[0045] The base of the second core NPN BJT Q4 is connected to the base of the third core NPN BJT Q5 and the collector of the third core NPN BJT Q5;

[0046] The emitter of the third core NPN BJT Q5 is connected to GND;

[0047] The first core resistor R4 is connected between the collector of the first core NPN BJT Q3 and GND;

[0048] The second core resistor R5 is connected between the emitter of the second core NPN BJT Q4 and GND;

[0049] The third core resistor R6 is connected between the collector of the second core NPN BJT Q4 and GND;

[0050] The fourth core resistor R7 is connected between the collector of the third core NPN BJT Q5 and GND.

[0051] The bandgap reference core circuit designed in this embodiment increases the feedback coefficient of the core loop and reduces the influence of the offset voltage and low-frequency noise from the operational amplifier on the output reference voltage.

[0052] Further, please continue to refer to Figure 2 , where the base current compensation circuit includes the first compensation NPN BJT Q1, the second compensation NPN BJT Q2, the third compensation NPN BJT Q6, the first compensation NMOS M N3 , the second compensation NMOS M N4 , the first compensation PMOS M P3 , the second compensation PMOS M P4 , the third compensation PMOS M P8 , the fourth compensation PMOS M P9 , the fifth compensation PMOS M P10 , the sixth compensation PMOS M P11 , the seventh compensation PMOS M P12 , the first compensation resistor R2, the second compensation resistor R3, the third compensation resistor R8, and the fourth compensation resistor R9.

[0053] Among them, the first compensation NPN BJT Q1, the second compensation NPN BJT Q2, the first compensation PMOS M P3 , the second compensation PMOS M P4 , the first compensation resistor R2, and the second compensation resistor R3 form the left compensation circuit; among them,

[0054] The emitter of the first compensation NPN BJT Q1 is connected to GND, its base is connected to the collector of the second compensation NPN BJT Q2, and its collector is connected to the drain of the first compensation PMOS M P3 ;

[0055] The emitter of the second compensation NPN BJT Q2 is connected to GND, its base is connected to the collector of the first core NPN BJT Q3, and its collector is connected to the drain of the second compensation PMOS M P4 ;

[0056] The source of the first compensation PMOS M P3 is connected to VDD, and its gate is connected to the output of the folded cascode operational amplifier;

[0057] The source of the second compensation PMOS M P4 is connected to VDD, and its gate is connected to the output of the folded cascode operational amplifier;

[0058] The first compensation resistor R2 is connected between the collector of the first compensation NPN BJT Q1 and GND;

[0059] The second compensation resistor R3 is connected between the collector of the second compensation NPN BJT Q2 and GND;

[0060] Furthermore, the third compensation NPN BJT Q6, the first compensation NMOS M N3 , the second compensation NMOS M N4 , the third compensation PMOS M P8 , the fourth compensation PMOS M P9 , the fifth compensation PMOS M P10 , the sixth compensation PMOS M P11 , the seventh compensation PMOS M P12 , the third compensation resistor R8, and the fourth compensation resistor R9 form the right compensation circuit; among them,

[0061] The base of the third compensation NPN BJT Q6 is connected to the drain of the sixth compensation PMOS M P11 , the gate of the sixth compensation PMOS M P11 , the gate of the fifth compensation PMOS M P10 , and its collector is connected to the seventh compensation PMOS MP12 the drain terminal of, the fifth compensating PMOS transistor M P10 the source terminal of, the sixth compensating PMOS transistor M P11 the source terminal of;

[0062] The third compensating PMOS transistor M P8 has its source terminal connected to VDD, and its gate terminal connected to the gate terminal of the fourth compensating PMOS transistor M P9 the gate terminal of, the fourth compensating PMOS transistor M P9 the drain terminal of, the first compensating NMOS transistor M N3 the drain terminal of;

[0063] The fourth compensating PMOS transistor M P9 has its source terminal connected to VDD;

[0064] The fifth compensating PMOS transistor M P10 has its drain terminal connected to the gate terminal of the first compensating NMOS transistor M N3 the gate terminal of, the second compensating NMOS transistor M N4 the gate terminal of, the second compensating NMOS transistor M N4 the drain terminal of;

[0065] The seventh compensating PMOS transistor M P12 has its source terminal connected to VDD, and its gate terminal connected to the output terminal of the folded cascode operational amplifier;

[0066] The first compensating NMOS transistor M N3 the source terminal of and the second compensating NMOS transistor M N4 the source terminal of are both connected to GND;

[0067] The third compensating resistor R8 is connected between the emitter of the third compensating NPN BJT Q6 and GND;

[0068] The fourth compensating resistor R9 is connected between the collector of the third compensating NPN BJT Q6 and GND.

[0069] Optionally, as an implementation, as Figure 3 shown, Figure 3 is the folded cascode operational amplifier provided by the embodiment of the present invention, which includes a current source circuit, a DC bias circuit, and a folded cascode differential pair connected in sequence; wherein,

[0070] The current source circuit is used to generate a stable current;

[0071] The DC bias circuit is used to provide an appropriate bias current for the amplifier circuit and determine the static operating point;

[0072] The folded cascode differential pair is used for small-signal amplification.

[0073] Specifically, the current source circuit includes a first current source NMOS transistor M1, a second current source NMOS transistor M2, a third current source NMOS transistor M7, a fourth current source NMOS transistor M8, a first current source PMOS transistor M3, a second current source PMOS transistor M4, a third current source PMOS transistor M5, a fourth current source PMOS transistor M6, and a first current source resistor R 11 , and a second current source resistor R 12 ; among them,

[0074] The source terminal of the first current source NMOS transistor M1 is connected to GND, and its gate terminal is connected to the drain terminal of the first current source NMOS transistor M1 and the gate terminal of the second current source NMOS transistor M2;

[0075] The source terminal of the second current source NMOS transistor M2 is connected to GND, and its drain terminal is connected to the gate terminal of the second current source PMOS transistor M4 and the drain terminal of the first current source PMOS transistor M3;

[0076] The source terminal of the third current source NMOS transistor M7 is connected to GND, and its gate terminal is connected to the gate terminal of the fourth current source NMOS transistor M8, the drain terminal of the fourth current source NMOS transistor M8, the drain terminal of the second current source PMOS transistor M4, and the drain terminal of the fourth current source PMOS transistor M6. Its drain terminal is connected to the drain terminal of the third current source PMOS transistor M5, the gate terminal of the first current source PMOS transistor M3, the gate terminal of the third current source PMOS transistor M5, and the gate terminal of the fourth current source PMOS transistor M6;

[0077] The source terminal of the fourth current source NMOS transistor M8 is connected to GND;

[0078] The source terminals of the first current source PMOS transistor M3, the second current source PMOS transistor M4, the third current source PMOS transistor M5, and the fourth current source PMOS transistor M6 are all connected to VDD;

[0079] The first current source resistor R 11 is connected between the drain terminal of the first current source NMOS transistor M1 and VDD;

[0080] The second current source resistor R 12 is connected between the source terminal of the fourth current source PMOS transistor M6 and VDD.

[0081] Furthermore, please continue to refer to Figure 3 , where the DC bias circuit includes a first bias NMOS transistor M 11 , a second bias NMOS transistor M 12 , a third bias NMOS transistor M 15 , a fourth bias NMOS transistor M 19 , a fifth bias NMOS transistor M 18 , a sixth bias NMOS transistor M17 , the first bias PMOS transistor M9, the second bias PMOS transistor M 10 , the third bias PMOS transistor M 16 , the fourth bias PMOS transistor M 13 , the fifth bias PMOS transistor M 14 ; wherein,

[0082] The source terminal of the first bias NMOS transistor M 11 is connected to GND, its gate terminal is connected to the gate terminal of the third current source NMOS transistor M7, and its drain terminal is connected to the drain terminal of the first bias PMOS transistor M9, the gate terminal of the first bias PMOS transistor M9, the gate terminal of the second bias PMOS transistor M 10 , the gate terminal of the third bias PMOS transistor M 16 ;

[0083] The source terminal of the second bias NMOS transistor M 12 is connected to GND, its gate terminal is connected to the gate terminal of the third bias NMOS transistor M 15 , the drain terminal of the second bias NMOS transistor M 12 , the drain terminal of the second bias PMOS transistor M 10 ;

[0084] The source terminal of the third bias NMOS transistor M 15 is connected to GND, and its drain terminal is connected to the drain terminal of the fifth bias PMOS transistor M 14 , the gate terminal of the fifth bias PMOS transistor M 14 ;

[0085] The source terminal of the fourth bias NMOS transistor M 19 is connected to GND, its gate terminal is connected to the drain terminal of the fourth bias NMOS transistor M 19 , the source terminal of the fifth bias NMOS transistor M 18 ;

[0086] The gate terminal of the fifth bias NMOS transistor M 18 is connected to the gate terminal of the sixth bias NMOS transistor M 17 , the drain terminal of the sixth bias NMOS transistor M 17 , the drain terminal of the third bias PMOS transistor M 16 , and its drain terminal is connected to the source terminal of the sixth bias NMOS transistor M 17 ;

[0087] The source terminals of the first bias PMOS transistor M9, the second bias PMOS transistor M 10 , and the third bias PMOS transistor M 16 are all connected to VDD;

[0088] The fourth bias PMOS transistor M 13The source terminal of 13 is connected to the drain terminal of the fourth bias PMOS transistor M 14 and the source terminal of the fifth bias PMOS transistor M

[0089] Furthermore, please continue to refer to Figure 3 , where the folded cascode differential pair includes the first differential NMOS transistor M 23 , the second differential NMOS transistor M 27 , the third differential NMOS transistor M 22 , the fourth differential NMOS transistor M 26 , the fifth differential NMOS transistor M 29 , the sixth differential NMOS transistor M 32 , the first differential PMOS transistor M 20 , the second differential PMOS transistor M 24 , the third differential PMOS transistor M 21 , the fourth differential PMOS transistor M 25 , the fifth differential PMOS transistor M 28 , the sixth differential PMOS transistor M 30 , the seventh differential PMOS transistor M 31 ; where

[0090] The source terminal of the first differential NMOS transistor M 23 is connected to GND, and its gate terminal is connected to the gate terminal of the second differential NMOS transistor M 27 , the drain terminal of the third differential NMOS transistor M 22 , the drain terminal of the third differential PMOS transistor M 21 , and its drain terminal is connected to the source terminal of the third differential NMOS transistor M 22 ;

[0091] The source terminal of the second differential NMOS transistor M 27 is connected to GND, and its drain terminal is connected to the source terminal of the fourth differential NMOS transistor M 26 ;

[0092] The gate terminal of the third differential NMOS transistor M 22 is connected to the gate terminal of the fourth differential NMOS transistor M 26 and the drain terminal of the fifth bias NMOS transistor M 29 ;

[0093] The drain terminal of the fourth differential NMOS transistor M 26 is connected to the drain terminal of the fourth differential PMOS transistor M 25 and serves as the output terminal of the folded cascode operational amplifier;

[0094] The source terminal of the fifth differential NMOS transistor M 29 is connected to GND, and its gate terminal is connected to the gate terminal of the sixth differential NMOS transistor M32 The gate terminal of the fifth differential NMOS transistor M 29 The drain terminal of the fifth differential PMOS transistor;

[0095] The source terminal of the sixth differential NMOS transistor is connected to GND, and its drain terminal is connected to the source terminal of the sixth differential PMOS transistor M 28 The source terminal of the seventh differential PMOS transistor M 31 The source terminal;

[0096] The source terminal of the first differential PMOS transistor M 20 is connected to VDD, and its gate terminal is connected to the gate terminal of the first bias PMOS transistor M9, the gate terminal of the second differential PMOS transistor M 24 The gate terminal of the fifth differential PMOS transistor M 28 The gate terminal, and its drain terminal is connected to the source terminal of the third differential PMOS transistor M 21 The source terminal of the sixth differential PMOS transistor M 30 The drain terminal;

[0097] The source terminal of the second differential PMOS transistor M 24 is connected to VDD, and its drain terminal is connected to the source terminal of the fourth differential PMOS transistor M 25 The source terminal of the seventh differential PMOS transistor M 31 The drain terminal;

[0098] The gate terminal of the third differential PMOS transistor M 21 is connected to the gate terminal of the fourth differential PMOS transistor M 25 The drain terminal of the third bias NMOS transistor M 15 The drain terminal;

[0099] The source terminal of the fifth differential PMOS transistor M 28 is connected to VDD;

[0100] The gate terminal of the sixth differential PMOS transistor M 30 is used as the positive input port of the folded cascode operational amplifier;

[0101] The gate terminal of the seventh differential PMOS transistor M 31 is used as the negative input port of the folded cascode operational amplifier.

[0102] Furthermore, please continue to refer to Figure 2 , in which the startup circuit includes the first startup NMOS transistor M N1 , the second startup NMOS transistor M N2 , the first startup PMOS transistor M P1 , the second startup PMOS transistor M P2 , the first startup resistor R1; where

[0103] The first startup NMOS transistor M N1The source terminal of is connected to GND, and its gate terminal and drain terminal are connected together and commonly connected to the gate terminal of the second startup NMOS transistor M N2 ;

[0104] The source terminal of the second startup NMOS transistor M N2 is connected to GND, and its drain terminal is connected to the gate terminal of the second startup PMOS transistor M P2 , the drain terminal of the first startup PMOS transistor M P1 ;

[0105] The source terminal of the first startup PMOS transistor M P1 is connected to VDD, and its gate terminal is connected to the output terminal of the folded cascode operational amplifier;

[0106] The source terminal of the second startup PMOS transistor M P2 is connected to VDD, and its drain terminal is connected to the drain terminal of the first core PMOS transistor M P5 ;

[0107] The first startup resistor R1 is connected between the drain terminal of the first startup NMOS transistor M N1 and VDD.

[0108] Furthermore, please continue to refer to Figure 2 , where the output stage circuit includes the first output PMOS transistor M P13 , the first output resistor R 10 ; where

[0109] The source terminal of the first output PMOS transistor M P13 is connected to VDD, and its gate terminal is connected to the output terminal of the folded cascode operational amplifier;

[0110] The first output resistor R 10 is connected between the drain terminal of the first output PMOS transistor M P13 and GND.

[0111] The detailed circuit diagram of the bandgap reference voltage source with offset and noise cancellation and base current compensation provided by the present invention; on the one hand, a high-performance bandgap reference core circuit is designed, increasing the feedback coefficient of the core loop and reducing the influence of the offset voltage and low-frequency noise from the operational amplifier on the output reference voltage; on the other hand, a base current compensation circuit is designed, and by means of pumping and sinking currents, the influence of the base current of the BJT in the core circuit on the collector current density is eliminated, reducing the temperature coefficient of the output reference voltage and realizing the optimization of the temperature characteristics.

[0112] Next, the basic principle of the BGR with offset and noise cancellation and base current compensation provided by the present invention will be introduced, compared and analyzed with the traditional current-mode bandgap reference circuit, and then combined with simulation tests, the beneficial effects of the present invention will be described in detail.

[0113] Specifically, please refer to Figure 4 , Figure 4 , which is the structural diagram of offset and low-frequency noise suppression and a partial small-signal equivalent circuit diagram provided by the embodiments of the present invention. Among them, the left figure is the structural diagram of offset and low-frequency noise suppression based on a current-mode BGR, and the right figure is a partial small-signal equivalent circuit diagram. As Figure 4 shown, the perturbation ΔV O of noise to V n，O is:

[0114]

[0115] To find the feedback coefficient F, it is necessary to find the perturbation of V O noise ΔV O causing the perturbation of V X and V Y . The perturbation received by V Y is conveyed through two paths. First, it is through M3 and Q3 to V Z , and V Z is through Q2 to V Y . The perturbation of V Z is:

[0116]

[0117] where g mp is the transconductance of transistor M 1-3 . The currents flowing through Q1 - Q3 are the same, so they have the same transconductance g mQ . Then, the perturbation of V O by Q2 to V Y is:

[0118]

[0119] R Y is the impedance at the V Y node, R Y = r op / / R1 / / g mQ r oQ R2, r op is the small-signal impedance of transistor g mp is the small-signal impedance of transistor M 1-3 . r oQ is the small-signal impedance of Q1 - Q3. Another perturbation of V O reaches V Y through M2:

[0120] ΔV Y2 = -g mp R Y ΔV O(4)

[0121] Then V Y is perturbed by V O as

[0122]

[0123] V X is also perturbed by V O from two paths. The first path is through V Y and Q1 to convey to V X :

[0124] ΔV X1 =-g mQ R X ΔV Y =g mQ R X g mp R Y ΔV O (6)

[0125] R X is the impedance at the V X node, R X =r op / / r oQ / / R2. V X is perturbed by V O through another path via M1 to convey to V X :

[0126] ΔV X2 =-g mp R X ΔV O (7)

[0127] Then V X is perturbed by V O as

[0128] ΔV X =ΔV X1 +ΔV X2 =g mp R X (g mQ R Y -1)ΔV O (8)

[0129] The feedback coefficient F is

[0130]

[0131] The reference output voltage error V n,REF caused by the low-frequency noise of the error amplifier is

[0132]

[0133] For comparison, see Figure 5 , Figure 5 , which is the related structure diagram of a traditional current-mode BGR. Among them, Figure 4 Figure (a) in is the structure diagram of the traditional current-mode BGR, Figure (b) is the feedback model of the traditional current-mode BGR error amplifier, and Figure (c) is the small-signal equivalent circuit of the traditional current-mode BGR.

[0134] In the traditional current-mode bandgap reference, the feedback coefficient F of the feedback network is:

[0135]

[0136] The reference output voltage error V OS,EA caused by the input offset voltage V OS,REF of the error amplifier is:

[0137]

[0138] In the formula, A1 is the gain from V O to V REF , then R Y = r op / / R1 / / g mQ r oQ R2 ≈ g mQ r oQ R2.

[0139] Comparing equations (10) and (12), it can be seen that the low-frequency noise of the amplifier of the reference proposed by the present invention on the reference output voltage error is 1 / g mQ R X g mQ R oQ times that of the traditional structure. The analysis of the offset voltage is similar to that of the low-frequency noise, and the equivalent reference voltage will also be greatly reduced. The main reason can be known by comparing equations (9) and (10). The feedback coefficient of the reference core has been greatly improved, thereby reducing the influence of the low-frequency noise and offset voltage of the operational amplifier on the reference output accuracy.

[0140] Furthermore, Kirchhoff's current law is used for the drain terminals of the first core NPN BJT Q3, the second core NPN BJT Q4, and the third core NPN BJT Q5 in the bandgap reference core circuit respectively:

[0141]

[0142] Among them, I DS5,6,7 are respectively the core PMOS transistors M P5, M P6 , M P7 The leakage currents of P6 , P7 , and R are equal due to the current mirror relationship; I R represents the magnitude of the current flowing through R 4,5,6 . Since these resistors have the same resistance value and the same voltage drop across them, the magnitudes of the currents flowing through these resistors are the same. Due to the influence of the base current, the collector currents of the three transistors are not equal, so the temperature characteristics of the bandgap reference deviate from the ideal situation, and it will also cause an increase in the offset of the operational amplifier.

[0143] Based on this, the base current compensation circuit including the left and right parts is designed in this embodiment. Among them, the role of the left half circuit in base current compensation is to draw a current of magnitude I B1 from node A. It consists of the field effect transistors M P3 , M P4 ; the bipolar transistors Q1, Q2 and the resistors R2, R3. Among them, Q1 and Q2 are both transistors of the same type and the same area as Q3; M P3 , M P4 form an equivalent replicated current mirror with other PMOSs in the circuit; R2 and R3 have the same resistance value as the bypass resistor R4 in the core circuit, and their role is to make the DC voltage biases of Q1, Q2 and Q3 the same. The relationship between the base current and the collector current of the Q3 transistor is:

[0144]

[0145] where I C is the magnitude of the collector current of the bipolar transistor in the core circuit after base current compensation, and β1 is the common emitter DC amplification factor of the Q3 transistor.

[0146] The magnitude of the current on the PMOS current mirror after base current compensation is:

[0147] I DS = I C + i b1 + I R (15)

[0148] The base currents of the Q1 and Q2 transistors are:

[0149]

[0150] where I BQ2 is the magnitude of the current drawn from node A. The β value is generally from dozens to hundreds, so the left half of the base current compensation circuit draws a current magnitude from node A that is close enough to I B1 .

[0151] The base current compensation circuit on the right half is composed of field effect transistors M P8～12 , M N3～4 ; bipolar transistor Q6 and resistors R8, R9. Among them, M P10 and M P5 , M P6 and other transistors form a current mirror; M P8 and M P9 , M P10 and M P11 , M N3 and M N4 respectively form current mirrors; the resistance value of R8 is the same as that of R5, and the resistance value of R9 is the same as that of R6. In this circuit structure, the biasing conditions of Q6 and Q4 are the same.

[0152] For transistor Q4, the relationship between its base current and collector current is:

[0153]

[0154] β2 is the common emitter DC amplification factor of transistor Q4.

[0155] At the collector junction node of transistor Q6, according to Kirchhoff's current law:

[0156] I C6 = I DS12 - I R - 2I BQ6 (19)

[0157] Substitute I BQ6 = I C6 / β2 into equation (19), and the base current of transistor Q6 can be solved as:

[0158]

[0159] I BQ6 After being mirrored and copied by the current mirror, it is injected into node C.

[0160] β2 generally takes values from dozens to hundreds, and the base current generally takes values of dozens of nA. Therefore, in the base current compensation circuit on the right half, the current injected at node C is close enough to I B2 .

[0161] Apply Kirchhoff's current law to nodes A, B, and C after base current compensation respectively:

[0162]

[0163] The base current compensation circuit realizes extracting a current close enough to I B1 at node A and injecting a current close enough to I B2The effect of the current. Although theoretically, the collector currents of the three bipolar transistors in the compensated core circuit are not exactly the same, they are close enough to eliminate the negative impact of the base current in the core circuit, making the circuit closer to the ideal situation in principle, which is beneficial to reducing the temperature coefficient of the output reference voltage and minimizing the operational amplifier offset.

[0164] At the same time, the base current compensation circuit also introduces new paths in the core loop, which will change the feedback parameters of the core loop. First, analyze the right half of the base current compensation circuit. M P9 is a PMOS in diode connection, which results in a very low total parallel resistance value at its source node. From the perspective of this feedback path, its feedback coefficient is very small. Compared with the feedback coefficient of the core loop, the feedback coefficient of this new feedback path is so small that it can be ignored.

[0165] The left half of the base current compensation circuit newly introduces two feedback paths in total. In both feedback paths, the small signal transmitted from the output terminal of the operational amplifier will pass through the collector of Q2 tube and then return to the input terminal of the operational amplifier from its base. The feedback coefficients of these two feedback paths will become very small because they pass through Q2. Compared with the feedback coefficient of the core loop, the feedback coefficients of these two new feedback paths are also so small that they can be ignored. Therefore, the influence of the base current compensation circuit on the feedback coefficient of the core loop is very small.

[0166] Furthermore, please refer jointly to Figures 1 - 4 , when the core circuit is not at the ideal static operating point, the gate voltage of M P2 is at a low level, the gate voltage of M P2 is less than its threshold voltage, M P2 conducts, the path from VDD to node A is opened, and node A starts to be charged, and its potential gradually rises; due to the effect of the operational amplifier, the potential of node P starts to decrease, and the core circuit reaches the normal operating state. After that, due to the decrease in the potential of node P, the gate voltage of M P1 is less than its threshold voltage, M P1 conducts. Since the pull-up ability of M P1 is stronger than that of M N2 , as a result, the parasitic capacitance of node Q is charged, and the potential of node Q rises until M P2 turns off. At this time, the startup process ends, and all the charge and discharge paths from the power supply to the nodes in the core circuit are closed, and the bandgap reference circuit is no longer affected by the startup process.

[0167] Next, the circuit provided by the present invention and the traditional circuit are subjected to simulation tests, and the results are as Figures 6 - 16 shown, where

[0168] Figure 6It is the start-up waveform diagram of the current-mode bandgap reference circuit provided by the embodiment of the present invention; it can be seen that the start-up time of the reference voltage source is less than 30 microseconds, verifying that the proposed reference voltage source has the characteristic of fast response.

[0169] Figure 7 It is the curve graph of the output reference voltage of the current-mode bandgap reference circuit provided by the embodiment of the present invention changing with temperature; it can be seen that the temperature coefficient of the current-mode bandgap reference source proposed by the present invention is 17.78 ppm / °C.

[0170] Figure 8 It is the curve graph of the output reference voltage of the traditional current-mode bandgap reference changing with temperature; it can be seen that the temperature coefficient of the traditional current-mode bandgap reference source is 31.42 ppm / °C. Comparing Figure 7 and Figure 8 , it verifies the optimization of the temperature characteristics of the bandgap reference source proposed by the present invention.

[0171] Figure 9 It is the simulation diagram of the offset suppression ability of the current-mode bandgap reference circuit provided by the embodiment of the present invention. For the current-mode bandgap reference source proposed by the present invention, the reference output voltage before introducing the operational amplifier offset voltage is about 600.30 mV; after adding a 10 mV operational amplifier offset voltage, the reference output voltage is about 601.11 mV, and the change amount before and after is 0.81 mV, and the offset voltage is attenuated by about 12 times at the output end.

[0172] Figure 10 It is the simulation diagram of the offset suppression ability of the traditional current-mode bandgap reference. For the traditional current-mode bandgap reference source, the reference output voltage before introducing the offset voltage is about 600.37 mV; after adding a 10 mV operational amplifier offset voltage, the reference output voltage is about 661.30 mV, and the change amount before and after is 60.92 mV, and the offset voltage is amplified by about 61 times at the output end. Comparing Figure 7 and Figure 8 , it verifies that the current-mode bandgap reference source proposed by the present invention has excellent ability to suppress operational amplifier offset.

[0173] Figure 11 It is the AC simulation diagram of the folded cascode operational amplifier provided by the embodiment of the present invention. The low-frequency gain of this operational amplifier is 82 dB, and the phase margin is 86°, verifying its excellent performance and being suitable for voltage clamping in the bandgap reference circuit.

[0174] Figure 12 It is the curve of the equivalent output noise of the current-mode bandgap reference circuit provided by the embodiment of the present invention changing with frequency. It can be seen that in the frequency range of 0.1 Hz to 100 Hz, the integrated noise of the output voltage generated by the bandgap reference source proposed by the present invention is 7.61 μVrms.

[0175] Figure 13 It is the curve of the equivalent output noise of the traditional current-mode bandgap reference varying with frequency. It can be seen that in the frequency range of 0.1 Hz to 100 Hz, the integrated noise of the output voltage generated by the traditional current-mode bandgap reference source is 98.03 μVrms. Comparing Figure 12 and Figure 13 verifies that the output reference voltage of the bandgap reference circuit proposed by the present invention has a lower noise level.

[0176] Figure 14 It is the simulation curve of the average output voltage and 1σ error of the current-mode bandgap reference circuit provided by the embodiment of the present invention varying with temperature. It can be seen that in the temperature range of -45°C to 125°C, the maximum value of the output error of the current-mode bandgap reference proposed by the present invention is 0.146%.

[0177] Figure 15 It is the simulation curve of the average output voltage and 1σ error of the traditional current-mode bandgap reference varying with temperature. It can be seen that in the temperature range of -45°C to 125°C, the maximum value of the output error of the traditional current-mode bandgap reference is 2.406%. Comparing Figure 14 and Figure 15 verifies that the current-mode bandgap reference circuit proposed by the present invention has a stronger ability to withstand random offset and has better performance in Monte Carlo simulation.

[0178] Figure 16 It is the simulation curve of the static total current of a current-mode bandgap reference circuit with offset and noise cancellation and base current compensation provided by the embodiment of the present invention varying with temperature. It can be seen that at 27°C, the static total current of the bandgap reference source is 22.55 μA and the power consumption is 27.06 μW; at 125°C, the power consumption is the largest, the static total current is 22.84 μA, and the power consumption reaches 27.41 μW. It verifies that the power consumption of the bandgap reference circuit is also positively correlated with temperature.

[0179] In summary, the bandgap reference circuit proposed by the present invention is based on a 0.18 μm standard CMOS process. Under the conditions of a power supply voltage of 1.2 V and a temperature of 27°C, the output voltage of the bandgap reference source is 600.30 mV, the power consumption is 27.06 μW, and the integrated noise in the range of 0.1 Hz to 100 Hz is 7.612 μVrms. In the temperature range of -45°C to 125°C, the temperature coefficient is 17.78 ppm / °C, and the maximum value of the output error is 0.14%.

[0180] It should be noted that the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0181] In addition, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of another identical element in the article or device comprising the element.

[0182] The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A bandgap reference voltage source with offset and noise cancellation and base current compensation, characterized in that It includes a bandgap reference core circuit, a base current compensation circuit, a folded common source and common gate operational amplifier, a startup circuit and an output stage circuit; wherein, The bandgap reference core circuit is used to output a voltage that is independent of temperature; The base current compensation circuit is connected to the bandgap reference core circuit and is used to balance the collector current of the transistor in the bandgap reference core circuit so as to make the circuit more ideal; The folded cascode operational amplifier is connected to the bandgap reference core circuit and is used to introduce deep negative feedback to clamp the output voltage of the bandgap reference core circuit; The startup circuit is connected to the bandgap reference core circuit and is used to enable the bandgap reference circuit to be powered on and operate in a correct stable state; The output stage circuit is connected to the bandgap reference core circuit and is used to output a reference voltage with a zero temperature coefficient; Wherein, the base current compensation circuit includes a first compensation NPN-type BJT tube, a second compensation NPN-type BJT tube, a third compensation NPN-type BJT tube, a first compensation NMOS tube, a second compensation NMOS tube, a first compensation PMOS tube, a second compensation PMOS tube, a third compensation PMOS tube, a fourth compensation PMOS tube, a fifth compensation PMOS tube, a sixth compensation PMOS tube, a seventh compensation PMOS tube, a first compensation resistor, a second compensation resistor, a third compensation resistor, and a fourth compensation resistor; The first compensation NPN BJT tube, the second compensation NPN BJT tube, the first compensation PMOS tube, the second compensation PMOS tube, the first compensation resistor, and the second compensation resistor constitute a left compensation circuit; The emitter of the first compensation NPN BJT tube is connected to GND, and the base thereof is connected to the collector of the second compensation NPN BJT tube, and the collector thereof is connected to the drain of the first compensation PMOS tube; The emitter of the second compensation NPN BJT tube is connected to GND, the base thereof is connected to the collector of the first core NPN BJT tube, and the collector thereof is connected to the drain of the second compensation PMOS tube; The source end of the first compensation PMOS tube is connected to VDD, and the gate end thereof is connected to the output end of the folded common source and common gate operational amplifier; The source end of the second compensation PMOS tube is connected to VDD, and the gate end thereof is connected to the output end of the folded common source and common gate operational amplifier; The first compensation resistor is connected between the collector of the first compensation NPN type BJT tube and GND; The second compensation resistor is connected between the collector of the second compensation NPN type BJT tube and GND; The third compensation NPN BJT tube, the first compensation NMOS tube, the second compensation NMOS tube, the third compensation PMOS tube, the fourth compensation PMOS tube, the fifth compensation PMOS tube, the sixth compensation PMOS tube, the seventh compensation PMOS tube, the third compensation resistor, and the fourth compensation resistor constitute a right compensation circuit; wherein, The base of the third compensation NPN BJT tube is connected to the drain terminal of the sixth compensation PMOS tube, the gate terminal of the sixth compensation PMOS tube, and the gate terminal of the fifth compensation PMOS tube, and the collector thereof is connected to the drain terminal of the seventh compensation PMOS tube, the source terminal of the fifth compensation PMOS tube, and the source terminal of the sixth compensation PMOS tube; The source terminal of the third compensation PMOS transistor is connected to VDD, and its gate terminal is connected to the gate terminal of the fourth compensation PMOS transistor, the drain terminal of the fourth compensation PMOS transistor, and the drain terminal of the first compensation NMOS transistor; The source terminal of the fourth compensation PMOS transistor is connected to VDD; The drain terminal of the fifth compensation PMOS transistor is connected to the gate terminal of the first compensation NMOS transistor, the gate terminal of the second compensation NMOS transistor, and the drain terminal of the second compensation NMOS transistor; The source terminal of the seventh compensation PMOS transistor is connected to VDD, and its gate terminal is connected to the output terminal of the folded cascode operational amplifier; The source terminals of the first compensation NMOS transistor and the second compensation NMOS transistor are both connected to GND; The third compensation resistor is connected between the emitter of the third compensation NPN BJT transistor and GND; The fourth compensation resistor is connected between the collector of the third compensation NPN BJT transistor and GND.

2. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 1, characterized in that, The bandgap reference core circuit includes a first core NPN BJT transistor, a second core NPN BJT transistor, a third core NPN BJT transistor, a first core PMOS transistor, a second core PMOS transistor, a third core PMOS transistor, a first core resistor, a second core resistor, a third core resistor, and a fourth core resistor; wherein, The source terminal of the first core PMOS transistor is connected to VDD, its gate terminal is connected to the output terminals of the start-up circuit and the folded cascode operational amplifier, and its drain terminal is connected to the collector of the first core NPN BJT transistor and the inverting input terminal of the folded cascode operational amplifier; The source terminal of the second core PMOS transistor is connected to VDD, its gate terminal is connected to the output terminal of the folded cascode operational amplifier, and its drain terminal is connected to the collector of the second core NPN BJT transistor; The source terminal of the third core PMOS transistor is connected to VDD, its gate terminal is connected to the output terminal of the folded cascode operational amplifier, and its drain terminal is connected to the collector of the third core NPN BJT transistor; The emitter of the first core NPN BJT transistor is connected to GND, and its base terminal is connected to the collector of the second core NPN BJT transistor and the non-inverting input terminal of the folded cascode operational amplifier; The base terminal of the second core NPN BJT transistor is connected to the base terminal and the collector of the third core NPN BJT transistor; The emitter of the third core NPN BJT transistor is connected to GND; The first core resistor is connected between the collector of the first core NPN BJT transistor and GND; The second core resistor is connected between the emitter of the second core NPN BJT transistor and GND; The third core resistor is connected between the collector of the second core NPN BJT transistor and GND; The fourth core resistor is connected between the collector of the third core NPN BJT transistor and GND.

3. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 1, wherein The folded cascode operational amplifier includes a current source circuit, a DC bias circuit, and a folded cascode differential pair connected in sequence; wherein, The current source circuit is used to generate a stable current; The DC bias circuit is used to provide an appropriate bias current for the amplifier circuit and determine the quiescent operating point; The folded cascode differential pair is used for small-signal amplification.

4. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 3, characterized in that, The current source circuit includes a first current source NMOS transistor, a second current source NMOS transistor, a third current source NMOS transistor, a fourth current source NMOS transistor, a first current source PMOS transistor, a second current source PMOS transistor, a third current source PMOS transistor, a fourth current source PMOS transistor, a first current source resistor, and a second current source resistor; among them, The source terminal of the first current source NMOS transistor is connected to GND, and its gate terminal is connected to the drain terminal of the first current source NMOS transistor and the gate terminal of the second current source NMOS transistor; The source terminal of the second current source NMOS transistor is connected to GND, and its drain terminal is connected to the gate terminal of the second current source PMOS transistor and the drain terminal of the first current source PMOS transistor; The source terminal of the third current source NMOS transistor is connected to GND, and its gate terminal is connected to the gate terminal of the fourth current source NMOS transistor, the drain terminal of the fourth current source NMOS transistor, the drain terminal of the second current source PMOS transistor, and the drain terminal of the fourth current source PMOS transistor. Its drain terminal is connected to the drain terminal of the third current source PMOS transistor, the gate terminal of the first current source PMOS transistor, the gate terminal of the third current source PMOS transistor, and the gate terminal of the fourth current source PMOS transistor; The source terminal of the fourth current source NMOS transistor is connected to GND; The source terminals of the first current source PMOS transistor, the second current source PMOS transistor, the third current source PMOS transistor, and the fourth current source PMOS transistor are all connected to VDD; The first current source resistor is connected between the drain terminal of the first current source NMOS transistor and VDD; The second current source resistor is connected between the source terminal of the fourth current source PMOS transistor and VDD.

5. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 3, characterized in that, The DC bias circuit includes a first bias NMOS transistor, a second bias NMOS transistor, a third bias NMOS transistor, a fourth bias NMOS transistor, a fifth bias NMOS transistor, a sixth bias NMOS transistor, a first bias PMOS transistor, a second bias PMOS transistor, a third bias PMOS transistor, a fourth bias PMOS transistor, and a fifth bias PMOS transistor; among them, The source terminal of the first bias NMOS transistor is connected to GND, and its gate terminal is connected to the gate terminal of the third current source NMOS transistor. Its drain terminal is connected to the drain terminal of the first bias PMOS transistor, the gate terminal of the first bias PMOS transistor, the gate terminal of the second bias PMOS transistor, and the gate terminal of the third bias PMOS transistor; The source terminal of the second bias NMOS transistor is connected to GND, and its gate terminal is connected to the gate terminal of the third bias NMOS transistor, the drain terminal of the second bias NMOS transistor, and the drain terminal of the second bias PMOS transistor; The source terminal of the third bias NMOS transistor is connected to GND, and its drain terminal is connected to the drain terminal of the fifth bias PMOS transistor and the gate terminal of the fifth bias PMOS transistor; The source terminal of the fourth bias NMOS transistor is connected to GND, and its gate terminal is connected to the drain terminal of the fourth bias NMOS transistor and the source terminal of the fifth bias NMOS transistor; The gate terminal of the fifth bias NMOS transistor is connected to the gate terminal of the sixth bias NMOS transistor, the drain terminal of the sixth bias NMOS transistor, and the drain terminal of the third bias PMOS transistor. Its drain terminal is connected to the source terminal of the sixth bias NMOS transistor; The source terminals of the first bias PMOS transistor, the second bias PMOS transistor, and the third bias PMOS transistor are all connected to VDD; The source terminal of the fourth-biased PMOS transistor is connected to VDD, and its gate terminal is connected to the drain terminal of the fourth-biased PMOS transistor and the source terminal of the fifth-biased PMOS transistor.

6. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 3, characterized in that, The folded cascode differential pair includes a first differential NMOS transistor, a second differential NMOS transistor, a third differential NMOS transistor, a fourth differential NMOS transistor, a fifth differential NMOS transistor, a sixth differential NMOS transistor, a first differential PMOS transistor, a second differential PMOS transistor, a third differential PMOS transistor, a fourth differential PMOS transistor, a fifth differential PMOS transistor, a sixth differential PMOS transistor, and a seventh differential PMOS transistor; among them, The source terminal of the first differential NMOS transistor is connected to GND, its gate terminal is connected to the gate terminal of the second differential NMOS transistor, the drain terminal of the third differential NMOS transistor, and the drain terminal of the third differential PMOS transistor, and its drain terminal is connected to the source terminal of the third differential NMOS transistor; The source terminal of the second differential NMOS transistor is connected to GND, and its drain terminal is connected to the source terminal of the fourth differential NMOS transistor; The gate terminal of the third differential NMOS transistor is connected to the gate terminal of the fourth differential NMOS transistor and the drain terminal of the fifth-biased NMOS transistor; The drain terminal of the fourth differential NMOS transistor is connected to the drain terminal of the fourth differential PMOS transistor and serves as the output terminal of the folded cascode operational amplifier; The source terminal of the fifth differential NMOS transistor is connected to GND, and its gate terminal is connected to the gate terminal of the sixth differential NMOS transistor, the drain terminal of the fifth differential NMOS transistor, and the drain terminal of the fifth differential PMOS transistor; The source terminal of the sixth differential NMOS transistor is connected to GND, and its drain terminal is connected to the source terminal of the sixth differential PMOS transistor and the source terminal of the seventh differential PMOS transistor; The source terminal of the first differential PMOS transistor is connected to VDD, its gate terminal is connected to the gate terminal of the first-biased PMOS transistor, the gate terminal of the second differential PMOS transistor, and the gate terminal of the fifth differential PMOS transistor, and its drain terminal is connected to the source terminal of the third differential PMOS transistor and the drain terminal of the sixth differential PMOS transistor; The source terminal of the second differential PMOS transistor is connected to VDD, and its drain terminal is connected to the source terminal of the fourth differential PMOS transistor and the drain terminal of the seventh differential PMOS transistor; The gate terminal of the third differential PMOS transistor is connected to the gate terminal of the fourth differential PMOS transistor and the drain terminal of the third-biased NMOS transistor; The source terminal of the fifth differential PMOS transistor is connected to VDD; The gate terminal of the sixth differential PMOS transistor serves as the non-inverting input port of the folded cascode operational amplifier; The gate terminal of the seventh differential PMOS transistor serves as the inverting input port of the folded cascode operational amplifier.

7. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 1, characterized in that, The startup circuit includes a first startup NMOS transistor, a second startup NMOS transistor, a first startup PMOS transistor, a second startup PMOS transistor, and a first startup resistor; among them, The source terminal of the first startup NMOS transistor is connected to GND, and its gate terminal and drain terminal are connected together and commonly connected to the gate terminal of the second startup NMOS transistor; The source terminal of the second startup NMOS transistor is connected to GND, and its drain terminal is connected to the gate terminal of the second startup PMOS transistor and the drain terminal of the first startup PMOS transistor; The source terminal of the first startup PMOS transistor is connected to VDD, and its gate terminal is connected to the output terminal of the folded cascode operational amplifier; The source terminal of the second startup PMOS transistor is connected to VDD, and its drain terminal is connected to the drain terminal of the first core PMOS transistor; The first startup resistor is connected between the drain terminal of the first startup NMOS transistor and VDD.

8. The bandgap reference voltage source with offset and noise cancellation and base current compensation according to claim 1, characterized in that, The output stage circuit includes a first output PMOS transistor and a first output resistor; wherein, the source terminal of the first output PMOS transistor is connected to VDD, and its gate terminal is connected to the output terminal of the folded cascode operational amplifier; the first output resistor is connected between the drain terminal of the first output PMOS transistor and GND.

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