Gate drive circuit and system

Abstract

The application provides a gate drive circuit and system, the gate drive circuit comprises a transistor and a margin adjustment unit; the margin adjustment unit comprises a drive transistor, a first drive module and a floating ground adjustment module; the first end of the first drive module is electrically connected with the source electrode of the drive transistor, the second end of the first drive module is electrically connected with a first voltage source, and the first drive module is used for driving the drive transistor; the first end of the floating ground adjustment module is electrically connected with the floating ground end of the first drive module, the second end of the floating ground adjustment module is electrically connected with a voltage source, and the floating ground adjustment module is used for adjusting the voltage of the floating ground end of the first drive module. By adding the floating ground adjustment module, the voltage of the floating ground end of the first drive module can be adjusted, the gate voltage margin of the transistor is improved, and the problem of low gate voltage margin of the high side and low side transistors in the drive IC circuit in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of gate drive circuit, in particular to a gate drive circuit and system. BACKGROUND

[0002] The conventional gate drive IC usually converts the PWM input signal (with a swing of 0V-5V) from the front-end controller input TTL level into a power supply voltage (with a voltage of usually 4.5-30V) through the internal circuit of the drive IC, and then outputs through the driving tubes SRC and SNK in the chip to drive the high-voltage power MOSFET or IGBT device (the high-voltage side of the power device is usually greater than 600V).

[0003] As shown in Figure 1 , the common gate drive IC usually adopts a low-swing logic signal to control four switch tubes A, B, C and D in the front-stage driver based on the consideration of cost, power consumption and driving efficiency, so as to control the full-swing high-voltage power tubes SRC and SNK to drive the external power device, and therefore a floating ground FGND (FGND = VDD-5V) is needed as the low level of the control logic signal of the gate of the switch tubes A and C, and a voltage source FVDD (FVDD = GND+5V) is needed as the high level of the control logic signal of the gate of the switch tubes B and D, and a bias voltage is provided for M0 and M1 through the mirror source follow structure. That is to say, when the VCC voltage is 20V, the gate control voltage swing of the tubes A and C is 15V-20V, the gate control voltage swing of the tubes B and D is 0V-5V, the gate voltage swing of the SRC tube is 15V+V TH0 -20V, and the gate voltage swing of the SNK tube is 0V-5V-V TH1 .

[0004] Because the bias voltage V BP of the high-voltage bias tube M0 is generated by the source follow structure, when the SRC tube is turned on, the potential of the point PG needs to be rapidly reduced from VDD to FGND+VTH0, and in this process, the parasitic capacitor C gd needs to be rapidly charged, and at this time, a ΔV BP is generated. However, the source follow structure only has the ability of unidirectional sink current, and only relies on the resistance current to charge C gd , and therefore the instantaneous peak current capacity of the SRC tube is affected (as shown in the following figure). In addition, because of the limitation of the structure, the swing of the PG end is limited within VDD to FGND+VTH0 (VTH0 is the threshold voltage of the gate of the tube M0), and the peak current capacity of the SRC tube is also reduced. SUMMARY

[0005] The main purpose of the present application is to provide a gate drive circuit and system to at least solve the problem of low voltage margin of the gate of the transistor of the high side and low side in the drive IC circuit in the prior art.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a gate drive circuit is provided, which comprises a transistor and a margin adjusting unit; the source of the transistor is electrically connected with a first voltage source, and the drain of the transistor is electrically connected with a driven device; the margin adjusting unit comprises a drive transistor, a first drive module and a floating ground adjusting module; the source of the drive transistor is electrically connected with the gate of the transistor; the first end of the first drive module is electrically connected with the source of the drive transistor, the second end of the first drive module is electrically connected with the first voltage source, and the first drive module is used to drive the drive transistor; the first end of the floating ground adjusting module is electrically connected with the floating ground end of the first drive module, and the second end of the floating ground adjusting module is electrically connected with the voltage source, and the floating ground adjusting module is used to adjust the voltage of the floating ground end of the first drive module.

[0007] Optionally, the margin adjusting unit further comprises a second drive module, which is electrically connected with the drain of the drive transistor, and the second drive module is used to drive the drive transistor.

[0008] Optionally, the first drive module comprises a first logic control submodule and a first transistor, the first logic control submodule is used to control the first transistor to be turned on or turned off, the power supply end of the first logic control submodule is electrically connected with the first voltage source, the power supply end of the first logic control submodule is electrically connected with the source of the first transistor, the gate of the first transistor is electrically connected with the control end of the first logic control submodule, the drain of the first transistor is electrically connected with the source of the drive transistor, and the floating ground end of the first logic control submodule is electrically connected with the first end of the floating ground adjusting module.

[0009] Optionally, the second drive module comprises a second logic control submodule and a second transistor, the second logic control submodule is used to control the second transistor to be turned on or turned off, the power supply end of the second logic control submodule is electrically connected with a second voltage source, the control end of the second logic control submodule is electrically connected with the gate of the second transistor, the ground end of the second logic control submodule is grounded respectively with the source of the second transistor, and the drain of the second transistor is electrically connected with the drain of the drive transistor.

[0010] Optionally, the margin adjusting unit further comprises a first biasing module, a second biasing module and a first current source; a first end of the first biasing module is electrically connected with the first voltage source, a second end of the first biasing module is electrically connected with a third end of the floating ground adjusting module, the first biasing module is configured to provide a first biasing voltage drop for the floating ground adjusting module; a first end of the second biasing module is electrically connected with the first voltage source, a second end of the second biasing module is electrically connected with a third end of the first biasing module, a third end of the second biasing module is electrically connected with a fourth end of the first biasing module, a fourth end of the second biasing module is electrically connected with the gate of the driving transistor, the second biasing module is configured to provide a second biasing voltage drop for the gate of the driving transistor; the first current source is electrically connected with the fourth end of the first biasing module.

[0011] Optionally, the floating ground adjusting module comprises a third transistor, a first resistance module and a second resistance module; a source of the third transistor is electrically connected with a first end of the first resistance module and a floating ground end of the first driving module respectively, a drain of the third transistor is electrically connected with a first end of the second resistance module, a gate of the third transistor is electrically connected with a second end of the first biasing module; a second end of the first resistance module is electrically connected with the first voltage source, a second end of the second resistance module is grounded.

[0012] Optionally, the first biasing module comprises a fourth transistor, a fifth transistor and a third resistance module; a gate of the fourth transistor is electrically connected with a drain of the fourth transistor, a gate of the fifth transistor, a drain of the fifth transistor and a third end of the floating ground adjusting module respectively; a source of the fifth transistor is electrically connected with a first end of the first current source, a second end of the first current source is grounded; a source of the fourth transistor is electrically connected with a first end of the third resistance module, a second end of the third resistance module is electrically connected with the first voltage source.

[0013] Optionally, the second biasing module comprises a sixth transistor and a seventh transistor; a source of the sixth transistor is electrically connected with a source of the seventh transistor and a gate of the driving transistor respectively; a drain of the sixth transistor is electrically connected with the first voltage source; a gate of the sixth transistor is electrically connected with a third end of the first biasing module; a gate of the seventh transistor is electrically connected with the third end of the first biasing module; a drain of the seventh transistor is grounded.

[0014] Optionally, the driving transistor is a P-type MOS transistor structure.

[0015] According to another aspect of the present application, there is provided a gate driving system, the gate driving system comprising any one of the gate driving circuits.

[0016] By means of the floating ground adjusting module, the voltage of the floating ground end of the first driving module is adjusted, the gate voltage margin of the transistor is improved, and the problem of low gate voltage margin of the high side and low side transistors in the driving IC circuit in the prior art is solved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings constituting a part of this specification illustrate preferred embodiments of the present application and, together with the description, serve to explain the principles of the present application. The present application is to be considered only from the illustrative embodiments given hereinafter from a non-restrictive point of view. In the drawings:

[0018] Figure 1 A schematic diagram of a gate driving circuit in the prior art is shown;

[0019] Figure 2 A schematic diagram of a high side margin adjusting unit in a gate driving circuit according to an embodiment of the present application is shown;

[0020] Figure 3 A schematic diagram of a gate driving circuit according to an embodiment of the present application is shown;

[0021] Figure 4 A potential sequence schematic diagram of a gate driving circuit according to an embodiment of the present application is shown.

[0022] In the above drawings, the following reference signs are used:

[0023] 100, high side margin adjusting unit; 110, first high side driving module; 120, second high side driving module; 130, floating ground adjusting module; 140, first biasing module; 150, second biasing module. DETAILED DESCRIPTION

[0024] It should be noted that the embodiments and features in the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second" and "third" and the like in the description and in the claims of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or apparatus that includes a list of steps or units is not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products or apparatuses.

[0027] As introduced in the background, because the bias voltage VBP of the high voltage bias tube M0 is generated by the source follow structure, when the SRC tube is turned on, the potential of the PG point will be quickly reduced from VDD to FGND+VTH0, and in this process, the parasitic capacitor Cgd needs to be quickly charged, at this time, a ΔVBP will be generated, but the source follow structure only has the ability of one-way sink current, and only relies on resistance current when charging the Cgd, so it will affect the instantaneous peak current capability of the SRC tube. In addition, due to the limitation of the structure, the swing of the PG end is limited within VDD to FGND+VTH0 (VTH0 is the threshold voltage of the gate of the SRC tube), which will also reduce the peak current capability of the SRC tube. In order to solve the problem of low voltage margin of the gate of the high side and low side transistors in the driving IC circuit in the prior art, the embodiments of the present application provide a gate drive circuit and system.

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0029] The embodiments of the present application provide a gate drive circuit, which comprises a transistor and a margin adjustment unit; the source of the transistor is electrically connected with a first voltage source, and the drain of the transistor is electrically connected with a driven device; the margin adjustment unit comprises a driving transistor, a first driving module and a floating ground adjustment module; the source of the driving transistor is electrically connected with the gate of the transistor; the first end of the first driving module is electrically connected with the source of the driving transistor, the second end of the first driving module is electrically connected with the first voltage source, and the first driving module is used to drive the driving transistor; the first end of the floating ground adjustment module is electrically connected with the floating ground end of the first driving module, and the second end of the floating ground adjustment module is electrically connected with the voltage source; and the floating ground adjustment module is used to adjust the voltage of the floating ground end of the first driving module.

[0030] The floating ground adjusting module is added to the gate drive circuit, so that the voltage of the floating ground end of the first drive module is adjusted, the gate voltage margin of the transistor is improved, and the problem of low gate voltage margin of the high side and low side transistors in the drive IC circuit in the prior art is solved.

[0031] In an embodiment of the present application, the margin adjusting unit further comprises a second drive module, the second drive module is electrically connected to the drain of the drive transistor, and the second drive module is configured to drive the drive transistor.

[0032] Specifically, the current precision is improved because the circuit originally providing bias for the gate voltage VBP of the M0 transistor is updated to a CLASS-AB structure, and the logic modules A and B are configured to generate non-overlapping signals to prevent the AB transistor from passing through to generate a large current.

[0033] In an embodiment of the present application, the first drive module comprises a first logic control submodule and a first transistor, the first logic control submodule is configured to control the first transistor to be turned on or turned off, a power supply end of the first logic control submodule is configured to be electrically connected to the first voltage source, the power supply end of the first logic control submodule is electrically connected to the source of the first transistor, the gate of the first transistor is electrically connected to the control end of the first logic control submodule, the drain of the first transistor is electrically connected to the source of the drive transistor, and the floating ground end of the first logic control submodule is electrically connected to the first end of the floating ground adjusting module.

[0034] Specifically, the first logic control submodule and the first transistor are configured to drive the drive transistor.

[0035] In an embodiment of the present application, the second drive module comprises a second logic control submodule and a second transistor, the second logic control submodule is configured to control the second transistor to be turned on or turned off, a power supply end of the second logic control submodule is electrically connected to the second voltage source, a control end of the second logic control submodule is electrically connected to the gate of the second transistor, a ground end of the second logic control submodule is respectively grounded, and the drain of the second transistor is electrically connected to the drain of the drive transistor.

[0036] Specifically, the first logic control submodule and the second logic control submodule can be implemented by using a chip internal circuit capable of generating a non-overlapping clock control signal, the first logic control submodule, the first transistor, the second logic control submodule and the second transistor constitute a double control drive structure to drive the drive transistor, and the peak current precision of the drive transistor is improved.

[0037] In an embodiment of the present application, the margin adjustment unit further comprises a first biasing module, a second biasing module and a first current source; a first end of the first biasing module is electrically connected to the first voltage source, a second end of the first biasing module is electrically connected to a third end of the floating ground adjustment module, and the first biasing module is configured to provide a first biasing voltage drop for the floating ground adjustment module; a first end of the second biasing module is electrically connected to the first voltage source, a second end of the second biasing module is electrically connected to a third end of the first biasing module, a third end of the second biasing module is electrically connected to a fourth end of the first biasing module, a fourth end of the second biasing module is electrically connected to the gate of the driving transistor, and the second biasing module is configured to provide a second biasing voltage drop for the gate of the driving transistor; and the first current source is electrically connected to the fourth end of the first biasing module.

[0038] Specifically, the first biasing module provides a first biasing voltage drop for the floating ground adjustment module, thereby improving the gate voltage margin of the transistor, and the second biasing module is a CLASS-AB structure, which provides a DC bias for the M0 transistor and provides source current and sink current when the bias voltage changes, thereby supplementing the charge of the parasitic capacitors Cgs and Cgd.

[0039] In an embodiment of the present application, the floating ground adjustment module comprises a third transistor, a first resistance module and a second resistance module; a source of the third transistor is electrically connected to a first end of the first resistance module and a floating ground end of the first driving module; a drain of the third transistor is electrically connected to a first end of the second resistance module; a gate of the third transistor is electrically connected to a second end of the first biasing module; a second end of the first resistance module is electrically connected to the first voltage source; and a second end of the second resistance module is grounded.

[0040] Specifically, the first resistance module and the second resistance module function as voltage stabilizers, and the third transistor delivers the first biasing voltage drop to FGND, thereby improving the voltage swing of the gate of the SRC transistor when the SRC transistor is turned on; the swing of the existing solution is VDD to FGND+VTH0, and the swing of the present application is VDD to FGND, which improves the absolute value of the voltage difference between VDD and FGND.

[0041] In an embodiment of the present application, the first biasing module comprises a fourth transistor, a fifth transistor and a third resistance module, a gate of the fourth transistor is electrically connected with a drain of the fourth transistor, a gate of the fifth transistor, a drain of the fifth transistor and a third terminal of the floating ground adjusting module respectively, a source of the fifth transistor is electrically connected with a first terminal of the first current source, a second terminal of the first current source is grounded, a source of the fourth transistor is electrically connected with a first terminal of the third resistance module, and a second terminal of the third resistance module is electrically connected with the first voltage source.

[0042] Specifically, by adding the fourth transistor and the fifth transistor, the peak current capability of the transistor is independent of the driving voltage of the driving transistor, i.e., V PG The gate driving voltage of the transistor has a larger voltage margin.

[0043] In an embodiment of the present application, the second biasing module comprises a sixth transistor and a seventh transistor, a source of the sixth transistor is electrically connected with a source of the seventh transistor and a gate of the driving transistor respectively, a drain of the sixth transistor is electrically connected with the first voltage source, a gate of the sixth transistor is electrically connected with a third terminal of the first biasing module, a gate of the seventh transistor is electrically connected with the third terminal of the first biasing module, and a drain of the seventh transistor is grounded.

[0044] The sixth transistor and the seventh transistor constitute a CLASS-AB structure, provide DC bias for the M0 transistor, and provide source current and sink current when the bias voltage changes, and supplement charges for the parasitic capacitances Cgs and Cgd.

[0045] In an embodiment of the present application, the driving transistor is a P-type MOS transistor structure.

[0046] Taking the high-side driving as an example, as shown in Figure 2 and Figure 3 The gate driving circuit comprises:

[0047] a high-side transistor SRC, a source of the high-side transistor SRC is electrically connected with the first voltage source VDD, and a drain of the high-side transistor SRC is used to be electrically connected with a driven device;

[0048] a high-side margin adjusting unit 100, which is electrically connected with a gate of the high-side transistor SRC, and is used to improve a voltage margin of the gate of the high-side transistor SRC;

[0049] as shown in Figure 2 and Figure 3As shown, the high-side margin adjustment unit 100 includes a high-side drive transistor M0, a first high-side drive module 110, a second high-side drive module 120, a floating ground adjustment module 130, a first bias module 140, and a second bias module 150. The high-side margin adjustment unit 100 further includes a first parasitic capacitor C gd and a second parasitic capacitor C gs ;

[0050] The capacitances of the two parasitic capacitors are not changed compared with the prior art. The application improves the charging speed of the two parasitic capacitors. The structure of the prior art has a small source current and a large sink current because the resistor is on the top. Therefore, the charging speed of the two parasitic capacitors is fast and slow when turned on and off, which causes voltage glitch to affect the accuracy. The application changes to a CLASS-AB structure, so that the source current and the sink current are large. Therefore, the charging of the parasitic capacitors is fast. Similarly, on the low side, the source current is large and the sink current is small.

[0051] The gate of the high-side drive transistor M0 is electrically connected to the high-side transistor SRC. The first end of the first high-side drive module 110 is electrically connected to the source of the high-side drive transistor M0. The second end of the first high-side drive module 110 is electrically connected to the first voltage source VDD. The second high-side drive module 120 is electrically connected to the drain of the high-side drive transistor M0. The first end of the floating ground adjustment module 130 is electrically connected to the floating ground end FGND of the first high-side drive module 110. The second end of the floating ground adjustment module 130 is electrically connected to the voltage source. The floating ground adjustment module 130 is used to adjust the voltage of the floating ground end FGND of the first high-side drive module 110. The first end of the first bias module 140 is electrically connected to the first voltage source VDD. The second end of the first bias module 140 is electrically connected to the third end of the floating ground adjustment module 130. The first bias module 140 is used to provide a first bias voltage drop for the floating ground adjustment module 130. The first end of the second bias module 150 is electrically connected to the first voltage source VDD. The second end of the second bias module 150 is electrically connected to the third end of the first bias module 140. The third end of the second bias module 150 is electrically connected to the fourth end of the first bias module 140. The fourth end of the second bias module 150 is electrically connected to the gate of the high-side drive transistor M0. The second bias module 150 is used to provide a second bias voltage drop for the gate of the high-side drive transistor M0. The first current source IB1 is electrically connected to the fourth end of the first bias module 140.

[0052] The floating ground adjusting module is added, so that the voltage of the floating ground end of the first driving module is adjusted, the gate voltage margin of the transistor is improved, and the problem of low gate voltage margin of the high side and low side transistors in the driving IC circuit in the prior art is solved.

[0053] As shown in Figure 2 and Figure 3 The first high side driving module 110 includes a first logic control submodule Q1 and a first transistor A, the first logic control submodule Q1 is used for controlling the first transistor A to be turned on or turned off, the power supply end of the first logic control submodule Q1 is electrically connected with the first voltage source VDD and the source of the first transistor A respectively, the gate of the first transistor A is electrically connected with the control end of the first logic control submodule Q1, the drain of the first transistor A is electrically connected with the source of the high side driving transistor M0, and the floating ground end FGND of the first logic control submodule Q1 is electrically connected with the first end of the floating ground adjusting module 130.

[0054] As shown in Figure 2 and Figure 3 The second high side driving module 120 includes a second logic control submodule Q2 and a second transistor B, the second logic control submodule Q2 is used for controlling the second transistor B to be turned on or turned off, the power supply end of the second logic control submodule Q2 is electrically connected with the second voltage source FVDD, the control end of the second logic control submodule Q2 is electrically connected with the gate of the second transistor B, the ground end of the second logic control submodule Q2 is grounded respectively with the source of the second transistor B, and the drain of the second transistor B is electrically connected with the drain of the high side driving transistor M0.

[0055] As shown in Figure 2 and Figure 3 The floating ground adjusting module 130 includes a third transistor MQ3, a first resistance module R1 and a second resistance module R2, the source of the third transistor MQ3 is electrically connected with the first end of the first resistance module R1 and the floating ground end FGND of the first high side driving module 110 respectively, the drain of the third transistor MQ3 is electrically connected with the first end of the second resistance module R2, the gate of the third transistor MQ3 is electrically connected with the second end of the first biasing module 140, the second end of the first resistance module R1 is electrically connected with the first voltage source VDD, and the second end of the second resistance module R2 is grounded.

[0056] As shown in Figure 2 and Figure 3As shown in the above first bias module 140 includes a fourth transistor MQ4, a fifth transistor MQ5 and a third resistance module R3, the gate of the fourth transistor MQ4 is electrically connected with the drain of the fourth transistor MQ4, the gate of the fifth transistor MQ5, the drain of the fifth transistor MQ5 and the third end of the floating ground adjusting module 130 respectively, the source of the fifth transistor MQ5 is electrically connected with the first end of the first current source IB1, the second end of the first current source IB1 is grounded, the source of the fourth transistor MQ4 is electrically connected with the first end of the third resistance module R3, and the second end of the third resistance module R3 is electrically connected with the first voltage source VDD.

[0057] As shown in the above first bias module 140 includes a fourth transistor MQ4, a fifth transistor MQ5 and a third resistance module R3, the gate of the fourth transistor MQ4 is electrically connected with the drain of the fourth transistor MQ4, the gate of the fifth transistor MQ5, the drain of the fifth transistor MQ5 and the third end of the floating ground adjusting module 130 respectively, the source of the fifth transistor MQ5 is electrically connected with the first end of the first current source IB1, the second end of the first current source IB1 is grounded, the source of the fourth transistor MQ4 is electrically connected with the first end of the third resistance module R3, and the second end of the third resistance module R3 is electrically connected with the first voltage source VDD. Figure 2 and Figure 3 As shown in the above first bias module 140 includes a fourth transistor MQ4, a fifth transistor MQ5 and a third resistance module R3, the gate of the fourth transistor MQ4 is electrically connected with the drain of the fourth transistor MQ4, the gate of the fifth transistor MQ5, the drain of the fifth transistor MQ5 and the third end of the floating ground adjusting module 130 respectively, the source of the fifth transistor MQ5 is electrically connected with the first end of the first current source IB1, the second end of the first current source IB1 is grounded, the source of the fourth transistor MQ4 is electrically connected with the first end of the third resistance module R3, and the second end of the third resistance module R3 is electrically connected with the first voltage source VDD.

[0058] MQ4, MQ5 fixed bias voltage drop, MQ6 and MQ7 bias voltage drop, as shown in the above first bias module 140 includes a fourth transistor MQ4, a fifth transistor MQ5 and a third resistance module R3, the gate of the fourth transistor MQ4 is electrically connected with the drain of the fourth transistor MQ4, the gate of the fifth transistor MQ5, the drain of the fifth transistor MQ5 and the third end of the floating ground adjusting module 130 respectively, the source of the fifth transistor MQ5 is electrically connected with the first end of the first current source IB1, the second end of the first current source IB1 is grounded, the source of the fourth transistor MQ4 is electrically connected with the first end of the third resistance module R3, and the second end of the third resistance module R3 is electrically connected with the first voltage source VDD. Figure 2 and Figure 3 As shown in the above first bias module 140 includes a fourth transistor MQ4, a fifth transistor MQ5 and a third resistance module R3, the gate of the fourth transistor MQ4 is electrically connected with the drain of the fourth transistor MQ4, the gate of the fifth transistor MQ5, the drain of the fifth transistor MQ5 and the third end of the floating ground adjusting module 130 respectively, the source of the fifth transistor MQ5 is electrically connected with the first end of the first current source IB1, the second end of the first current source IB1 is grounded, the source of the fourth transistor MQ4 is electrically connected with the first end of the third resistance module R3, and the second end of the third resistance module R3 is electrically connected with the first voltage source VDD. G6 = VDD - R3 x Ib1, V G7 = VDD - R3 x Ib1 - Vgs4 - Vgs5, Vgs4 is the voltage difference between the gate and the source of the MQ4 tube, Vgs5 is the voltage difference between the gate and the source of the MQ5 tube, V G6 is the voltage of the gate of the MQ6 tube, V G7 is the voltage of the gate of the MQ7 tube, the gate of M0 can obtain source and sink current respectively when the SRC tube is turned on and off,

[0059] Let Vgs6 = Vgs7, then ΔVBP(source) = ΔVBP(sink), so as to reduce the glitch of VBP voltage, thereby obtaining more stable peak driving capability, as shown in the above first bias module 140 includes a fourth transistor MQ4, a fifth transistor MQ5 and a third resistance module R3, the gate of the fourth transistor MQ4 is electrically connected with the drain of the fourth transistor MQ4, the gate of the fifth transistor MQ5, the drain of the fifth transistor MQ5 and the third end of the floating ground adjusting module 130 respectively, the source of the fifth transistor MQ5 is electrically connected with the first end of the first current source IB1, the second end of the first current source IB1 is grounded, the source of the fourth transistor MQ4 is electrically connected with the first end of the third resistance module R3, and the second end of the third resistance module R3 is electrically connected with the first voltage source VDD. Figure 4As shown, the voltage fluctuation generated when the SRC tube is turned on and off is coupled to VBP through the parasitic capacitance, at which time the MQ6 tube and the MQ7 tube can timely supplement the charge for the parasitic capacitance, thereby reducing the voltage fluctuation.

[0060] Secondly, since the fourth transistor MQ4 and the fifth transistor MQ5 are added in the first biasing module, and the intermediate point voltage of the fourth transistor MQ4 and the fifth transistor MQ5 is taken as the biasing voltage of the MQ3, then V FGND = VDD - IB1 x R3 - Vgs4 + Vgs3, V PG = VDD - IB1 x R3 - V gs6 + V gs0 ,

[0061] So that V gs0 = Vgs3, V gs6 = Vgs4; V gs0 is the voltage difference between the gate end and the source end of the M0 tube;

[0062] Then V PG = V FGND , I SRC = K (VDD - V FGND - V TSRC ) 2 ;

[0063] At this time, the peak current capability of the SRC tube is irrelevant to the overdrive voltage of the M0, that is, V PG has a larger voltage margin.

[0064] Low-side drive: the gate drive circuit further comprises a low-side transistor SNK, a low-side drive transistor M1, a third logic control submodule Q3, a fourth logic control submodule Q4, an eighth transistor C, a ninth transistor D, a tenth transistor MQ8, an eleventh transistor MQ9, a twelfth transistor MQ10, a thirteenth transistor MQ11, a fourteenth transistor MQ12, a fourth resistance module R4, a fifth resistance module R5, a sixth resistance module R6, and a second current source IB2, and the connection mode is as shown in Figure 3 As shown, because the low-side drive and the high-side drive have the same principle, and the low-side drive is a mirror circuit of the high-side drive, here, the FVDD and the FGND have the same working principle, and a local fixed bias is generated through a source follow structure in the low side to provide power supply for the Q2 and Q4 logic units, so that when the low-side SNK is turned on, the swing of the gate is GND to FVDD, which is symmetrical with the swing of the gate of the SRC tube of the high side VDD to FGND.

[0065] The application further provides a gate drive system, which comprises any one of the above-mentioned gate drive circuits.

[0066] It should be noted that the above electrical connection can be direct electrical connection or indirect electrical connection, direct electrical connection means that two devices are directly connected, indirect electrical connection means that A and B connected are connected with other similar devices such as capacitors and resistors.

[0067] It should also be noted that the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, product or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, product or equipment including the element.

[0068] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

[0069] The gate drive circuit of the present application adds a floating ground adjustment module, thereby achieving the purpose of adjusting the voltage of the floating ground end of the first drive module, improving the gate voltage margin of the transistor, and solving the problem of low gate voltage margin of the high side and low side transistors in the existing drive IC circuit.

[0070] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A gate drive circuit characterized by comprising: The application relates to a voltage source driving circuit, comprising: a transistor, a source of the transistor being electrically connected with a first voltage source, a drain of the transistor being electrically connected with a driven device; a margin adjusting unit, comprising: a driving transistor, a source of the driving transistor being electrically connected with a gate of the transistor; a first driving module, a first end of the first driving module being electrically connected with a source of the driving transistor, a second end of the first driving module being electrically connected with the first voltage source, the first driving module being used for driving the driving transistor; a floating ground adjusting module, a first end of the floating ground adjusting module being electrically connected with a floating ground end of the first driving module, a second end of the floating ground adjusting module being electrically connected with the voltage source, the floating ground adjusting module being used for adjusting a voltage of the floating ground end of the first driving module; a first biasing module, a first end of the first biasing module being electrically connected with the first voltage source, a second end of the first biasing module being electrically connected with a third end of the floating ground adjusting module, the first biasing module being used for providing a first biasing voltage drop for the floating ground adjusting module; a second biasing module, a first end of the second biasing module being electrically connected with the first voltage source, a second end of the second biasing module being electrically connected with a third end of the first biasing module, a third end of the second biasing module being electrically connected with a fourth end of the first biasing module, a fourth end of the second biasing module being electrically connected with a gate of the driving transistor, the second biasing module being used for providing a second biasing voltage drop for the gate of the driving transistor; a first current source, the first current source being electrically connected with the fourth end of the first biasing module.

2. The gate drive circuit according to claim 1, characterized by The margin adjusting unit further comprises: a second driving module, the second driving module being electrically connected with a drain of the driving transistor, the second driving module being used for driving the driving transistor.

3. The gate drive circuit according to claim 1, characterized by The first driving module comprises a first logic control submodule and a first transistor, the first logic control submodule being used for controlling the first transistor to be turned on or turned off, a power supply end of the first logic control submodule being electrically connected with the first voltage source, the power supply end of the first logic control submodule being electrically connected with a source of the first transistor, a gate of the first transistor being electrically connected with a control end of the first logic control submodule, a drain of the first transistor being electrically connected with a source of the driving transistor, and a floating ground end of the first logic control submodule being electrically connected with a first end of the floating ground adjusting module.

4. The gate drive circuit according to claim 2, characterized by The second driving module comprises a second logic control submodule and a second transistor, the second logic control submodule being used for controlling the second transistor to be turned on or turned off, a power supply end of the second logic control submodule being electrically connected with a second voltage source, a control end of the second logic control submodule being electrically connected with a gate of the second transistor, a ground end of the second logic control submodule being respectively grounded, and a drain of the second transistor being electrically connected with a drain of the driving transistor.

5. The gate drive circuit according to claim 1, characterized by The floating ground adjusting module comprises a third transistor, a first resistance module and a second resistance module, the source of the third transistor is electrically connected with the first end of the first resistance module and the floating ground end of the first driving module respectively, the drain of the third transistor is electrically connected with the first end of the second resistance module, the gate of the third transistor is electrically connected with the second end of the first biasing module, the second end of the first resistance module is electrically connected with the first voltage source, and the second end of the second resistance module is grounded.

6. The gate drive circuit according to claim 1, characterized by The first biasing module comprises a fourth transistor, a fifth transistor and a third resistance module, the gate of the fourth transistor is electrically connected with the drain of the fourth transistor, the gate of the fifth transistor, the drain of the fifth transistor and the third end of the floating ground adjusting module respectively, the source of the fifth transistor is electrically connected with the first end of the first current source, the second end of the first current source is grounded, the source of the fourth transistor is electrically connected with the first end of the third resistance module, and the second end of the third resistance module is electrically connected with the first voltage source.

7. The gate drive circuit according to claim 1, wherein The second biasing module comprises a sixth transistor and a seventh transistor, the source of the sixth transistor is electrically connected with the source of the seventh transistor and the gate of the driving transistor respectively, the drain of the sixth transistor is electrically connected with the first voltage source, the gate of the sixth transistor is electrically connected with the third end of the first biasing module, the gate of the seventh transistor is electrically connected with the third end of the first biasing module, and the drain of the seventh transistor is grounded.

8. The gate drive circuit according to any one of claims 1 to 7, characterized by, The driving transistor is a P-type MOS tube structure.

9. A gate drive system characterized by, The gate driving circuit comprises the gate driving circuit according to any one of claims 1 to 7. The gate driving circuit comprises the gate driving circuit according to any one of claims 1 to 7.

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